Relevant bibliographies by topics / Microprocessors – Power supply

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Microprocessors – Power supply'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 February 2022

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Journal articles on the topic "Microprocessors – Power supply"

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Sulaiman, Diary R. "Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 6 (December 1, 2020): 6549. http://dx.doi.org/10.11591/ijece.v10i6.pp6549-6557.

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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.
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Sulaiman, Diary, Ibrahim Hamarash, and Muhammed Ibrahim. "Adaptive supply and body voltage control for ultra-low power microprocessors." IEICE Electronics Express 14, no. 12 (2017): 20170306. http://dx.doi.org/10.1587/elex.14.20170306.

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Saint-Laurent, M., and M. Swaminathan. "Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors." IEEE Transactions on Advanced Packaging 27, no. 1 (February 2004): 135–44. http://dx.doi.org/10.1109/tadvp.2004.825480.

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Bleckmann, H.-W., and L. Weise. "The New Four-Wheel Anti-Lock Generation: A Compact Anti-Lock and Booster Aggregate and an Advanced Electronic Safety Concept." Proceedings of the Institution of Mechanical Engineers, Part D: Transport Engineering 200, no. 4 (October 1986): 275–82. http://dx.doi.org/10.1243/pime_proc_1986_200_191_02.

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An overview is given on hydraulic anti-lock systems with direrent pedal characteristics, power supply concepts, and physical configurations suitable for ‘add-on’ installation or functional integration. The integrated Teves anti-skid system is presented with special attention to a three-circuit configuration including ‘dynamic’ brake circuits. Different safety levels of electronic concepts compared to the advanced Teves approach, and the application of microprocessors are discussed.
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Habib, H., N. G. Wright, and A. B. Horsfall. "Complementary JFET Logic for Low-Power Applications in Extreme Environments." Materials Science Forum 740-742 (January 2013): 1052–55. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1052.

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The static and dynamic characteristics of Complementary JFET (CJFET) logic inverter are studied across a range of temperatures and supply voltages to assess potential improvements in performance of digital logic functions for operation in extreme environments. The logic inverter is truly the core of all digital designs. The design and analysis of inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. At 500 deg C and operating at a supply voltage of 1 V, the CJFET inverter have noise margin comparable to that of room temperature silicon and silicon on insulator CMOS inverters. Furthermore, the static power dissipation by CJFET inverter at 500 deg C is 20.6 nW which is six orders of magnitude lower than that by current SiC technologies, making CJFET technology ideal for achieving complex logic functions, far greater than a few-transistors ICs, in the nearer term.
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Majerus, Steve, Daniel Howe, Steven Garverick, David Hiscock, and Walter Merrill. "High-Temperature, Bulk-CMOS Integrated Circuits for a Distributed FADEC System." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000047–53. http://dx.doi.org/10.4071/hitec-dhowe-ta22.

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The greatest roadblock to distributed engine control development is the lack of high-temperature, high-reliability electronic components. Four integrated circuits (ICs) have been developed to provide sensing, actuation, and power conversion capabilities in a high-temperature (over 150°C) environment. Patented high-temperature techniques facilitate designs in a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The HHT104 eight-channel instrumentation IC measures LVDTs, RTDs, thermocouples, and other sensors with up to 12-bit resolution. Dual sigma-delta converters and independent, programmable gain allow simultaneous conversion of two differential-output sensors. A stimulus driver may be used to drive bridge sensors with AC excitation and a temperature-stabilized oscillator provides 1.5- and 24-MHz system clocks for microprocessor use. The HHT212 current driver IC may be used to control two motors in full-bridge configuration or four independent half-bridge loads. Each channel is capable of driving up to 300 mA with 12-bit resolution. An internally-generated, temperature-stabilized current reference minimizes external components. The output current is programmed using a SPI serial interface, and the chip has built-in over-current and over-temperature protection. The HHT250 is a quad load driver featuring an integrated PWM controller, push-pull outputs and flexible drive capability. The HHT300 quad-output switched-mode power supply IC implements a compact power solution for multi-voltage microprocessors, sensors, and actuators. The external part count is minimized using integrated output FETs and a novel voltage feedback topology. Synchronous rectification reduces power dissipation and improves current capacity. Each channel has a pin-programmable output voltage and may be independently enabled for power supply sequencing.
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LIU, YUYU, JINGUO QUAN, HUAZHONG YANG, and HUI WANG. "MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL." International Journal of High Speed Electronics and Systems 15, no. 03 (September 2005): 599–614. http://dx.doi.org/10.1142/s0129156405003351.

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In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.
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Howe, Dan, Steve Majerus, Steve Garverick, Walter Merrill, and Ken Semega. "High-Temperature, Bulk-CMOS Integrated Circuits for a Distributed Control System-Performance Results." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000002–9. http://dx.doi.org/10.4071/hitec-2012-ta11.

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Four integrated circuits (ICs) have been developed to provide sensing, actuation, and power conversion capabilities in a high-temperature (200 °C) distributed control environment. Patented high-temperature techniques facilitate designs in a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The HHT104 eight-channel instrumentation IC measures LVDTs, RTDs, thermocouples, and other sensors with up to 12-bit resolution. Dual sigma-delta converters and independent, programmable gain allow simultaneous conversion of two differential-output sensors. A stimulus driver may be used to drive bridge sensors with AC excitation and a temperature-stabilized oscillator provides 1.5- and 24-MHz system clocks for microprocessor use. The HHT212 current driver IC may be used to control two motors in full-bridge configuration or four independent half-bridge loads. Each channel is capable of driving up to 300 mA with 12-bit resolution. An internally-generated, temperature-stabilized current reference minimizes external components. The output current is programmed using a SPI serial interface, and the chip has built-in over-current and over-temperature protection. The HHT250 is a quad load driver featuring an integrated PWM controller, push-pull outputs and flexible drive capability. The HHT300 quad-output switched-mode power supply IC implements a compact power solution for multi-voltage microprocessors, sensors, and actuators. The external part count is minimized using integrated output FETs and a novel voltage feedback topology. Synchronous rectification reduces power dissipation and improves current capacity. Each channel has a pin-programmable output voltage and may be independently enabled for power supply sequencing. A high-temperature development system has been created using the four ICs and a DSP for actuator controller prototypes. A reference application was implemented using this system to drive a torque motor using LVDT position feedback.
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Elbouchikhi, Elhoussin, Yassine Amirat, Gilles Feld, Mohamed Benbouzid, and Zhibin Zhou. "A Lab-scale Flywheel Energy Storage System: Control Strategy and Domestic Applications." Energies 13, no. 3 (February 4, 2020): 653. http://dx.doi.org/10.3390/en13030653.

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Flywheel is a promising energy storage system for domestic application, uninterruptible power supply, traction applications, electric vehicle charging stations, and even for smart grids. In fact, recent developments in materials, electrical machines, power electronics, magnetic bearings, and microprocessors offer the possibility to consider flywheels as a competitive option for electric energy storage, which can be of great interest for domestic applications in the near future. In this paper, a grid-tied flywheel-based energy storage system (FESS) for domestic application is investigated with special focus on the associated power electronics control and energy management. In particular, the overall PMSM-based flywheel configuration is reviewed and a controlling strategy was experimentally implemented using DS1104 controller board from dSPACE. Two case studies were considered for power peak shaving and power backup at domestic level. A lab-scale prototype was built to validate the proposal. The achieved results are presented and discussed to demonstrate the possibilities offered by such an energy storage system for domestic application.
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Goodman, C. J., and J. A. Taufiq. "Supply-Side Harmonics in d.c. Supplied Drives: An Approach to Their Specification and Control." Proceedings of the Institution of Mechanical Engineers, Part F: Journal of Rail and Rapid Transit 203, no. 1 (January 1989): 45–49. http://dx.doi.org/10.1243/pime_proc_1989_203_207_02.

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The use of power electronic switching controllers for all types of traction drives can lead to harmonic currents on the supply side. These currents, by conductive or mutual coupling, can cause interference in signalling and telecommunications circuits. After reviewing these basic considerations, this paper outlines the harmonic spectra of d.c.-supplied chopper and inverter drives. In the case of chopper controllers, choosing a frequency unrelated to any signalling frequency combined with the attenuation provided by the input filter is usually sufficient to avoid dangerous interference. For inverter drives, the situation is more complex due to the intrinsic sweep frequency nature of the drive. However, special modulation strategies can be used for the inverter which eliminates, or at least reduces to a safe level, any particular frequency which may interfere with signalling equipment. A method for generating these optimized pulse-width modulation schemes using fast on-board microprocessors is briefly described.
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Dissertations / Theses on the topic "Microprocessors – Power supply"

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López, Julià Toni. "Prospects of voltage regulators for next generation computer microprocessors." Doctoral thesis, Universitat Politècnica de Catalunya, 2010. http://hdl.handle.net/10803/77908.

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Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.
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Healy, Michael Benjamin. "Physical design for performance and thermal and power-supply reliability in modern 2D and 3D microarchitectures." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37093.

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The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010. The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature. The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology. The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.
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Roy, Soumyaroop. "A compiler-based leakage reduction technique by power-gating functional units in embedded microprocessors." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001832.

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Huang, Gang. "Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26619.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Meindl, James D.; Committee Member: Bakir, Muhannad S.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Kohl, Paul A.; Committee Member: Naeemi, Azad. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Siddique, Nafiul Alam. "Spare Block Cache Architecture to Enable Low-Voltage Operation." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/216.

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Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.
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Tate, D. "A microprocessor controlled error switching inverter used in the uninterruptible power supply environment." Thesis, University of Bath, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.275883.

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Klejma, Michael. "Svářečka MIG/MAG se spínaným zdrojem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318095.

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This diploma thesis deals with design of welding power supply for MIG / MAG and MMA technique with continuous output current 120 A. The first, theoretical part is devoted to welding process technology, physical characteristics of electric arc and description of individual welding methods. The thesis also deals with the concept of power converter. The design of the switched-mode power supply is based on a full bridge topology. In order to implement advanced controls of welding power supply, the ARM Cortex M4 microprocessor was selected. Due to the large power consumption of the stepper motor for drive the welding wire, an auxiliary switched-mode power supply was also implemented. The documentation describing the realization of the welding power supply and the results of the measurements are in the last part of the thesis. The welding power supply was successfully revived and reached nominal parameters. Inert gas welding has not been tested yet, due to lack of time caused by extensive work in order to complete mechanical realization.
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Kincl, Zdeněk. "Multifunkční display pro pozemní zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217990.

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The aim of this thesis was to design a concept and circuit for multifunction display. This unit is used in ground power supply for preflighting preparation of army helicopters. Multifunction display measures voltages and currents of AC and DC generators, teperatures of cooling air and fuel quantity. Display indicates a operational and fault states of ground power supply. The main element of multifunction display is 32-bit microprocessor from the manufacturer NXP, family ARM7. All information are displaying on graphic vacuum fluorescent display GU256x128.
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Sambamurthy, Sriram. "Power estimation of microprocessors." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-08-1907.

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The widespread use of microprocessor chips in high performance applications like graphics simulators and low power applications like mobile phones, laptops, medical applications etc. has made power estimation an important step in the manufacture of VLSI chips. It has become necessary to estimate the power consumption not only after the circuits have been laid out, but also during the design of the modules of the microprocessor at higher levels of design abstraction. The design of a microprocessor is complex and is performed at multiple layers of abstraction before it finally gets manufactured. The processor is first conceptually designed using blocks at the system level, and then modeled using a high-level language (C, C++, SystemC). This enables the early development of software applications using these high-level models. The C/C++ model is then translated to a hardware description language (HDL), that typically corresponds to the register transfer level (RT-Level). Once the processor is defined at the RT-Level, it is synthesized into gates and state elements based on user-defined constraints. In this thesis, novel techniques to estimate the power consumed by the microprocessor circuits at the gate level and RT-level of abstraction are presented. At the gate level, the average power consumed by microprocessor circuits is straight-forward to estimate, as the implementation is known. However, estimating the maximum or peak instantaneous power consumed by the microprocessor as a whole, when it is executing instructions, is a hard problem due to the high complexity of the state space involved. An hierarchical approach to estimate the peak power using powerful search techniques and formal tools is presented in this thesis. This approach has been extended and applied to solve the problem of estimating the maximum supply drop. Details on this extension and a discussion of promising results are also presented. In addition, this approach has been applied to explore the possibility of minimizing the leakage component of power dissipation, when the processor is idle. At the register transfer level, estimating the average power consumed by the circuits of the microprocessor is by itself a challenging problem. This is due to the fact that their implementation is unknown at this level of abstraction. The average power consumption directly depends on the implementation. The implementation, in turn, depends on the performance constraint imposed on the microprocessor. One of the factors affecting the performance of the microprocessor, is the speed of operation of its circuits. Considering these factors and dependencies (for making early design decisions at the RT-Level), a methodology that estimates the power vs. delay curves of microprocessor circuits has been developed. This will enable designers to make design decisions for even rudimentary designs without going through the time consuming process of synthesis.
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Books on the topic "Microprocessors – Power supply"

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P, Singh L. Digital protection: Protective relaying from electromechanical to microprocessor. New York: Wiley, 1994.

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P, Singh L. Digital protection: Protective relaying from electromechanical to microprocessor. 2nd ed. New Delhi: New Age International (P) Ltd., Publishers, 1997.

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Goremykin, Sergey. Relay protection and automation of electric power systems. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1048841.

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The textbook describes the main issues of the theory of relay protection and automation of electric power systems. The structure and functional purpose of protection devices and automation of power transmission lines of various configurations, synchronous generators, power transformers, electric motors and individual electrical installations are considered. For each of the types of protection of the above objects, the structure, the principle of operation, the order of selection of settings are given, the advantages and disadvantages are evaluated, indicating the scope of application. The manual includes material on complete devices based on semiconductor and microprocessor element bases. The progressive use of such devices (protection of the third and fourth generations) is appropriate and effective due to their significant advantages. Meets the requirements of the federal state educational standards of higher education of the latest generation. It is intended for students in the areas of training 13.03.02 "Electric power and electrical engineering" (profile "Power supply", discipline "Relay protection and automation of electric power systems") and 35.03.06 "Agroengineering" (profile "Power supply and electrical equipment of agricultural enterprises", discipline "Relay protection of electrical equipment of agricultural objects"), as well as for graduate students and specialists engaged in the field of electrification and automation of industrial and agrotechnical objects.
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Low-Power Processors and Systems on Chips. CRC, 2005.

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Book chapters on the topic "Microprocessors – Power supply"

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Maćkowski, Michał, and Krzysztof Skoroniak. "Instruction Prediction in Microprocessor Unit Based on Power Supply Line." In Computer Networks, 173–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13861-4_17.

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Weckx, Pieter, Nele Reynders, Ilse de Moffarts, and Wim Dehaene. "Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor." In Lecture Notes in Computer Science, 175–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36157-9_18.

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Okafor, Patrick Uche, Ndidi Stella Arinze, Osondu Ignatius Onah, and Ebenezer Nnajiofo Ogbodo. "Development of Solar-Powered Microcontroller-Relay-Based Control System Omnidirectional Wheelchair." In Handbook of Research on 5G Networks and Advancements in Computing, Electronics, and Electrical Engineering, 181–91. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6992-4.ch007.

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A solar-powered omnidirectional wheelchair is implemented for physically challenged persons. The framework was mounted on the wheels that were connected with two direct current (DC) motors. The ratings of the battery and solar module were determined using system voltage (12V). A 7,805-voltage regulator was used to supply 5VDC to the AT89352 microcontroller. The microcontroller was programmed to provide a reference signal to the motor. The motor provides the needed torque to drive the wheels through interconnected relays. The relays are energized by the microcontroller and omnidirectional movement achieved through relays connected with microprocessor and micro switches, eliminating the need for joysticks and complex control mechanisms. System performance test result showed that the auxiliary solar power supply of the wheelchair increased the travel range by approximately 86% compared with that of a wheelchair powered by battery alone.
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Conference papers on the topic "Microprocessors – Power supply"

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Vijayakumar, Arunkumar, Raghavan Kumar, and Sandip Kundu. "On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors." In 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2012. http://dx.doi.org/10.1109/isvlsi.2012.32.

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Wang, Kanwen, Hao Yu, Benfei Wang, and Chun Zhang. "3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.333.

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Shrivastava, Saurabh, Bahgat Sammakia, Roger Schmidt, and Madhusudan Iyengar. "Comparative Analysis of Different Data Center Airflow Management Configurations." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73234.

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Increase in computing power resulting from high performance microprocessors, packages, and modules and the deployment of high heat load computer rack units in high density configurations, has escalated the thermal challenges in today’s data center systems. One of the key issues is the location of hot recirculation regions in the room and the mixing of hot rack exhaust air with the cold supply air. Along with many factors such as the rack heat load and the cooling capacity of the supply air, the data center thermal management architecture plays an important role in determining the reliability of the electronic equipment and the general thermal performance of the data center. There are several candidate configurations available for the air ducting designs for data centers. The overall energy efficiency of the system is highly dependant upon the selection of the specific configuration. This paper will summarize the results of a broad numerical study carried out to assess the effectiveness of different data center configurations. The numerical modeling is performed using a commercial computational fluid dynamics (CFD) code based on finite volume approach. The configurations studied include different combinations of raised floor and ceiling supply and return vent location subject to specific constraints. The performance of the data center has been characterized on the basis of average and maximum mean region rack inlet air temperature. Among the seven different configurations compared, the raised floor/ceiling return type configuration is found to be the most effective configuration for the given set of constraints and assumptions.
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Adera, Solomon, Rishi Raj, and Evelyn N. Wang. "Capillary-Limited Evaporation From Well-Defined Microstructured Surfaces." In ASME 2013 4th International Conference on Micro/Nanoscale Heat and Mass Transfer. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/mnhmt2013-22120.

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Thermal management is increasingly becoming a bottleneck for a variety of high power density applications such as integrated circuits, solar cells, microprocessors, and energy conversion devices. The performance and reliability of these devices are usually limited by the rate at which heat can be removed from the device footprint, which averages well above 100 W/cm2 (locally this heat flux can exceed 1000 W/cm2). State-of-the-art air cooling strategies which utilize the sensible heat are insufficient at these large heat fluxes. As a result, novel thermal management solutions such as via thin-film evaporation that utilize the latent heat of vaporization of a fluid are needed. The high latent heat of vaporization associated with typical liquid-vapor phase change phenomena allows significant heat transfer with small temperature rise. In this work, we demonstrate a promising thermal management approach where square arrays of cylindrical micropillar arrays are used for thin-film evaporation. The microstructures control the liquid film thickness and the associated thermal resistance in addition to maintaining a continuous liquid supply via the capillary pumping mechanism. When the capillary-induced liquid supply mechanism cannot deliver sufficient liquid for phase change heat transfer, the critical heat flux is reached and dryout occurs. This capillary limitation on thin-film evaporation was experimentally investigated by fabricating well-defined silicon micropillar arrays using standard contact photolithography and deep reactive ion etching. A thin film resistive heater and thermal sensors were integrated on the back side of the test sample using e-beam evaporation and acetone lift-off. The experiments were carried out in a controlled environmental chamber maintained at the water saturation pressure of ≈3.5 kPa and ≈25 °C. We demonstrated significantly higher heat dissipation capability in excess of 100 W/cm2. These preliminary results suggest the potential of thin-film evaporation from microstructured surfaces for advanced thermal management applications.
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Chuang, Pierce I.-Jen, Christos Vezyrtzis, Divya Pathak, Richard Rizzolo, Tobias Webel, Thomas Strach, Otto Torreiter, et al. "26.2 Power supply noise in a 22nm z13™ microprocessor." In 2017 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2017. http://dx.doi.org/10.1109/isscc.2017.7870449.

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Stanford. "Microprocessor voltage regulators and power supply trends and device requirements." In IC's. IEEE, 2004. http://dx.doi.org/10.1109/wct.2004.239748.

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Reid, Michael, and Bernie Cook. "The Application of Smart, Connected Power Plant Assets for Enhanced Condition Monitoring and Improving Equipment Reliability." In ASME 2016 Power Conference collocated with the ASME 2016 10th International Conference on Energy Sustainability and the ASME 2016 14th International Conference on Fuel Cell Science, Engineering and Technology. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/power2016-59189.

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The U.S. electric utility industry continues to undergo dramatic change due to a number of key trends and also prolonged uncertainty. These trends include: • Increasing environmental regulations uncertainty • Natural gas supply uncertainty and price • Economic / decoupling of electricity demand growth from GDP • Aging coal and nuclear generation fleet / coal retirements • Aging workforce • Increasing distributed energy resources • Increasing customer expectations The transformation ultimately demands significant increases in power plant generation operating capabilities (e.g. flexibility, operating envelop, ramp rates, turn-down etc.) and higher levels of equipment reliability, while reducing O&M and capital budgets. Achieving higher levels of equipment reliability and flexibility, with such tightening budget and resource constraints, requires a very disciplined approach to maintenance and an optimized mix of the following maintenance practices: • Reactive (run-to-failure) • Preventive (time-based) • Predictive (condition-based) • Proactive (combination of 1, 2 and 3 + root cause failure analysis) Many U.S. electric utilities with fossil generation have adopted and implemented elements of an equipment reliability process consistent with Institute of Nuclear Power Operations (INPO) AP-913. The Electric Power Research Institute has created a guideline modeled from the learnings of AP-913, that consists of six key sub-processes [1]: 1. Scoping and identification of critical components (identifying system and component criticality) 2. Continuing equipment reliability improvement (establishing and continuously improving system and component maintenance bases) 3. Preventive Maintenance (PM) implementation (implementing the PM program effectively) 4. Performance monitoring (monitoring system and component performance) 5. Corrective action 6. Life cycle management (long-term asset management) A significant proportion of Duke Energy’s coal fleet is of an age where individual components have reached their design intent end-of-life thereby creating an increased need for performance monitoring. Until recent times this was largely performed by maintenance technicians with handheld devices. This approach does not allow regular data collection for trending and optimization of maintenance practices across the fleet. Significant and recent advances in sensor technology, microprocessors, data acquisition, data storage, communication technology, and software have enabled the transformation of critical power plant assets such as steam turbines, combustion turbines, generators, transformers, and large balance-of-plant equipment into smart, connected power plant assets. These enhanced assets, in conjunction with visualization software, provide a comprehensive conditioning monitoring solution that continuously acquires sensory data and performs real time analysis to provide information and insight. This advanced condition monitoring capability has been successfully applied to obtain earlier detection of equipment issues and failures and is key to improving overall equipment reliability. This paper describes an approach by Duke Energy to create and apply smart, connected power plant assets to greatly enhance its fossil generation continuous condition monitoring capabilities. It will discuss the value that is currently being realized and also look at future possibilities to apply big data and analytics to enhance information, insight, and actionable intelligence.
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Sarangi, Ananda, and Greg Taylor. "The Impact of Leakage to the Power Supply Impedance of a Microprocessor." In 2006 IEEE Workship on Signal Propagation on Interconnects. IEEE, 2006. http://dx.doi.org/10.1109/spi.2006.289184.

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Kim, Hyun Sung, and D. M. H. Walker. "Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits." In Seventh International Workshop on Microprocessor Test and Verification (MTV'06). IEEE, 2006. http://dx.doi.org/10.1109/mtv.2006.20.

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Cho, Kyu Min, Won Seok Oh, Kyung Sang Yoo, Chigak In, and Jaeeul Yeon. "A microprocessor based single stage power supply using fly-back converter for LED lightings." In 2011 International Conference on Applied Superconductivity and Electromagnetic Devices (ASEMD). IEEE, 2011. http://dx.doi.org/10.1109/asemd.2011.6145074.

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