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Dissertations / Theses on the topic 'Microprocessors'
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1
Taylor, Michael Bedford 1975. "Tiled microprocessors." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/38924.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 251-258).
Current-day microprocessors have reached the point of diminishing returns due to inherent scalability limitations. This thesis examines the tiled microprocessor, a class of microprocessor which is physically scalable but inherits many of the desirable properties of conventional microprocessors. Tiled microprocessors are composed of an array of replicated tiles connected by a special class of network, the Scalar Operand Network (SON), which is optimized for low-latency, low-occupancy communication between remote ALUs on different tiles. Tiled microprocessors can be constructed to scale to 100's or 1000's of functional units. This thesis identifies seven key criteria for achieving physical scalability in tiled microprocessors. It employs an archetypal tiled microprocessor to examine the challenges in achieving these criteria and to explore the properties of Scalar Operand Networks. The thesis develops the field of SONs in three major ways: it introduces the 5-tuple performance metric, it describes a complete, high-frequency <0,0,1,2,0> SON implementation, and it proposes a taxonomy, called AsTrO, for categorizing them.
(cont.) To develop these ideas, the thesis details the design, implementation and analysis of a tiled microprocessor prototype, the Raw Microprocessor, which was implemented at MIT in 180 nm technology. Overall, compared to Raw, recent commercial processors with half the transistors required 30x as many lines of code, occupied 100x as many designers, contained 50x as many pre-tapeout bugs, and resulted in 33x as many post-tapeout bugs. At the same time, the Raw microprocessor proves to be more versatile in exploiting ILP, stream, and server-farm workloads with modest to large amounts of parallelism.
by Michael Bedford Taylor.
Ph.D.
2
Siers, Scott. "Design and implementation of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1993. http://hdl.handle.net/1850/11562.
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Hadi, Muntasir J. "Design of a real-time multi-channel microprocessor based data acquisition and control system." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182787292.
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Sheth, Khushbooben Agrawal Vishwani D. "A hardware-software processor architecture using pipeline stalls for leakage power management." Auburn, Ala, 2009. http://hdl.handle.net/10415/1590.
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Mivehchi, M. H. "Microprocessors applications to telecommunications." Thesis, Bucks New University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375601.
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Fournier, Jacques Jean-Alain Michael. "Vector microprocessors for cryptography." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.613318.
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Дядечко, Алла Миколаївна, Алла Николаевна Дядечко, Alla Mykolaivna Diadechko, and D. Mulin. "The history of microprocessors." Thesis, Вид-во СумДУ, 2009. http://essuir.sumdu.edu.ua/handle/123456789/16862.
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Johnson, Kevin. "Design and implementation of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1994. http://hdl.handle.net/1850/11171.
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Pobbathi, Venkatesh Paneesh Kumar. "Randomization Based Verification for Microprocessors." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177438.
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Verification of microprocessors is a vital phase in their development. It takes majority of time and cost in the microprocessor development. Verification can be split into two; coverage and check. In coverage we try to find out if all desired conditions are executed. Where as in check, we try to find out if the behaviour of the DUT is as expected. In this thesis we concentrate more on coverage. The test bench should be able to cover all the cases, hence methodologies have to be used which will not only reduce the total time of the project but also get maximum coverage to increase the bug detection chances. Random simulation helps to quickly attain corner cases that would not have been found by the traditional directed testing. In this thesis functional verification for the microprocessor M6802 was implemented. Few verification approaches were implemented to find out their feasibility. It was found out that random generation had many advantages over directed testing but both the approaches failed to attain good coverage in reasonable time. To overcome this other implementations were explored such as coverage driven and machine learning. Machine learning showed significant improvement over the other methods for coverage on the filp side it required a lot of setup time. It was found out that the combination of these approaches have to be used to reduce the setup time and get maximum coverage. The method to be selected depends on the complexity of the processor and the functional coverpoint.
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Balfour, J. "Source level debugging for microprocessors." Thesis, Lancaster University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379582.
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Fox, A. C. J. "Algebraic models for advanced microprocessors." Thesis, Swansea University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.637000.
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In this thesis, algebraic methods are used to model advanced microprocessor organisations. Correctness is defined by modelling computer systems at two levels of abstraction: the abstract circuit level, and the programmer's model level. The abstract circuit corresponds with a microprocessor organisation, or micro-architecture; and the programmer's model corresponds with a computer architecture. Computer architectures provide stability at the interface between software and hardware; this is achieved by establishing a (relatively) constant target for program compilation, and for future processor development. For commercial viability most new processors must correctly implement an established architecture; in this way the processor guarantees the seamless support of an existing software base. This thesis formally defines the correctness of processors, including those of superscalar design. With the ever increasing need for computing power, superscalar designs are used in many personal computers, and even in embedded applications. Super-scalar designs use long instruction pipelines and multiple functional units to achieve high degrees of instruction-level parallelism; they can execute instructions simultaneously, or in some cases out-of-order. This thesis explores the nature of temporal abstraction for pipelined and super-scalar computer organisations. A superscalar case study is presented; this design provides for out-of-order instruction issue, and uses Thornton's algorithm. This thesis also provides a structured framework for processor verification. With the suitable use of initialisation functions, and temporal abstractions, it is shown that correctness can be verified without the explicit use of temporal induction. In addition to studying the control (temporal) aspects of processors, this thesis also addresses data issues and presents an (abbreviated) algebraic specification of the IEEE-754 floating-point standard.
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Bhagwati, Vishal Lalit. "Automatic verification of pipelined microprocessors." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34045.
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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 71-72).
by Vishal Lalit Bhagwati.
M.S.
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Chauhan, Anjali. "Hot spot mitigation in microprocessors by application of single phase microchannel heat sink and microprocessor floor planning." Diss., Online access via UMI:, 2009.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineeering, 2009.Includes bibliographical references.
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Ergin, Oǧuz. "Register file optimizations for superscalar microprocessors." Diss., Online access via UMI:, 2005.
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Jaskot, Roger Dean, and Harold W. Henry. "MICROLAN file transfer program for microprocessors." Thesis, Monterey, California. Naval Postgraduate School, 1985. http://hdl.handle.net/10945/23451.
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Koltes, Andreas. "Reconfigurable memory systems for embedded microprocessors." Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.709244.
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Olson, Joseph Augustine 1959. "Expandable multiprocessor using low cost microprocessors." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277133.
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This paper presents an expandable multiprocessor system design based on: (a) an INTEL 80188 based microcomputer as the basic processing element; (b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel. The basic system design consists of two IBM PC expansion cards--a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Each processor has access to two separate interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using a token bus data link control. IP communications is either direct or routed via intervening processors to support an unlimited number of processors in a given system.
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Furman, Samuel Lewis. "iLORE: Discovering a Lineage of Microprocessors." Thesis, Virginia Tech, 2021. http://hdl.handle.net/10919/104071.
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Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org.Master of Science
Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org.
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Yoo, Joonhyuk. "Harnessing checker hierarchy for reliable microprocessors." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7688.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Brown, Allen David Evans. "Parametric spectral analysis using digital signal microprocessors." Thesis, University of Hertfordshire, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387144.
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Osqui, Mitra M. 1980. "Evaluation of software energy consumption on microprocessors." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8344.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2002.Includes bibliographical references (leaves 72-75).
In the area of wireless communications, energy consumption is the key design consideration. Significant effort has been placed in optimizing hardware for energy efficiency, while relatively less emphasis has been placed on software energy reduction. For overall energy efficiency reduction of system energy consumption in both hardware and software must be addressed. One goal of this research is to evaluate the factors that affect software energy efficiency and identify techniques that can be employed to produce energy optimal software. In order to present a strong argument, two state-of-the-art low power processors were used for evaluation: the Intel StrongARM SA-1100 and the next generation Intel Xscale processor. A key step in analyzing the performance of software is to perform a comprehensive tabulation of the energy consumption per instruction, while taking into account the different modes of operation. This leads into a comprehensive energy profiling for the instruction set of the processors of interest. With information on the energy consumption per instruction, we can evaluate the feasibility of energy efficient programming and use the results to gain greater insight into the power consumption of the two processors under consideration. Benchmark programs will be tested on both processors to illustrate the effectiveness of the energy profiling results. The next goal is to look at the leakage current and current consumed during idle modes of the processors and how that impacts the overall picture of energy consumption. Thus energy consumption will be explored for the two processors from both a dynamic and static energy consumption perspective.
by Mitra M. Osqui.
S.M.
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Poyneer, Lisa A. (Lisa Ann) 1975. "Term rewriting system models of modern microprocessors." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80566.
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Tseng, Jessica Hui-Chun 1977. "Banked microarchitectures for complexity-effective superscalar microprocessors." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37901.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 95-99).
High performance superscalar microarchitectures exploit instruction-level parallelism (ILP) to improve processor performance by executing instructions out of program order and by speculating on branch instructions. Monolithic centralized structures with global communications, including issue windows and register files, are used to buffer in-flight instructions and to maintain machine state. These structures scale poorly to greater issue widths and deeper pipelines, as they must support simultaneous global accesses from all active instructions. The lack of scalability is exacerbated in future technologies, which have increasing global interconnect delay and a much greater emphasis on reducing both switching and leakage power. However, these fully orthogonal structures are over-engineered for typical use. Banked microarchitectures that consist of multiple interleaved banks of fewer ported cells can significantly reduce power, area, and latency of these structures.
(cont.) Although banked structures exhibit a minor performance penalty, significant reductions in delay and power can potentially be used to increase clock rate and lead to more complexity-effective designs. There are two main contributions in this thesis. First, a speculative control scheme is proposed to simplify the complicated control logic that is involved in managing a less-ported banked register file for high-frequency superscalar processors. Second, the RingScalar architecture, a complexity-effective out-of-order superscalar microarchitecture, based on a ring topology of banked structures, is introduced and evaluated.
by Jessica Hui-Chun Tseng.
Ph.D.
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Khan, Mohammad Ziaullah. "Concurrent detection of transient faults in microprocessors." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54212.
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A large number of errors in digital systems are due to the presence of transient faults. This is especially true of microprocessor-based systems working in a radiation environment that experience transient faults due to single event upsets. These upsets cause a temporary change in the state of the system without any permanent damage. Because of their random and non-recurring nature, transient faults are difficult to detect and isolate, hence they become a source of major concern, especially in critical real-time application areas. Concurrent detection of these errors is necessary for real-time operation.
Most existing fault tolerance schemes either use redundancy to mask effects of transient faults or monitor the system for abnormal operations and then perform recovery operation. Although very effective, redundancy schemes incur substantial overhead that makes them unsuitable for small systems. Most monitoring schemes, on the other hand, only detect control flow errors.
A new approach called Concurrent Processor Monitoring for on-line detection of transient faults is proposed that attempts to achieve high error coverage with small error detection latency. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is designed for monitoring operation of the main processor. The effectiveness of this technique is demonstrated through computer simulations.Ph. D.
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Van, Buren Brian G. "Graphical microcode simulator with a reconfigurable datapath /." Online version of thesis, 2006. https://ritdml.rit.edu/dspace/handle/1850/2892.
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Eble, John C. III. "A generic system simulator with novel on-chip cache and throughput models for gigascale integration." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15655.
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Narasimha, Swamy Bharath. "Exploiting heterogeneous many cores on sequential code." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S006/document.
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Les architectures ''Heterogeneous Many Cores'' (HMC) qui mélangent beaucoup de petits/simples cœurs avec quelques cœurs larges/complexes, fournissent de bonnes performances pour des applications séquentielles et permettent une économie d'énergie pour les applications parallèles. Les petits cœurs des HMC peuvent être utilisés comme des cœurs auxiliaires pour accélérer les applications séquentielles gourmandes en mémoire qui s'exécutent sur le cœur principal. Cependant, le surcoût pour accéder aux petits cœurs limite leur utilisation comme cœurs auxiliaires. En raison de la disparité de performance entre le cœur principal et les petits cœurs, on ne sait pas encore si les petits cœurs sont adaptés pour exécuter des threads auxiliaires pour faire du prefetching pour un cœur plus puissant. Dans cette thèse, nous présentons une architecture hardware/software appelée « core-tethering », pour supporter efficacement l'exécution de threads auxiliaires sur les systèmes HMC. Cette architecture permet au cœur principal de pouvoir lancer et contrôler directement l'exécution des threads auxiliaires, et de transférer efficacement le contexte des applications nécessaire à l'exécution des threads auxiliaires. Sur un ensemble de programmes ayant une utilisation intensive de la mémoire, les threads auxiliaires s'exécutant sur des cœurs relativement petits, peuvent apporter une accélération significative par rapport à du prefetching matériel seul. Et les petits cœurs fournissent un bon compromis par rapport à l'utilisation d'un seul cœur puissant pour exécuter les threads auxiliaires. En résumé, malgré le surcoût lié à la latence d'accès aux lignes de cache chargées par le prefetching depuis le cache L3 partagé, le prefetching par les threads auxiliaires sur les petits cœurs semble être une manière prometteuse d'améliorer la performance des codes séquentiels pour des applications ayant une utilisation intensive de la mémoire sur les systèmes HMCHeterogeneous Many Cores (HMC) architectures that mix many simple/small cores with a few complex/large cores are emerging as a design alternative that can provide both fast sequential performance for single threaded workloads and power-efficient execution for through-put oriented parallel workloads. The availability of many small cores in a HMC presents an opportunity to utilize them as low-power helper cores to accelerate memory-intensive sequential programs mapped to a large core. However, the latency overhead of accessing small cores in a loosely coupled system limits their utility as helper cores. Also, it is not clear if small cores can execute helper threads sufficiently in advance to benefit applications running on a larger, much powerful, core. In this thesis, we present a hardware/software framework called core-tethering to support efficient helper threading on heterogeneous many-cores. Core-tethering provides a co-processor like interface to the small cores that (a) enables a large core to directly initiate and control helper execution on the helper core and (b) allows efficient transfer of execution context between the cores, thereby reducing the performance overhead of accessing small cores for helper execution. Our evaluation on a set of memory intensive programs chosen from the standard benchmark suites show that, helper threads using moderately sized small cores can significantly accelerate a larger core compared to using a hardware prefetcher alone. We also find that a small core provides a good trade-off against using an equivalent large core to run helper threads in a HMC. In summary, despite the latency overheads of accessing prefetched cache lines from the shared L3 cache, helper thread based prefetching on small cores looks as a promising way to improve single thread performance on memory intensive workloads in HMC architectures
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Erazo, Jorge G. "An emulator system for the MC146805F2/G2 microprocessors." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1184001657.
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Eken, Huseyin Baha. "Feasibility analysis and design of a fault tolerant computing system : a TMR microprocessor system design of 64-Bit COTS microprocessors." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2001. http://handle.dtic.mil/100.2/ADA390948.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 2001.Thesis advisors, Alan A. Ross, Herschel H. Loomis. Includes bibliographical references (p. 101-102). Also Available online.
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Farkas, Keith I. "Memory-system design considerations for dynamically-scheduled microprocessors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ27922.pdf.
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Kim, Byung Moo. "Compilation techniques for multiprocessors based on DSP microprocessors." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/13728.
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Robinson, Andrew J. "Improving instruction encoding efficiency in low power microprocessors." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500489.
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Deka, Rabin. "Formulae and multiprocessor algorithms for digital signal microprocessors." Thesis, University of Bradford, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.304030.
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Boettcher, Matthias. "Memory and functional unit design for vector microprocessors." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/365071/.
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Modern mobile devices employ SIMD datapaths to exploit small scale data-level parallelism to achieve the performance required to process a continuously growing number of computation intensive applications within a severely energy constrained environment. The introduction of advanced SIMD features expands the applicability of vector ISA extensions from media and signal processing algorithms to general purpose code. Considering the high memory bandwidth demands and the complexity of execution units associated with those features, this dissertation focuses on two main areas of investigation, the efficient handling of parallel memory accesses and the optimization of vector functional units. A key observation, obtained from simulation based analysis on the type and frequency of memory access patterns exhibited by general purpose workloads, is the tendency of consecutive memory references to access the same page. Exploiting this and further observations, Page-Based Memory Access Grouping enables a level one data cache interface to utilize single-ported TLBs and cache banks to achieve performance similar to multi-ported components, while consuming significantly less energy. Page-Based Way Determination extends the proposed scheme with TLB-coupled structures holding way information on recently accessed lines. These structures improve the energy efficiency of the vast majority of memory references by enabling them to bypass tag-arrays and directly target individual cache ways. A vector benchmarking environment - comprised of a flexible ISA extension, a parameterizable simulation framework and a corresponding benchmark suite - is developed and utilized in the second part of this thesis to facilitate investigations into the design aspects and potential performance benefits of advanced SIMD features. Based on it, a set of microarchitecture optimizations is introduced, including techniques to compute hardware interpretable masks for segmented operations, partition scans to allow specific energy - performance trade-offs, re-use existing multiplexers to process predicated and segmented vectors, accelerate scans on incomplete vectors, efficiently handle micro-ops fully comprised of predicated elements, and reference multiple physical registers within individual operands to improve the utilization of the vector register file.
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Ahmed, Mohamed Hassan Abouelella. "Power Architectures and Design for Next Generation Microprocessors." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/103175.
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With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU.
Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions.
Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms.
The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations.
The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM.
Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application.
The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density.
This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control.Doctor of Philosophy
With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.
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Buehler, Christopher James 1974. "An instruction scheduling algorithm for communication-constrained microprocessors." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46254.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 130-132).
This thesis describes a new randomized instruction scheduling algorithm designed for communication-constrained VLIW-style machines. The algorithm was implemented in a retargetable compiler system for testing on a variety a different machine configurations. The algorithm performed acceptably well for machines with full communication, but did not perform up to expectations in the communication-constrained case. Parameter studies were conducted to ascertain the reason for inconsistent results.
by Christopher James Buehler.
S.M.
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Sung, Hyojin. "A portable MATLAB front-end for tiled microprocessors." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1461998.
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Thesis (M.S.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed March 3, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 56-58).
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Wadell, Robert Paul. "Experimental Investigation of Compact Evaporators for Ultra Low Temperature Refrigeration of Microprocessors." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7198.
Full textAbstract:
It is well known that microprocessor performance can be improved by lowering the junction temperature. Two stage cascaded vapor compression refrigeration (VCR) is a mature, inexpensive, and reliable cooling technology that can offer chip temperatures down to ?? C. Recent studies have shown that for a power limited computer chip, there is a non-linear scaling effect that offers a 4.3X performance enhancement at ?? C. The heat transfer performance of a compact evaporator is often the bottleneck in sub-ambient heat removal. For this reason, the design of a deep sub-ambient compact evaporator is critical to the cooling system performance and has not been addressed in the literature.
Four compact evaporator designs were investigated as feasible designs - a baseline case with no enhancement structures, micro channels, inline pin fin arrays, and alternating pin fin arrays. A parametric experimental investigation of four compact evaporator designs has been performed aiming at enhancing heat transfer. Each evaporator consists of oxygen free copper and has a footprint of 20 mm x 36 mm, with a total thickness of 3.1 mm. The micro channel evaporator contains 13 channels that are 400 um wide by 1.2 mm deep, and the pin fin evaporators contain approximately 80 pin fins that are 400 um wide by 1.2 mm tall with a pitch of 800 um. Two phase convective boiling of R508b refrigerant was investigated in each evaporator at flow rates of 50 - 70 g/min and saturation temperatures of ??to ??C. Pressure drop and local heat transfer measurements are reported and used to explain the performance of the various evaporator geometries. The results are compared to predictions from popular macro- and micro-channel heat transfer and pressure drop correlations. The challenges of implementing a two stage cascade VCR systems for microprocessor refrigeration are also discussed.
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Crummey, Thomas Paul. "A hardware scheduler for parallel processing in control." Thesis, Bangor University, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.265508.
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Singh, Aditya Kumar. "Design and development of fuzzy expert system for handy board." Morgantown, W. Va. : [West Virginia University Libraries], 1999. http://etd.wvu.edu/templates/showETD.cfm?recnum=1177.
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Thesis (M.S.)--West Virginia University, 1999.Title from document title page. Document formatted into pages; contains v, 134 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 66-69).
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Jiménez, Daniel Angel. "Delay-sensitive branch predictors for future technologies." Full text (PDF) from UMI/Dissertation Abstracts International, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3081043.
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López, Julià Toni. "Prospects of voltage regulators for next generation computer microprocessors." Doctoral thesis, Universitat Politècnica de Catalunya, 2010. http://hdl.handle.net/10803/77908.
Full textAbstract:
Synchronous buck converter based multiphase architectures are evaluated to
determine whether or not the most widespread voltage regulator topology can
meet the power delivery requirements of next generation computer
microprocessors. According to the prognostications, the load current will rise to
200A along with the decrease of the supply voltage to 0.5V and staggering tight
dynamic and static load line tolerances. In view of these demands, researchers face
serious challenges to bring forth compliant solutions that can further offer
acceptable conversion efficiencies and minimum mainboard area occupancy.
Among the most prominent investigation fronts are those surveying
fundamental technology improvements aiming at making power semiconductor
devices more effective at high switching frequency. The latter is of critical
importance as the increase of the switching frequency is fundamentally recognized
as the way forward to enhance power density conversion. Provided that switching
losses must be kept low to enable the miniaturization of the filter components, one
primary goal is to cope with semiconductor and system integration technologies
enabling fast dynamic operation of ultra-low ON resistance power switches.
This justifies the main focus of this thesis work, centered around a
comprehensive analysis of the MOSFET switching behavior in the synchronous
buck converter.
The MOSFETs dynamic operation, far from being well describable with the
traditional clamped inductive hard-switching mode, is strongly influenced by a
number of frequently ignored linear and nonlinear parasitic elements that must be
taken into account in order to fully predict real switching waveforms, understand
their dynamics, and most importantly, identify and quantify the related
mechanisms leading to heat generation. This will be revealed from in-depth
investigations of the switched converter under fast switching speeds and heavy
load.
Recognizing the key relevance of appropriate modeling tools that support this
task, the second focal point of the thesis aims at developing a number of suitable
models for the switching analysis of power MOSFETs.
Combined with a series of design guidelines and optimization procedures, these
models form the basis of a proposed methodological approach, where numerical
computations replace the usually enormous experimental effort to elucidate the
most effective pathways towards reducing power losses. This gives rise to the
concept referred to as virtual design loop, which is successfully applied to the
development of a new power MOSFET technology offering outstanding dynamic
and static performance characteristics. From a system perspective, the limits of the
power density conversion will be explored for this and other emerging
technologies that promise to open up a new paradigm in power integration
capabilities.
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Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.
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Puttaswamy, Kiran. "Designing high-performance microprocessors in 3-dimensional integration technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19759.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Loh, Gabriel H.; Committee Co-Chair: Lee, Hsien-Hsin S.; Committee Member: Lim, Sung Kyu; Committee Member: Prvulovic, Milos; Committee Member: Yalamanchili, Sudhakar; Committee Member: Yoder, Douglas.
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Chamdani, Joseph Irawan. "Microarchitecture techniques to improve the design of superscalar microprocessors." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15509.
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Chiou, Derek. "Extending the reach of microprocessors : column and curious caching." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80200.
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Ham, Christopher V. "UTILIZING OFF-THE-SHELF MICROPROCESSORS FOR COMPLEX TELEMETRY PREPROCESSING." International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615416.
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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, NevadaThis paper describes a system utilizing off-the-shelf microprocessor hardware to perform complex high-speed telemetry data preprocessing. The microprocessor equipment involves the latest in the Motorola computer series, namely the 68020 line. The author develops the specifications leading to the need of this type of preprocessor which is currently being developed under a contract to the McDonnell Douglas Helicopter Company. The paper fully describes the configuration of the hardware as well as the software available on the system. Detailed benchmarks of complex algorithms and other data manipulations are described. Test results relating parameter capacity and throughput are addressed. System architecture is described with the various trade-off analyses well defined. This system advances the art of preprocessing telemetry parameters requiring such functions as wild pointing, phase alignment concatenation, and derivations, all at rates in the megaword input.
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Wei, Jia. "High Frequency High-Efficiency Voltage Regulators for Future Microprocessors." Diss., Virginia Tech, 2004. http://hdl.handle.net/10919/11254.
Full textAbstract:
Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us.
The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency.
The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed.
The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics.
Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs.
The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities.Ph. D.
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Renaghan, Liam Eamon. "On-Chip Isotropic Microchannels for Cooling Three Dimensional Microprocessors." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/36404.
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This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C.
To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer.Master of Science
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Krishnamurthy, Sivasubramaniam T. "STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.
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