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Dissertations / Theses on the topic 'Microprocessors'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Taylor, Michael Bedford 1975. "Tiled microprocessors." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/38924.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>Includes bibliographical references (p. 251-258).<br>Current-day microprocessors have reached the point of diminishing returns due to inherent scalability limitations. This thesis examines the tiled microprocessor, a class of microprocessor which is physically scalable but inherits many of the desirable properties of conventional microprocessors. Tiled microprocessors are composed of an array of replicated tiles connected by a special class of network, the Scalar Operand Netwo

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2

Siers, Scott. "Design and implementation of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1993. http://hdl.handle.net/1850/11562.

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3

Hadi, Muntasir J. "Design of a real-time multi-channel microprocessor based data acquisition and control system." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182787292.

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4

Sheth, Khushbooben Agrawal Vishwani D. "A hardware-software processor architecture using pipeline stalls for leakage power management." Auburn, Ala, 2009. http://hdl.handle.net/10415/1590.

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5

Mivehchi, M. H. "Microprocessors applications to telecommunications." Thesis, Bucks New University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375601.

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6

Fournier, Jacques Jean-Alain Michael. "Vector microprocessors for cryptography." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.613318.

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7

Дядечко, Алла Миколаївна, Алла Николаевна Дядечко, Alla Mykolaivna Diadechko, and D. Mulin. "The history of microprocessors." Thesis, Вид-во СумДУ, 2009. http://essuir.sumdu.edu.ua/handle/123456789/16862.

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8

Johnson, Kevin. "Design and implementation of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1994. http://hdl.handle.net/1850/11171.

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9

Pobbathi, Venkatesh Paneesh Kumar. "Randomization Based Verification for Microprocessors." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177438.

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Verification of microprocessors is a vital phase in their development. It takes majority of time and cost in the microprocessor development. Verification can be split into two; coverage and check. In coverage we try to find out if all desired conditions are executed. Where as in check, we try to find out if the behaviour of the DUT is as expected. In this thesis we concentrate more on coverage. The test bench should be able to cover all the cases, hence methodologies have to be used which will not only reduce the total time of the project but also get maximum coverage to increase the bug detec

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10

Balfour, J. "Source level debugging for microprocessors." Thesis, Lancaster University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379582.

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11

Fox, A. C. J. "Algebraic models for advanced microprocessors." Thesis, Swansea University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.637000.

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In this thesis, algebraic methods are used to model advanced microprocessor organisations. Correctness is defined by modelling computer systems at two levels of abstraction: the abstract circuit level, and the programmer's model level. The abstract circuit corresponds with a microprocessor organisation, or micro-architecture; and the programmer's model corresponds with a computer architecture. Computer architectures provide stability at the interface between software and hardware; this is achieved by establishing a (relatively) constant target for program compilation, and for future processor

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12

Bhagwati, Vishal Lalit. "Automatic verification of pipelined microprocessors." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34045.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (p. 71-72).<br>by Vishal Lalit Bhagwati.<br>M.S.

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13

Chauhan, Anjali. "Hot spot mitigation in microprocessors by application of single phase microchannel heat sink and microprocessor floor planning." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineeering, 2009.<br>Includes bibliographical references.

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14

Ergin, Oǧuz. "Register file optimizations for superscalar microprocessors." Diss., Online access via UMI:, 2005.

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15

Jaskot, Roger Dean, and Harold W. Henry. "MICROLAN file transfer program for microprocessors." Thesis, Monterey, California. Naval Postgraduate School, 1985. http://hdl.handle.net/10945/23451.

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16

Koltes, Andreas. "Reconfigurable memory systems for embedded microprocessors." Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.709244.

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17

Olson, Joseph Augustine 1959. "Expandable multiprocessor using low cost microprocessors." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277133.

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This paper presents an expandable multiprocessor system design based on: (a) an INTEL 80188 based microcomputer as the basic processing element; (b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel. The basic system design consists of two IBM PC expansion cards--a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Each processor has access to two separate interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using

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18

Furman, Samuel Lewis. "iLORE: Discovering a Lineage of Microprocessors." Thesis, Virginia Tech, 2021. http://hdl.handle.net/10919/104071.

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Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement a

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19

Yoo, Joonhyuk. "Harnessing checker hierarchy for reliable microprocessors." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7688.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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20

Brown, Allen David Evans. "Parametric spectral analysis using digital signal microprocessors." Thesis, University of Hertfordshire, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387144.

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21

Osqui, Mitra M. 1980. "Evaluation of software energy consumption on microprocessors." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8344.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2002.<br>Includes bibliographical references (leaves 72-75).<br>In the area of wireless communications, energy consumption is the key design consideration. Significant effort has been placed in optimizing hardware for energy efficiency, while relatively less emphasis has been placed on software energy reduction. For overall energy efficiency reduction of system energy consumption in both hardware and software must be addressed. One goal of this research is to evaluate the factor

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22

Poyneer, Lisa A. (Lisa Ann) 1975. "Term rewriting system models of modern microprocessors." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80566.

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23

Tseng, Jessica Hui-Chun 1977. "Banked microarchitectures for complexity-effective superscalar microprocessors." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37901.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 95-99).<br>High performance superscalar microarchitectures exploit instruction-level parallelism (ILP) to improve processor performance by executing instructions out of program order and by speculating on branch instructions. Monolithic centralized structures with global communications, including issue windows and register files, are used to buffer in-flight instructions and to maintain machine state. These structures scale poorly to gre

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24

Khan, Mohammad Ziaullah. "Concurrent detection of transient faults in microprocessors." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54212.

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A large number of errors in digital systems are due to the presence of transient faults. This is especially true of microprocessor-based systems working in a radiation environment that experience transient faults due to single event upsets. These upsets cause a temporary change in the state of the system without any permanent damage. Because of their random and non-recurring nature, transient faults are difficult to detect and isolate, hence they become a source of major concern, especially in critical real-time application areas. Concurrent detection of these errors is necessary for real-time

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25

Narasimha, Swamy Bharath. "Exploiting heterogeneous many cores on sequential code." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S006/document.

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Les architectures ''Heterogeneous Many Cores'' (HMC) qui mélangent beaucoup de petits/simples cœurs avec quelques cœurs larges/complexes, fournissent de bonnes performances pour des applications séquentielles et permettent une économie d'énergie pour les applications parallèles. Les petits cœurs des HMC peuvent être utilisés comme des cœurs auxiliaires pour accélérer les applications séquentielles gourmandes en mémoire qui s'exécutent sur le cœur principal. Cependant, le surcoût pour accéder aux petits cœurs limite leur utilisation comme cœurs auxiliaires. En raison de la disparité de performa

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26

Van, Buren Brian G. "Graphical microcode simulator with a reconfigurable datapath /." Online version of thesis, 2006. https://ritdml.rit.edu/dspace/handle/1850/2892.

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27

Eble, John C. III. "A generic system simulator with novel on-chip cache and throughput models for gigascale integration." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15655.

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28

Erazo, Jorge G. "An emulator system for the MC146805F2/G2 microprocessors." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1184001657.

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29

Eken, Huseyin Baha. "Feasibility analysis and design of a fault tolerant computing system : a TMR microprocessor system design of 64-Bit COTS microprocessors." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2001. http://handle.dtic.mil/100.2/ADA390948.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 2001.<br>Thesis advisors, Alan A. Ross, Herschel H. Loomis. Includes bibliographical references (p. 101-102). Also Available online.

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30

Farkas, Keith I. "Memory-system design considerations for dynamically-scheduled microprocessors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ27922.pdf.

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31

Kim, Byung Moo. "Compilation techniques for multiprocessors based on DSP microprocessors." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/13728.

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32

Robinson, Andrew J. "Improving instruction encoding efficiency in low power microprocessors." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500489.

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33

Deka, Rabin. "Formulae and multiprocessor algorithms for digital signal microprocessors." Thesis, University of Bradford, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.304030.

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34

Boettcher, Matthias. "Memory and functional unit design for vector microprocessors." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/365071/.

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Modern mobile devices employ SIMD datapaths to exploit small scale data-level parallelism to achieve the performance required to process a continuously growing number of computation intensive applications within a severely energy constrained environment. The introduction of advanced SIMD features expands the applicability of vector ISA extensions from media and signal processing algorithms to general purpose code. Considering the high memory bandwidth demands and the complexity of execution units associated with those features, this dissertation focuses on two main areas of investigation, the

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35

Ahmed, Mohamed Hassan Abouelella. "Power Architectures and Design for Next Generation Microprocessors." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/103175.

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With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data c

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36

Buehler, Christopher James 1974. "An instruction scheduling algorithm for communication-constrained microprocessors." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46254.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 130-132).<br>This thesis describes a new randomized instruction scheduling algorithm designed for communication-constrained VLIW-style machines. The algorithm was implemented in a retargetable compiler system for testing on a variety a different machine configurations. The algorithm performed acceptably well for machines with full communication, but did not perform up to expectations in the communication-constrained case. Parameter studies

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37

Sung, Hyojin. "A portable MATLAB front-end for tiled microprocessors." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1461998.

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Thesis (M.S.)--University of California, San Diego, 2009.<br>Title from first page of PDF file (viewed March 3, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 56-58).

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38

Wadell, Robert Paul. "Experimental Investigation of Compact Evaporators for Ultra Low Temperature Refrigeration of Microprocessors." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7198.

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It is well known that microprocessor performance can be improved by lowering the junction temperature. Two stage cascaded vapor compression refrigeration (VCR) is a mature, inexpensive, and reliable cooling technology that can offer chip temperatures down to ?? C. Recent studies have shown that for a power limited computer chip, there is a non-linear scaling effect that offers a 4.3X performance enhancement at ?? C. The heat transfer performance of a compact evaporator is often the bottleneck in sub-ambient heat removal. For this reason, the design of a deep sub-ambient compact evaporator is c

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39

Crummey, Thomas Paul. "A hardware scheduler for parallel processing in control." Thesis, Bangor University, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.265508.

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40

Singh, Aditya Kumar. "Design and development of fuzzy expert system for handy board." Morgantown, W. Va. : [West Virginia University Libraries], 1999. http://etd.wvu.edu/templates/showETD.cfm?recnum=1177.

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Thesis (M.S.)--West Virginia University, 1999.<br>Title from document title page. Document formatted into pages; contains v, 134 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 66-69).

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41

Jiménez, Daniel Angel. "Delay-sensitive branch predictors for future technologies." Full text (PDF) from UMI/Dissertation Abstracts International, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3081043.

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42

López, Julià Toni. "Prospects of voltage regulators for next generation computer microprocessors." Doctoral thesis, Universitat Politècnica de Catalunya, 2010. http://hdl.handle.net/10803/77908.

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Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboa

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43

Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.

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44

Puttaswamy, Kiran. "Designing high-performance microprocessors in 3-dimensional integration technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19759.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Loh, Gabriel H.; Committee Co-Chair: Lee, Hsien-Hsin S.; Committee Member: Lim, Sung Kyu; Committee Member: Prvulovic, Milos; Committee Member: Yalamanchili, Sudhakar; Committee Member: Yoder, Douglas.

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45

Chamdani, Joseph Irawan. "Microarchitecture techniques to improve the design of superscalar microprocessors." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15509.

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46

Chiou, Derek. "Extending the reach of microprocessors : column and curious caching." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80200.

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47

Ham, Christopher V. "UTILIZING OFF-THE-SHELF MICROPROCESSORS FOR COMPLEX TELEMETRY PREPROCESSING." International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615416.

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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada<br>This paper describes a system utilizing off-the-shelf microprocessor hardware to perform complex high-speed telemetry data preprocessing. The microprocessor equipment involves the latest in the Motorola computer series, namely the 68020 line. The author develops the specifications leading to the need of this type of preprocessor which is currently being developed under a contract to the McDonnell Douglas Helicopter Company. The paper fully describes the configuration of the hardware as

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48

Wei, Jia. "High Frequency High-Efficiency Voltage Regulators for Future Microprocessors." Diss., Virginia Tech, 2004. http://hdl.handle.net/10919/11254.

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Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to

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49

Renaghan, Liam Eamon. "On-Chip Isotropic Microchannels for Cooling Three Dimensional Microprocessors." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/36404.

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This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by be

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50

Krishnamurthy, Sivasubramaniam T. "STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

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