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1
Kim, Tong-Ho. "Solid source molecular beam epitaxy of InP-based composite-channel high electron mobility transistor structures of microwave and millimeter-wave power applications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14859.
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Sayyah, Ali Afkari. "The design of power combined oscillators suitable for millimetre-wave development." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phs275.pdf.
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Yoo, Seungyup. "Field effect transistor noise model analysis and low noise amplifier design for wireless data communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13024.
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Schwierz, Frank Liou Juin J. "Modern microwave transistors : theory, design and performance /." Hoboken, NJ : Wiley-Interscience, 2003. http://www.loc.gov/catdir/toc/wiley023/2002027230.html.
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Barkhordarian, V. "The design and fabrication of Microwave Field-Effect Transistors." Thesis, University of Leeds, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233220.
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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices." Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.
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"2009"Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
xxii, 166 p. : ill (some col.)
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Cinar, Kamil. "Design And Construction Of A Microwave Plasma Ion Source." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612910/index.pdf.
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This thesis is about the designing and constructing a microwave ion source. The ions are generated in a thermal and dense hydrogen plasma by microwave induction. The plasma is generated by using a microwave source with a frequency of 2.45 GHz and a power of 700 W. The generated microwave is pulsing with a frequency of 50 Hz. The designed and constructed microwave system generates hydrogen plasma in a pyrex plasma chamber. Moreover, an ion extraction unit is designed and constructed in order to extract the ions from the generated hydrogen plasma. The ion beam extraction is achieved and ion currents are measured. Th e plasma parameters are determined by a double Langmuir probe and the ion current is measured by a Faraday cup. The designed ion extraction unit is simulated by using the dimensions of the designed and constructed ion extraction unit in order to trace out the trajectories of the extracted ions.
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Keogh, David Martin. "Design and fabrication of InGaN/GaN heterojunction bipolar transistors for microwave power amplifiers." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237565.
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Thesis (Ph. D.)--University of California, San Diego, 2006.Title from first page of PDF file (viewed December 13, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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Andrews, Joel. "Design of SiGe HBT power amplifiers for microwave radar applications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28116.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Member: John Cressler; Committee Member: John Papapolymerou; Committee Member: Joy Laskar; Committee Member: Thomas Morley; Committee Member: William Hunt.
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Sung, YunMo. "Critical analysis of SiC SIT design and performance based upon material and device properties." Diss., Mississippi State : Mississippi State University, 2005. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.
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Sotoodeh, Mohammed. "Design, characterisation, and numerical simulation of double heterojunction bipolar transistors for microwave power applications." Thesis, King's College London (University of London), 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.367945.
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Staiculescu, Daniela. "Design rules for RF and microwave flip-chip." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13265.
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Teru, Agboola Awolola. "Efficient rectenna circuits for microwave wireless power transmission." Thesis, University of Fort Hare, 2010. http://hdl.handle.net/10353/481.
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Miniaturisation has been the holy grail of mobile technology. The ability to move around with our gadgets, especially the ones for communication and entertainment, has been what semiconductor scientists have battled over the past decades. Miniaturisation brings about reduced consumption in power and ease of mobility. However, the main impediment to untethered mobility of our gadgets has been the lack of unlimited power supply. The battery had filled this gap for some time, but due to the increased functionalities of these mobile gadgets, increasing the battery capacity would increase the weight of the device considerably that it would eventually become too heavy to carry around. Moreover, the fact that these batteries need to be recharged means we are still not completely free of power cords. The advent of low powered micro-controllers and sensors has created a huge industry for more powerful devices that consume a lot less power. These devices have encouraged hardware designers to reduce the power consumption of the gadgets. This has encouraged the idea of wireless power transmission on another level. With lots of radio frequency energy all around us, from our cordless phones to the numerous mobile cell sites there has not been a better time to delve more into research on WPT. This study looks at the feasibilities of WPT in small device applications where very low power is consumed to carry out some important functionality. The work done here compared two rectifying circuits’ efficiencies and ways to improve on the overall efficiencies. The results obtained show that the full wave rectifier would be the better option when designing a WPT system as more power can be drawn from the rectenna. The load also had a great role as this determined the amount of power drawn from the circuitry.
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Abdeen, Mohammad. "Modeling of the single- and dual-gate microwave field effect transistors for computer aided design." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/29071.
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The increasing need for advanced communication technologies in the 21 st century is leading to continuous development of new and more complex active devices and systems. Transistors such as BJTs, HBTs, FETs, and HEMTs are fundamental components in today's personal, corporate and global communication systems.
The single- and dual-gate MESFETs are widely used devices with wide areas of RF/Microwave applications. Due to their superior performance, MESFETs have been extensively used in high frequency, high-gain, and low-noise amplifiers, oscillator, mixers, and many other applications.
In this thesis, conventional and intelligent modeling methodologies are investigated for the applicability to today's computer-aided design methodologies and tools. Novel approaches of this work are applied to the area of small- and large-signal modeling of the GaAs MESFET (the single- and dual-gate.)
Optimal models for the single-gate MESFET are obtained using conventional techniques. A CAD tool called, TopFinder, is developed for optimal small and large-signal model generation. The tool has been successfully tested on a commercial single-gate MESFET and HEMT transistors.
Neural network modeling technique is applied to the modeling of the dual-gate MESFET. More specifically, neural network large-signal models for the dual-gate MESFET are developed. These models present the RF device performance behavior including temperature dependence. The neural network technique is successfully applied to two dual-gate MESFET devices; a discrete chip and an on-wafer chip. First, the drain current is modeled while presenting both isothermal (using pulsed measurements) and temperature dependent neural network model for the dual-gate MESFET. A comprehensive large-signal neural network model is also developed. This model includes the nonlinearity of conductances as well as those of the junction capacitances. The nonlinear dual-gate MESFET model is successfully incorporated into ADS. The model is verified by comparing the measurements of a nonlinear single-stage amplifier application based on the dual-gate MESFET to harmonic balance simulations in ADS showing satisfactory results.
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Adil, Farhan. "Offset reduction using floating-gate devices." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14945.
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Sutherland, David B. "Self-aligned gallium arsenide MESFETs for microwave integrated circuits." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28522.
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A refractory self-aligned gate fabrication process for gallium arsenide MESFETs has been developed and applied to a sample and hold circuit. The process has been shown to reduce the parasitic end resistance of MESFETs which can be a limiting factor in their microwave performance. A mask set was designed to be compatible with Cascade Inc. probes which allowed on chip microwave measurements to be made. Usable gain was measured up to 18GHz on FETs and 5GHz on buffer amplifiers with the microwave probes at the Communications Research Centre in Ottawa Ontario. The microwave probes were also used to test sample and hold operation. The maximum tested sampling rate was limited by the test equipment to 250 MHz.
The fabrication process included a plasma etch for producing an undercut 'T' gate structure for self-aligned ion implantation. A method of sputtering a thermally stable alloy of TiW refractory metal was developed to provide suitable Schottky contacts to GaAs. It was found that a rapid thermal anneal following the self-aligned implant maintained suitable TiW/GaAs Schottky characteristics and yielded MESFETs with reduced end resistance when compared to those fabricated by the more conventional selective implant process. A technique was developed to reduce the gate resistance of self-aligned MESFETs using an evaporated metal overlayer. Also, procedures for fabricating airbridges using a single evaporation and Metal-Insulator-Metal (MIM) capacitors using silicon nitride as the dielectric were developed. The effect of gate resistance on the microwave performance of the self-aligned MESFETs was investigated by modeling with the EEsof Inc. microwave software package, Touchstone. The modeling showed that self-aligned MESFETs are capable of giving greater high frequency gain than are selective implant devices with the same design geometry. The operation of the sample and hold circuit was simulated using a version of SPICE that included the Sussman Fort GaAs MESFET model. The simulations showed that the sample and hold could be used for gigahertz sampling.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Zhou, Mi. "Design of Tunable/Reconfigurable and Compact Microwave Devices." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc500093/.
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With the rapid development of the modern technology, radio frequency and microwave systems are playing more and more important roles. Since the time the first microwave device was invented, they have been leading not only the military but also our daily life to a new era. In order to make the devices have more practical applications, more and more strict requirements have been imposed. For example, good adaptability, reduced cost and shrank size are highly required. In this thesis, three devices are designed based on this requirement. At first, a symmetric four-port microwave varactor based 90-degree directional coupler with tunable coupling ratios and reconfigurable responses is presented. The proposed coupler is designed based on the modified structure of a crossover, where varactors are loaded. Then, a novel reconfigurable 3-dB directional coupler is presented. Varactors and inductors are loaded to the device to realize the reconfigurable performance. By adjusting the voltage applied to the varactors, the proposed coupler can be reconfigured from a branch-line coupler (90-degree coupler) to a rat-race coupler (180 degree coupler) and vice versa. At last, two types (Type-I and Type-II) of microwave baluns with generalized structures are presented. Different from the conventional transmission-line-based baluns where λ/2 transmission lines or λ/4 coupled lines are used, the proposed baluns are constructed by transmission lines with arbitrary electrical lengths.
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Kim, Taehoon. "Design, fabrication, and analysis of enhanced mobility silicon germanium transistors." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3034553.
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Cheung, Chi-chuen Cecil, and 張志泉. "Device design and fabrication of InGaP/GaAsSb/GaAs DHBTs." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2003. http://hub.hku.hk/bib/B29753727.
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Brooks, David J. "Design, construction, and application of a microwave-induced plasma reactor to solid state chemistry." Thesis, University of York, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.421499.
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Thakare, Aditya. "A Study of Microwave curing of Underfill using Open and Closed microwave ovens." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2246.
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As the demand for microprocessors is increasing with more and more consumers using integrated circuits in their daily life, the demand on the industry is increasing to ramp up production.
In order to speed up the manufacturing processes, new and novel approaches are trying to change certain aspects of it. Microwaves have been tried as an alternative to conventional ovens in the curing of the polymers used as underfills and encapsulants in integrated circuits packages. Microwaves however being electromagnetic waves have non uniform energy distribution in different settings, causing burning or incomplete cure of polymers.
In this study, we compare the two main types of microwaves proposed to perform the task of curing the polymers. To limit the study and obtain comparable results, both microwaves were limited to propagate in a single mode, TE10. The first is a closed microwave cavity using air as the propagation medium, and the second is an open microwave oven with a PTFE cavity that uses an evanescent field to provide energy.
The open air cavity was studied with different orientations of a substrate placed inside it so as to find the best case scenario in the curing process. This scenario was then compared with the best case scenario found for a sample cured in an evanescent field.
This comparison yielded results showing an advantage of the open microwave in maximum field present, thus leading to higher localized energy absorption and temperatures in the substrate, however this case also lead to a higher temperature gradient. The substrate cured in the closed microwave has a lower temperature gradient, but also a lower maximum field which leads to slower cure.
In the TE10 mode therefore, a closed microwave has an overall advantage as the heating process is only slightly slower than that of an open cavity, but the temperature gradient in this case is significantly lower.
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Matinpour, Babak. "Development of a compact monolithic direct down-conversion microwave receiver for wireless applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13721.
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Chin, Shaoan. "MOS-bipolar composite power switching devices." Diss., Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/54275.
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Two MOS-Bipolar composite power semiconductor switching devices are proposed and experimentally demonstrated. These devices feature high voltage and high current capabilities, fast switching speeds, simple gate drive requirements, savings in chip area, reverse bias second breakdown ruggedness and large safe operating areas. Application characteristics of the devices for high frequency power inverter circuits are discussed. Monolithic integration of the two composite devices are also proposed.Ph. D.
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Wang, Li Kang. "Design of ultra-wideabnd [sic] bandpass filter with reconfigurable bandwidth and notch using microstrip and slotline structure." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691126.
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Overstreet, William Patton. "VHF bipolar transistor power amplifiers: measurement, modeling, and design." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71166.
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Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results.
The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation.
Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report.Ph. D.
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Cresci, David John. "On-wafer characterization of ground vias in multilayer FR-4 printed circuit boards at RF/microwave frequencies." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15806.
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Pratap, Rana Jitendra. "Design and Optimization of Microwave Circuits and Systems Using Artificial Intelligence Techniques." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7225.
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In this thesis, a new approach combining neural networks and genetic algorithms is presented for microwave design. In this method, an accurate neural network model is developed from the experimental data. This neural network model is used to perform sensitivity analysis and derive response surfaces. An innovative technique is then applied in which genetic algorithms are coupled with the neural network model to assist in synthesis and optimization. The proposed method is used for modeling and analysis of circuit parameters for flip chip interconnects up to 35 GHz, as well as for design of multilayer inductors and capacitors at 1.9 GHz and 2.4 GHz. The method was also used to synthesize mm wave low pass filters in the range of 40-60 GHz. The devices obtained from layout parameters predicted by the neuro-genetic design method yielded electrical response close to the desired value (95% accuracy). The proposed method also implements a weighted priority scheme to account for tradeoffs in microwave design. This scheme was implemented to synthesize bandpass filters for 802.11a and HIPERLAN wireless LAN applications in the range of 5-6 GHz.
This research also develops a novel neuro-genetic design centering methodology for yield enhancement and design for manufacturability of microwave devices and circuits. A neural network model is used to calculate yield using Monte Carlo methods. A genetic algorithm is then used for yield optimization. The proposed method has been used for yield enhancement of SiGe heterojunction bipolar transistor and mm wave voltage-controlled oscillator. It results in significant yield enhancement of the SiGe HBTs (from 25 % to 75 %) and VCOs (from 8 % to 85 %). The proposed method is can be extended for device, circuit, package, and system level integrated co-design since it can handle a large number of design variables without any assumptions about the component behavior. The proposed algorithm could be used by microwave community for design and optimization of microwave circuits and systems with greater accuracy while consuming less computational time.
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Alwardi, Milad. "Design and characterization of integrating silicon junction field-effect transistor amplifiers for operation in the temperature range 40-77 K." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184871.
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The very low photon backgrounds to be achieved by future cryogenic astronomical telescopes present the ultimate challenge to the sensitivity of infrared detectors and associated readout electronics. Cooled silicon JFETs, operated around 70 K in transimpedance amplifiers, have shown excellent performance and stability. However, due to Johnson noise in the feedback resistor, the read noise in one second achieved by such amplifiers is about 500 electrons per second. A drastic improvement in sensitivity was demonstrated using a simple form of integrating JFET amplifiers. Therefore, the excellent performance obtained with cooled silicon JFETs has led to the investigation of their properties in the temperature range 33-77 K to explore their full potential and improve the performance of the integrating amplifier. The freezeout effect in silicon JFETs has been characterized both experimentally and theoretically using a simple analytical simulation program. The effect of variation in device parameters on the freezeout characteristic has been studied, and test results showed that an effective channel mobility must be used instead of a bulk mobility in order to simulate accurately the device current and transconductance freezeout at low temperatures. Many types of commercially available JFETs have been characterized below 77 K and measurements revealed that a balanced source follower or a common-source amplifier with active load can operate well down to 38 Kelvin with extremely low power dissipation. The open gate equivalent input noise voltage was found to be optimum below 77 K, due to a decrease in the gate leakage current, in agreement with theoretical prediction. Based on the superior performance of the balanced source follower with active load, a single channel hybrid integrating JFET amplifier with a JFET reset and a compensation capacitor was developed for operation in the temperature range 40-77 K. Read noise as low as 10 electrons in 128 seconds integration was achieved when the integrator was operated at an optimum temperature of about 55 K. Using a similar design, a 16-channel monolithic integrating amplifier array was designed and built. Preliminary test results at 77 K showed noise performance comparable to the single channel hybrid integrator.
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Marrett, Courtney Elizabeth. "Synthesis of composites for use in the rapid manufacturing of electronic/microwave devices." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/16677.
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Pietersen, Richard Gordon. "Thermoelectric cooling for microwave transmitters located at remote sites." Thesis, Cape Technikon, 1992. http://hdl.handle.net/20.500.11838/2158.
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Thesis (MDiploma (Mechanical Engineering))--Cape Technikon, 1992.An investigation into the use of thermoelectric cooling energised by photovoltaic (PV) panels for removing sensible heat from electronic telecommunications equipment. The thermoelectric cooler consists of a solid-state heat pump which operates on the principle of the Peltier effect. The thermoelectric device transfers heat through a cold sink to ambient outside air via a hot sink. A major prerequisite was that the system should be selfsufficient in terms of power because the sites for the microwave transmitters are often remote. Solar power was the only alternative source of energy and the cooler was designed to accept direct current from PV panels which are usually used to power transmitters on distant locations. The cooling device had to be reliable, virtually maintenance-free and simple to repair.
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Matinpour, Babak. "Design and development of compact and monolithic direct conversion receivers." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14991.
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Nayeem, Mustayeen B. "Applied mechanical tensile strain effects on silicon bipolar and silicon-germanium heterojunction bipolar devices." Thesis, Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-07182005-102447/.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006.Dr. John D. Cressler, Committee Chair ; John Papapolymerou, Committee Member ; Joy Laskar, Committee Member.
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Low, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.
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Constantin, Nicolas 1964. "Analysis and design of a gated envelope feedback technique for automatic hardware reconfiguration of RFIC power amplifiers, with full on-chip implementation in gallium arsenide heterojunction bipolar transistor technology." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=115666.
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In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers.A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations.
The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities.
Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.
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Ashraf, Rehman. "Robust Circuit & Architecture Design in the Nanoscale Regime." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/240.
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Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed. An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates.
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Cheng, Kam-ho, and 鄭錦豪. "A study on novel organic semiconductor devices: light-emitting diode and thin-film transistor." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2009. http://hub.hku.hk/bib/B43085519.
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Kang, Sangbeom. "The epitaxial growth of GaN and A1GaN/GaN Heterostructure Field Effect Transistors (HFET) on Lithium Gallate (LiGaO₂) substrates." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/13903.
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Vermaak, Elrien. "Development of a low phase noise microwave voltage controlled oscillator." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1940.
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Baker, Bryant. "A 3.6 GHz Doherty Power Amplifier with a 40 dBm Saturated Output Power using GaN on SiC HEMT Devices." PDXScholar, 2014. https://pdxscholar.library.pdx.edu/open_access_etds/1781.
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This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time.
The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier.
The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR).
The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.
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Thompson, Dane C. "Characterization and Design of Liquid Crystal Polymer (LCP) Based Multilayer RF Components and Packages." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10498.
Full textAbstract:
This thesis discusses the investigation and utilization of a new promising thin-film material, liquid crystal polymer (LCP), for microwave and millimeter-wave (mm-wave [>30 GHz]) components and packages. The contribution of this research is in the determination of LCP's electrical and mechanical properties as they pertain to use in radio frequency (RF) systems up to mm-wave frequencies, and in evaluating LCP as a low-cost substrate and packaging material alternative to the hermetic materials traditionally desired for microwave circuits at frequencies above a few gigahertz (GHz).
A study of LCP's mm-wave material properties was performed. Resonant circuit structures were designed to find the dielectric constant and loss tangent from 2-110 GHz under both ambient and elevated temperature conditions. Several unique processes were developed for the realization of novel multilayer LCP-based RF circuits. These processes include thermocompression bonding with tight temperature control (within a few degrees Celsius), precise multilayer alignment and patterning, and LCP laser processing with three different types of lasers. A proof-of-concept design that resulted from this research was a dual-frequency dual-polarization antenna array operating at 14 and 35 GHz.
Device characterization such as mechanical flexibility testing of antennas and seal testing of packages were also performed. A low-loss interconnect was developed for laser-machined system-level thin-film LCP packages. These packages were designed for and measured with both RF micro-electromechanical (MEM) switches and monolithic microwave integrated circuits (MMICs). These research findings have shown LCP to
be a material with uniquely attractive properties/capabilities for vertically integrated, compact multilayer LCP circuits and modules.
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Mays, Kenneth W. "A 40 GHz Power Amplifier Using a Low Cost High Volume 0.15 um Optical Lithography pHEMT Process." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/552.
Full textAbstract:
The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.
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Awad, Mohamad. "Conception d'un circuit electonique pour la récupération d'énergie électromagnétique en technologie FDSOI 28 nm." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT060/document.
Full textAbstract:
La récupération d’énergie est un thème de recherche prometteur qui explore un large éventail de sources. Parmi ces sources, on trouve l’énergie mécanique, thermique, électromagnétique, etc. Cette thèse se propose d’explorer des solutions techniques de récupération de l’énergie électromagnétique ambiante. Ce type d’énergie offre une belle opportunité pour participer à l’alimentation, partielle ou complète, d’un système de communication sans fil à basse consommation. Beaucoup d’applications intéressantes telles que les réseaux de capteurs sans fil (WSN), assurant ainsi l’IoT (internet of things), dans le domaine médical et dans la sécurité, sont dotés d’une antenne. Or cette antenne qui est un composant passif volumineux n’est utilisée qu’une faible fraction du temps pour les seules communications. Dans le cadre de la récupération d’énergie RF, l’idée est de mettre à profit ce composant pour glaner l’énergie électromagnétique ambiante, malgré la faible puissance récupérée. Associée à l’antenne, la récupération d’énergie RF est basée sur la mise en œuvre de diodes en redresseurs. Dans ce manuscrit, des diodes intégrées issues d’une technologie moderne : FDSOI 28 nm sont utilisées.A l’issue de ces travaux, trois « runs » dont deux en technologie FDSOI ont pu être réalisés. Des convertisseurs d’énergie RF, du type Dickson, d’un et deux étages, ont été conçus et réalisés à l’aide de cette technologie, mesurés et même comparés à des convertisseurs RF-DC réalisés avec une autre technologie BiCMOS 55 nm. Les convertisseurs réalisés sont à l’état de l’art au niveau du rendement de conversion énergétique pour une puissance donnée de l’ordre de -20 dBm. La technologie FD-SOI offre un nouveau degré de liberté à l’aide de la polarisation de la grille arrière (BG : Back Gate). Cette polarisation du BG permet de modifier les paramètres de l’élément non-linéaire à la base de la conversion. Par ailleurs, une étude sur la réalisation d’une diode Schottky intégrée dans le processus de la FDSOI 28 nm a même été envisagée. A l’issue de ces premières expériences, une méthode d’optimisation de la conception de ces convertisseurs Dickson à partir d’un cahier des charges simplifiée, a été proposéeEnergy harvesting is a promising research theme which analyzes a wide range of sources for the application. These sources can be mechanical, thermal or electromagnetic, etc. Hereby, the work presented explores technical solutions for ambient electromagnetic energy harvesting. Electromagnetic energy is capable of partly or completely supplying energy to low-power wireless communication systems. Many interesting applications are feasible, such as, wireless sensor networks (WSN) ensuring IoT (Internet-of-Things), in the medical field, security, by using equipments containing an antenna. However, the antenna is a voluminous passive component which is utilized merely for a fraction of the time, i.e., just for communications. The underlying idea of RF energy harvesting is to use the antenna to harvest the ambient electromagnetic energy, despite the low power recovered. Associated with the antenna, the RF energy harvesting is based on implementing diodes in rectifiers. In this manuscript, integrated diodes from modern technology: FD-SOI 28 nm are studied.In this work, three run for RF energy harvesting are designed. Two of them are realized in FD-SOI technology. One and two stage Dickson rectifiers for RF energy harvesting using FD-SOI are designed, characterized, measured and compared to RF-DC converters made with 55nm BiCMOS technology. These rectifiers are state-of-the-art in terms of the power conversion efficiency for a given power of the order of -20 dBm. Furthermore, FD-SOI technology offers a new degree of freedom with the back gate polarization (BG). This polarization of the BG makes it viable to change the parameters of the non-linear elements at the base of the conversion. Moreover, an investigation of integrated Schottky diodes using FDSOI 28 nm is presented. At the end of these experiments, a method of optimizing of the design of these Dickson converters based on simplified specifications is proposed
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Venkataraman, Sunitha. "Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.
Full textAbstract:
The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory.
This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions.
The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications.
This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.
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Liu, Xiang. "Reliability study of InGaP/GaAs heterojunction bipolar transistor MMIC technology by characterization, modeling and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4967.
Full textAbstract:
HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBT-based MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBT-based MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future.; Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fsubscript T] and fsubscript max] as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region.ID: 030423028; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 82-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
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Peršun, Marijan. "Scaling of the Silicon-on-Insulator Si and Si1-xGex p-MOSFETs." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4934.
Full textAbstract:
Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gate design with low body doping. Then+ gate design is more suited for the design of fully depleted (FD) devices since we need to keep the doping low to minimize the threshold adjustment implant dose and to use thin silicon films to control the SCE. The design of both p-MOSFET and Si 1-xGex p-MOSFET requires the implantation for the threshold voltage adjustment. The p+ gate design is more suited for the partially depleted (PD) or near-fully depleted device design since we need to use high doping for the threshold voltage adjustment and this results in large threshold voltage sensitivity to silicon film thickness for FD devices. The design of Si SOI p-MOSFET is done by properly adjusting the body doping. For the Si1-xGex SOI p-MOSFET large reduction in VTH requires large body doping. This increases the parasitic capacitances and slows down the device.
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Zhou, Sida. "Mobility Modeling and Simulation of SOI Si1-x Gex p-MOSFET." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4954.
Full textAbstract:
With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si 1_xGex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si 1_xGex channel. A high mobility p-MOSFET would improve both the circuit speed and the level of integration. The purpose of the present study was to model and simulate the effective mobility (μeff) of SOI Si 1-xGex p-MOSFET, and to investigate the suitability of local mobility models provided by simulator MEDICI for studying SOI Si 1_xGex p-MOSFET. The simulation is performed by using the two-dimensional device simulation program (MEDICI). The design parameters, such as Si-cap thickness, Ge profile and back-gate bias, were also investigated. A long channel (6μ) and a short channel (0.25μ) SOI and bulk Si 1_xGex p MOSFET were used for the study. Simulation reveals good effective mobility μeff match with experimental results if Si Ge channel of p-MOSFET can simply be treated like a bulk silicon with mobility 250cm2 /Vs. Mobility models provided by MEDICI are two types: a) mobility model (SRFMOB2) that is dependent on transverse electric field only at Si/ Si02 interface, which means that the effective mobility is a function of grid spacing at Si/ Si02 interface, and b) mobility models (PRPMOB, LSMMOB and HPMOB) that are dependent on transverse electric field anywhere in the device. PRPMOB and LSMMOB produce very good μef f and are insensitive to the grid spacing. HP MOB gives slight over estimation of effective mobility μef f. Silicon cap thickness can significantly influence the effective mobility μef f. In general, the thin silicon cap have better effective mobility μef f, but it is limited by manufacturing process. Graded Si 1_:z:Ge:z: channel presents nearly 100% improvement of effective mobility μeff for p-MOSFET over its bulk counterpart. This improvement is sustained up to gate voltage of 2.5 V. Simulation also indicates that large improvement of effective mobility μef f requires higher Ge concentration at the top of SiGe channel with steep grading. The influence of back-gate bias on μeff is small, hence, SOI SiGe MOSFET is well suited to building CMOS circuits.
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Caenepeel, Matthias. "Techniques de modélisation pour une conception efficace de filtres passe-bande micro-ondes." Thesis, Université Côte d'Azur (ComUE), 2016. http://www.theses.fr/2016AZUR4052.
Full textAbstract:
La conception de filtres hautes fréquences requiert l’optimisation des paramètres physiques du filtre afin d’obtenir une réponse en fréquence qui remplit les conditions imposées par le gabarit de fréquence. Cette optimisation dépend de simulations électromagnétiques. La résolution de ces équations aux dérivées partielles étant très couteuse en temps de calcul, nous proposons de développer des modèles pour le filtre qui permettent de réduire le nombre de simulations EM nécessaires au réglage du filtre. Le but recherché est d’incorporer ces modèles dans une méthode de conception assistée par ordinateur. Dans cette thèse, je propose différentes approches pour la modélisation du filtre. La première approche utilise la matrice de couplage du filtre, qu’elle décrit en fonction des paramètres physiques. La deuxième approche modélise les paramètres S en fonction de ces mêmes paramètres. Dans la première méthode, on se concentre essentiellement sur l’extraction de la matrice de couplage physique. On introduit une technique pour estimer la matrice de sensibilité (le Jacobien) qui lie les paramètres physiques aux paramètres de couplage. Cette estimation utilise les sensibilités adjointes des paramètres. L’utilisation de cette information réduit drastiquement le nombre de simulations EM et donc le temps de calcul global. Une deuxième approche utilise le concept de méta-modèle. L’idée maitresse de cette approche est que l’évaluation de ce modèle est numériquement beaucoup plus avantageuse que celle des simulations EM. Les méthodes développées sont tour à tour appliquées à la conception de filtres complexes qui sont réalisés en technologie microstripThe design of microwave bandpass filter generally requires optimization or fine-tuning of the physical design parameters in order to meet the electrical specifications given by a frequency template. In this thesis we develop models to assist the designer in the time-efficient physical design of the distributed element microwave filters. The aim is to incorporate these models in different CAD methods. By a time-efficient design, we mean a design that requires a low number of EM simulations. The EM-simulations typically represent the most time-consuming step during the optimization process. We propose different modeling approaches for the frequency response behavior of the filter. The first approach models the coupling matrix as a function of the physical design parameters and the second approach models the scattering parameters, again as a function of the physical parameters. In the first part we focus on the extraction of the coupling matrix. We introduce a novel CAT technique based on an efficient estimation of the Jacobian of the function relating the design parameters to the coupling parameters. The estimation of the Jacobian uses adjoint sensitivity analysis, which drastically reduces the number of required EM-simulations. In the second part of the thesis we propose an alternative modeling approach which is based on the concept of a metamodel. The idea is that the metamodel is numerically much cheaper to evaluate than the original simulation model while keeping an acceptable accuracy. We apply these methods to several state of-the-art microstrip bandpass filters
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.
Full textAbstract:
Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.
The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Courty, Alexis. "Architecture d'amplificateur de puissance linéaire et à haut rendement en technologie GaN de type Doherty numérique." Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0067/document.
Full textAbstract:
Les fortes capacités actuelles et envisagées des futurs liens satellites de communication pour la 5G conduisent les signaux traités dans les charges utiles à présenter simultanément d'importantes variations d'amplitude (PAPR>10dB) et de très larges bandes passantes instantanées (BW>1GHz). A l'intérieur du sous-système d'émission hyperfréquence, le fonctionnement du module d'amplification de puissance se trouve très contraint par les formes d'ondes véhiculées, il se présente comme l'un des postes de consommation énergétique des plus importants, et ayant le plus d'impact sur l'intégrité du signal émis. Dans ce contexte, les fonctions dédiées au traitement numérique des signaux et couramment implémentées par le processeur numérique (telles que le filtrage, la canalisation, et éventuellement la démodulation et la régénération des signaux bande de base) embarquées dans les charges utiles, représentent une solution à fort potentiel qui permettrait de relâcher les contraintes reportées sur la fonction d'amplification de puissance afin de gérer au mieux la ressource électrique allouée. Ces travaux de thèse proposent d'étudier les potentialités d'amélioration du fonctionnement en rendement et linéarité d'un amplificateur de type Doherty à double entrée de gamme 20W en technologie GaN et fonctionnant en bande C. La combinaison des signaux de puissance sur la charge RF est optimisée par une distribution optimale des signaux en amplitude et phase à l'entrée par des moyens numériques de génération. Dans un premier temps une méthodologie de conception large bande d'un amplificateur Doherty est introduite et validée par la conception d'un démonstrateur en bande C. Dans un second temps, l'outil expérimental permettant l'extraction des lois optimales de distribution d'amplitude et de phase RF est présenté en détail, et la caractérisation expérimentale du dispositif en double entrée est réalisée puis comparée aux simulations. Finalement, en perspective à ces travaux, une étude préliminaire des potentialités de l'architecture Doherty à double entrée pour la gestion d’une désadaptation de la charge de sortie (gestion de TOS) est menée et des résultats sont mis en avantThe high capabilities of current and future 5G communication satellite links lead the processed signals in the payloads to simultaneously exhibit large amplitude variations (PAPR>10dB) and wide instantaneous bandwidths (BW>1GHz). Within the microwave transmission subsystem, the operation of the power amplification stage is highly constrained by the transmitted waveforms, it is one of the most energy-consuming module of the payload affecting as well the integrity of the transmitted signal. In this context, the functions dedicated to digital signal processing and currently implemented by the digital processor (such as filtering, channeling, and possibly the demodulation and regeneration of baseband signals) embedded in the payloads, represent a potential solution that would reduce the constraints reported on the power amplification function and help to manage the allocated power ressource. This work proposes a study on the capability of dual input power amplifier architectures in order to manage the efficiency-linearity trade-off over a wide bandwidth. This study is carried out on a 20W GaN Doherty demonstrator operating in C band. The combination of the output signals on the RF load is managed by an optimal amplitude and phase distribution that is digitally controlled at the input. Firstly, a wideband design methodology of Doherty amplifier is introduced and validated on a C band demonstrator. In a second time the experimental tool allowing the extraction of amplitude and phase input distributions is presented, the dual input characterization is achieved and compared with simulation results. Finally, in perspective of this work, a preliminary study of the capabilities of the digital Doherty for the management of an output load mismatch (VSWR management) is carried out and the results are put forward
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Yoo, Byungwook 1975. "New platforms for electronic devices: n-channel organic field-effect transistors, complementary circuits, and nanowire transistors." Thesis, 2007. http://hdl.handle.net/2152/3165.
Full textAbstract:
This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain.text