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Journal articles on the topic 'Mixed signal circuits Signal processing'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Kledrowetz, Vilem, Roman Prokop, Lukas Fujcik, Michal Pavlik, and Jiří Háze. "Low-power ASIC suitable for miniaturized wireless EMG systems." Journal of Electrical Engineering 70, no. 5 (2019): 393–99. http://dx.doi.org/10.2478/jee-2019-0071.

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Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

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Li, Bo, and Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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3

Strle, Drago, та Janez Trontelj. "On Self-Aware Mixed-Signal Systems Based on S-Δ ADC". International Journal of Embedded and Real-Time Communication Systems 3, № 2 (2012): 92–110. http://dx.doi.org/10.4018/jertcs.2012040105.

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In this paper the authors discuss the issues related to the self-awareness of high-resolution, mixed-signal circuits and systems, based on S-? ADC, which is the most important and sensitive module and the key element for analogue to digital conversion. The basic methodology and framework for improving the self-awareness of such systems are presented. The methodology is based on efficient real-time measurements of a high-resolution, mixed-signal system using pseudo random signal source, real-time calculation of a distance between responses, the possibility to adapt measured circuit to minimize the distance, and changing the parameters of a reference system according to learning rules. The use of pseudo-random noise as a signal source leads to efficient and cost-effective measurements that run in parallel to the main signal processing. The calculation of the distance between the system and its reference are theoretically analysed and verified using Matlab model. The response of a system together with the response of high precision analogue to digital converter (ADC) is compared to the response of a bit-true model of a reference digital circuit. The differences are calculated using simple area-efficient cross-correlation algorithm. Together with adaptation strategy and tuning circuitry it forms the basis for self-awareness of mixed-signal circuits.

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Orcioni, Simone, Giorgio Biagetti, and Massimo Conti. "A Mixed Signal Fuzzy Controller Using Current Mode Circuits." Analog Integrated Circuits and Signal Processing 38, no. 2/3 (2004): 215–31. http://dx.doi.org/10.1023/b:alog.0000011169.98696.87.

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5

Zhao, Wen Li, Yuan Ping Yin, and Jin Liu. "Medium-Low-Frequency Signal Detection and Simulation Based on the Principle of Stochastic Resonance." Applied Mechanics and Materials 105-107 (September 2011): 1991–94. http://dx.doi.org/10.4028/www.scientific.net/amm.105-107.1991.

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The principle of stochastic resonance in bistable system is introduced firstly. The medium-low-frequency periodic signal and multi-frequency harmonic signal (the large parameter signal) are common in mechanical failure, but it is difficult to achieve stochastic resonance in these signals detection. The signal modulation characteristic is used in this paper to transform the various frequency components into small parameter signals which satisfy the adiabatic approximation theory. On the basis of that, weak signal detection based on stochastic resonance theory is realized. Then a mixing circuit system based on stochastic resonance is designed, the circuit first makes a frequency selection processing with a mixer on the mixed signal between the measurable signal and a scanning signal, and then it is input to the nonlinear bistable system to realize signal detection based on stochastic resonance. At last, the MATLAB simulation result shows that the circuit can realize the stochastic resonance and detection of weak periodic signal in medium-low frequency from noise background.

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6

Materka, Andrzej, and Michal Strzelecki. "Parametric testing of mixed-signal circuits by ANN processing of transient responses." Journal of Electronic Testing 9, no. 1-2 (1996): 187–202. http://dx.doi.org/10.1007/bf00137574.

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7

NICODIMUS, R. A. "Active Shield Circuit for Digital Noise Suppression in Mixed-Signal Integrated Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 2 (2005): 438–43. http://dx.doi.org/10.1093/ietfec/e88-a.2.438.

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8

Khemchandani, Sunil L., Javier del Pino, Enrique López-Morillo, et al. "RF and mixed signal circuits for a DVB-H receiver." Analog Integrated Circuits and Signal Processing 65, no. 1 (2010): 1–14. http://dx.doi.org/10.1007/s10470-010-9452-1.

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9

Ryndin, Konoplev, Lysenko, Kulikova, and Popov. "Highly Sensitive Signal Processing Devices for Capacitive Transducers of Micromechanical Accelerometers." Electronics 8, no. 9 (2019): 932. http://dx.doi.org/10.3390/electronics8090932.

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In this paper, the principles of the open-loop frequency-based signal processing devices for capacitive MEMS accelerometers are used to develop three CMOS IP-core (Intellectual Property core) projects of highly sensitive signal processing devices with frequency output. Signal processing devices designed in accordance with the considered method form an output of rectangular pulses whose frequencies equal a difference of signal frequencies from two identical generators with micromechanical accelerometer capacitive transducers in their frequency control circuits. First, the analog project scheme uses two harmonic LC oscillators and an analog mixer to form an output rectangular-shape differential-frequency signal, the frequency of which is dependent on the measured acceleration. Second, the digital project is fully scalable for various CMOS-technologies due to oscillators of rectangular pulses and a digital mixer. Third, the mixed-signal project combines the advantages of the analog and digital projects. The signal processing device projects were developed, modeled and compared to comprehensively solve the problems of increasing sensitivity, dynamic range, noise immunity and resistance to destabilizing factors (e.g., to temperature changes).

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10

Vasudeva, G., and Uma B. V. "22nm FINFET Based High Gain Wide Band Differential Amplifier." International Journal of Circuits, Systems and Signal Processing 15 (February 5, 2021): 55–62. http://dx.doi.org/10.46300/9106.2021.15.7.

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Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

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11

Moaiyeri, Mohammad Hossein, Reza Chavoshisani, Ali Jalali, Keivan Navi, and Omid Hashemipour. "High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology." Circuits, Systems, and Signal Processing 31, no. 2 (2011): 465–88. http://dx.doi.org/10.1007/s00034-011-9344-3.

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12

Perera, Sirani M., Viduneth Ariyarathna, Nilan Udayanga, et al. "Wideband $N$ -Beam Arrays Using Low-Complexity Algorithms and Mixed-Signal Integrated Circuits." IEEE Journal of Selected Topics in Signal Processing 12, no. 2 (2018): 368–82. http://dx.doi.org/10.1109/jstsp.2018.2822940.

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13

Lee, Nai-Chi. "A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards." Analog Integrated Circuits and Signal Processing 4, no. 3 (1993): 261–68. http://dx.doi.org/10.1007/bf01239078.

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14

Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

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15

Gustard, N. C., and R. E. Massara. "On the optimal design of switched-capacitor filter circuits for analog and mixed-signal integrated circuit realization." Analog Integrated Circuits and Signal Processing 6, no. 3 (1994): 219–29. http://dx.doi.org/10.1007/bf01238890.

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16

Rashidzadeh, Rashid, Majid Ahmadi, and William C. Miller. "On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique." Analog Integrated Circuits and Signal Processing 50, no. 2 (2006): 105–13. http://dx.doi.org/10.1007/s10470-006-9013-9.

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17

Kundu, Sudip, Siddhartha Sarkar, Pradip Mandal, and Aminul Islam. "Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems." Analog Integrated Circuits and Signal Processing 99, no. 1 (2018): 95–109. http://dx.doi.org/10.1007/s10470-018-1310-6.

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18

Pandiev, Ivailo M., and Mariya P. Aleksandrova. "Dynamic FPAA-based Mixed-Signal Processing Circuit for Thin-Film CdTe/Lead-Free Perovskite Photodetectors." Elektronika ir Elektrotechnika 27, no. 2 (2021): 22–30. http://dx.doi.org/10.5755/j02.eie.28751.

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New photodetector structure combining thinned CdTe film with lead-free perovskite photoelectric film was produced and investigated. This setting of the CdTe thickness results in photodetector parameters’ competitiveness to the state-of-the-art in the field of advanced photoelectric materials. The device shows a promising sensitivity of ~40 μA/W, maximum responsivity of 10.6 mA/W at 460 nm, equal rise and fall times of 30 ms, and high linearity (maximum linearization error is less than 0.6 %). However, the optoelectronic performance of CdTe/lead-free perovskite structures integrated with signal processing circuit remains unexplored. For this purpose, Field Programmable Analogue Array (FPAA)-based mixed-signal processing circuit is developed for pulse width modulated electrical signal with duty cycle controlled by the illumination degree of the detecting photoelement. This novel approach guarantees a smooth change of the electrical output at a smooth change of the input illumination between the light and dark switching states and can be practically applied as a precise position detector of moving objects. The paper represents a synergistic connection between microelectronics, electronics, and signal technology.

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19

Dai, Lan, та Chengying Chen. "A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic". VLSI Design 2016 (29 грудня 2016): 1–7. http://dx.doi.org/10.1155/2016/6708253.

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A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.

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20

KOSAKA, D., M. NAGATA, Y. MURASAKA, and A. IWATA. "Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A, no. 2 (2007): 380–87. http://dx.doi.org/10.1093/ietfec/e90-a.2.380.

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21

Marszalek, Wieslaw, and Zdzislaw Trzaska. "Mixed-Mode Oscillations in a Modified Chua’s Circuit." Circuits, Systems and Signal Processing 29, no. 6 (2010): 1075–87. http://dx.doi.org/10.1007/s00034-010-9190-8.

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22

WANG, TONY, and L. A. AKERS. "AN ELECTRONIC HABITUATION CHIP." Journal of Circuits, Systems and Computers 06, no. 02 (1996): 155–69. http://dx.doi.org/10.1142/s0218126696000133.

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Habituation is a biological behavior allowing non-critical information to be disregarded enabling more processing resources for critical tasks. This requires the ability to determine if a signal is novel or not. We have implemented habituation adaptation in a small mixed signal circuit. A software simulation is used to demonstrate the ability of habituation to eliminate a stuck-at 1 error from succeeding stages of processing. Experimental test results are shown illustrating the habituation response.

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23

Arbel, Arie F. "Pure mode versus mixed mode interfacing between analog circuits." Analog Integrated Circuits and Signal Processing 4, no. 2 (1993): 167–72. http://dx.doi.org/10.1007/bf01254867.

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24

Vogelstein, R. Jacob, Udayan Mallik, Eugenio Culurciello, Gert Cauwenberghs, and Ralph Etienne-Cummings. "A Multichip Neuromorphic System for Spike-Based Visual Information Processing." Neural Computation 19, no. 9 (2007): 2281–300. http://dx.doi.org/10.1162/neco.2007.19.9.2281.

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We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 × 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

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25

Scheytt, J. Christoph, Abdul Rehman Javed, Eswara Rao Bammidi, Karthik KrishneGowda, Ingmar Kallfass, and Rolf Kraemer. "100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing." Frequenz 71, no. 9-10 (2017): 399–414. http://dx.doi.org/10.1515/freq-2017-0174.

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Abstract In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.

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26

Dualibe, Carlos, Paul Jespers, and Michel Verleysen. "Designing Mixed-Signal Programmable Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies." Journal of Integrated Circuits and Systems 1, no. 1 (2004): 14–22. http://dx.doi.org/10.29292/jics.v1i1.250.

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A digitally programmable analog Fuzzy Logic Controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimization of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: a 2.7% RMSE, from 2.22 to 5.26 Mflips (Mega fuzzy logic inferences per second) at the pin terminals (@CL=13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL≤ 5pF) up to 8 Mflips may be expected.

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27

Duarte-Villaseñor, Miguel Aurelio, Esteban Tlelo-Cuautle, and Luis Gerardo de la Fraga. "Binary Genetic Encoding for the Synthesis of Mixed-Mode Circuit Topologies." Circuits, Systems, and Signal Processing 31, no. 3 (2011): 849–63. http://dx.doi.org/10.1007/s00034-011-9353-2.

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28

Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.

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Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

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29

Liu, C. C., and S. Tiwari. "Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 3 (2006): 207–11. http://dx.doi.org/10.1109/tcsii.2005.857538.

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30

Dogaru, R., P. Julian, L. O. Chua, and M. Glesner. "The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications." IEEE Transactions on Neural Networks 13, no. 4 (2002): 995–1008. http://dx.doi.org/10.1109/tnn.2002.1021899.

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31

Aksshaya, B., G. Madhura L. V., Nivethashri S, Vishnuvarthini T, and Mohankumar N. "Design And Analysis of Analog TRNG Using Sample and Hold Circuit." International Journal of Engineering & Technology 7, no. 3.8 (2018): 69. http://dx.doi.org/10.14419/ijet.v7i3.8.15222.

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Implementation of analog True random number generators is inevitable in almost all the security applications and encryption protocols nowadays. Although many digital True Random Number Generators are available, we proposed a method of random number generation using analog module of mixed signals. In actual fact generation of True Random Numbers is by utilizing the sample and hold circuit which is controlled by another random clock source, and a post processing circuit for generation of unpredictable binary sequence of numbers. The primary input source is an analog signal, essentially highly random noise from the external environment. The high unpredictability, less resource and simple circuit design are some highlights of the proposed work. Finally, the randomness is evaluated using NIST test suites and results are plotted and analyzed.

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32

Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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Iwashita, A., and M. Shimojo. "A Development of Mixed Signal LSI for Tactile Data Processing : Verification and Improvement of the Analog Circuit." Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) 2004 (2004): 54. http://dx.doi.org/10.1299/jsmermd.2004.54_2.

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Constandinou, T. G., J. Georgiou, and C. Toumazou. "Nano-power mixed-signal tunable edge-detection circuit for pixel-level processing in next generation vision systems." Electronics Letters 39, no. 25 (2003): 1774. http://dx.doi.org/10.1049/el:20031185.

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35

Song, Ling-Yen, Yu-Kang Lou, Ching-Ho Lin, et al. "Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation." Electronics 10, no. 9 (2021): 1088. http://dx.doi.org/10.3390/electronics10091088.

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For mixed-signal systems, identifying the analog and digital circuit blocks in the transistor-level netlist has many benefits for system analysis and verification. However, existing approaches still have difficulty handling large mixed-signal designs with millions of transistors, especially when multiple analog structure patterns are included. In this paper, we propose an efficient structure recognition methodology to support analyzing highly complex designs with various circuit structures and different devices. In order to tackle the complexity of real cases, a hierarchical partition-based analysis methodology and an encoding-based fast screening technique are proposed in this work. To correctly ascertain the boundary of analog and digital structures, we propose an enhanced direct current connection (DCC) partition method and combine it with the analog structure analysis flow. The non-transistor devices, such as resistors and capacitors, are also included in our recognition flow to improve the recognition capability and accuracy. As demonstrated with two industrial cases, the behavioral models generated from the structure recognition results do help to improve the efficiency of the AMS system verification.

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KUWAZAKI, Tatsuya, Jun SHIRATAKI, and Makiko OKUMURA. "The Mixed Time-Frequency Steady-State Analysis Method for Nonlinear Circuits Driven by Multitone Signals." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 10 (2009): 2540–45. http://dx.doi.org/10.1587/transfun.e92.a.2540.

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37

Banchuin, Rawid. "Novel Complete Probabilistic Models of Random Variation in High Frequency Performance of Nanoscale MOSFET." Journal of Electrical and Computer Engineering 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/189436.

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The novel probabilistic models of the random variations in nanoscale MOSFET's high frequency performance defined in terms of gate capacitance and transition frequency have been proposed. As the transition frequency variation has also been considered, the proposed models are considered as complete unlike the previous one which take only the gate capacitance variation into account. The proposed models have been found to be both analytic and physical level oriented as they are the precise mathematical expressions in terms of physical parameters. Since the up-to-date model of variation in MOSFET's characteristic induced by physical level fluctuation has been used, part of the proposed models for gate capacitance is more accurate and physical level oriented than its predecessor. The proposed models have been verified based on the 65 nm CMOS technology by using the Monte-Carlo SPICE simulations of benchmark circuits and Kolmogorov-Smirnov tests as highly accurate since they fit the Monte-Carlo-based analysis results with 99% confidence. Hence, these novel models have been found to be versatile for the statistical/variability aware analysis/design of nanoscale MOSFET-based analog/mixed signal circuits and systems.

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38

MINGESZ, ROBERT, ANGELA BARNA, ZOLTAN GINGL, and JANOS MELLAR. "ENHANCED CONTROL OF EXCIMER LASER PULSE TIMING USING TUNABLE ADDITIVE NOISE." Fluctuation and Noise Letters 11, no. 01 (2012): 1240007. http://dx.doi.org/10.1142/s021947751240007x.

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Recently we have shown a system developed to precisely control the laser pulse timing of excimer lasers [R. Mingesz, Z. Gingl, G. Almasi, A. Csengeri and P. Makra, Utilising jitter noise in the precise synchronisation of laser pulses, Fluct. Noise Lett. 8 (2008) L41–L49]. The electronic circuit based on an embedded microcontroller and utilized the natural jitter noise of the laser pulse generation to improve the long term regulation of the delay of the laser related to an external trigger pulse. Based on our results we have developed an improved system that uses additional, programmable time delay units to tune the noise source to further enhance performance and allows reduction of complexity in the same time. A mixed-signal microcontroller generates a randomly dithered delay of the pulse generation moment to enhance the resolution and also runs a dedicated algorithm to optimize regulation. The compact, flexible hardware supports further enhancements; the signal processing algorithm can be replaced even by in-system reprogramming. Optimized processing and the relaxed hardware requirements may also support low-power operation, wireless communication, therefore the application possibilities may be extended to many other disciplines.

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Marković, Ivo, Milka Potrebić, and Dejan Tošić. "Memristors as Candidates for Replacing Digital Potentiometers in Electric Circuits." Electronics 10, no. 2 (2021): 181. http://dx.doi.org/10.3390/electronics10020181.

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Digital potentiometers are substantial components for the design of many mixed-signal electronic circuits and systems. Their capability to program resistance value almost instantly provides hardware designers an additional level of freedom. Unfortunately, this feature is limited to DC and lower frequencies, due to parasitic effects. Nowadays, memristors as continuously tunable resistors are becoming candidates for potentiometer successors. Memristors are two-terminal non-volatile devices which have less significant parasitic effects and a wide resistance range. The memristance value can be changed on the fly. Using nanotechnology, memristor implementation has a nanoscale footprint with nanosecond transition between resistive states. In this paper, we present a comparison between the frequency characteristics of digital potentiometers and the only commercially available memristors. Memristor parasitic effects dominate at higher frequencies which extends the bandwidth. In order to present the advantages of memristive circuits, we have analyzed and implemented tunable circuits such as a voltage divider, an inverting amplifier, a high-pass filter, and a phase shifter. A commercially available memristor by KnowM Inc. is used for this purpose. Experimental results obtained by the measurements verify that a memristor has equal or better characteristics than a digital potentiometer. Memristive realizations of voltage dividers and inverting amplifiers have a wider bandwidth, while filters and phase shifters with a memristor have almost identical frequency characteristics as the corresponding realizations with a digital potentiometer.

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Tian, Tian, Peng Li, Huiqun Huang, Yilin Pu, and Bin Wu. "A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver." Electronics 10, no. 15 (2021): 1869. http://dx.doi.org/10.3390/electronics10151869.

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The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

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Schmitz, Oliver, Sven Karsten Hampel, Christian Orlob, Marc Tiebout, and Ilona Rolfes. "Body effect up- and down-conversion mixer circuits for low-voltage ultra-wideband operation." Analog Integrated Circuits and Signal Processing 64, no. 3 (2009): 233–40. http://dx.doi.org/10.1007/s10470-009-9426-3.

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Kerns, Kevin J., Ivan L. Wemple, and Andrew T. Yang. "Efficient parasitic substrate modeling for monolithic mixed-A/D circuit design and verification." Analog Integrated Circuits and Signal Processing 10, no. 1-2 (1996): 7–21. http://dx.doi.org/10.1007/bf00713976.

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Soulier, Fabien, Achraf Lamlih, Vincent Kerzérho, Serge Bernard, and Tristan Rouyer. "Very Low Resource Digital Implementation of Bioimpedance Analysis." Sensors 19, no. 15 (2019): 3381. http://dx.doi.org/10.3390/s19153381.

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Bioimpedance spectroscopy consists of measuring the complex impedance of biological tissues over a large frequency domain. This method is particularly convenient for physiological studies or health monitoring systems. For a wide range of applications, devices need to be portable, wearable or even implantable. Next generation of bioimpedance sensing systems thus require to be implemented with power and resource savings in mind. Impedance measurement methods are divided into two main categories. Some are based on “single-tone” signals while the others use “multi-tone” signals. The firsts benefit from a very simple analysis that may consist of synchronous demodulation. However, due to necessary frequency sweep, the total measurement may take a long time. On the other hand, generating a multi-frequency signal allows the seconds to cover the whole frequency range simultaneously. This is at the cost of a more complex analysis algorithm. This makes both approaches hardly suitable for embedded applications. In this paper, we propose an intermediate approach that combines the speed of multi-tone systems with a low-resource analysis algorithm. This results in a minimal implementation using only adders and synchronous adc. For optimal performances, this small footprint digital processing can be synthesized and embedded on a mixed-mode integrated circuit together with the analog front-end. Moreover, the proposed implementation is easily scalable to fit an arbitrary frequency range. We also show that the resulting impact on noise sensitivity can be mitigated.

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Barkalov, Alexander, Larysa Titarenko, and Kazimierz Krzywicki. "Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review." Electronics 10, no. 10 (2021): 1174. http://dx.doi.org/10.3390/electronics10101174.

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The review is devoted to methods of structural decomposition that are used for optimizing characteristics of circuits of finite state machines (FSMs). These methods are connected with the increasing the number of logic levels in resulting FSM circuits. They can be viewed as an alternative to methods of functional decompositions. The roots of these methods are analysed. It is shown that the first methods of structural decomposition have appeared in 1950s together with microprogram control units. The basic methods of structural decomposition are analysed. They are such methods as the replacement of FSM inputs, encoding collections of FSM outputs, and encoding of terms. It is shown that these methods can be used for any element basis. Additionally, the joint application of different methods is shown. The analysis of change in these methods related to the evolution of the logic elements is performed. The application of these methods for optimizing FPGA- based FSMs is shown. Such new methods as twofold state assignment and mixed encoding of outputs are analysed. Some methods are illustrated with examples of FSM synthesis. Additionally, some experimental results are represented. These results prove that the methods of structural decomposition really improve the characteristics of FSM circuits.

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Kumar, Raj, and Ram Awadh Mishra. "Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 62. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp62-70.

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Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2<sup>n </sup>- 1, 2<sup>n</sup>, 2<sup>n</sup> + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

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Morais, Flávio, Pedro Carvalhaes-Dias, Yu Zhang, et al. "Low-Cost Control and Measurement Circuit for the Implementation of Single Element Heat Dissipation Soil Water Matric Potential Sensor Based on a SnSe2 Thermosensitive Resistor." Sensors 21, no. 4 (2021): 1490. http://dx.doi.org/10.3390/s21041490.

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A low-cost signal processing circuit developed to measure and drive a heat dissipation soil matric potential sensor based on a single thermosensitive resistor is demonstrated. The SnSe2 has a high thermal coefficient, from −2.4Ω/°C in the 20 to 25 °C to −1.07Ω/°C in the 20 to 25 °C. The SnSe2 thermosensitive resistor is encapsulated with a porous gypsum block and is used as both the heating and temperature sensing element. To control the power dissipated on the thermosensitive resistor and keep it constant during the heat pulse, a mixed analogue/digital circuit is used. The developed control circuit is able to maintain the dissipated power at 327.98±0.3% mW when the resistor changes from 94.96Ω to 86.23Ω. When the gravimetric water content of the porous block changes from dry to saturated (θw=36.7%), we measured a variation of 4.77Ω in the thermosensitive resistor, which results in an end-point sensitivity of 130 mΩ/%. The developed system can easily meet the standard requirement of measuring the gravimetric soil water content with a resolution of approximately Δθw=1%, since the resistance is measured with a resolution of approximately μ31μΩ, three orders of magnitude smaller than the sensitivity.

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PETRÁS, ISTVÁN, CSABA REKECZKY, TAMÁS ROSKA, RICARDO CARMONA, FRANCISCO JIMÉNEZ-GARRIDO, and ANGEL RODRÍGUEZ-VÁZQUEZ. "EXPLORATION OF SPATIAL-TEMPORAL DYNAMIC PHENOMENA IN A 32×32-CELL STORED PROGRAM TWO-LAYER CNN UNIVERSAL MACHINE CHIP PROTOTYPE." Journal of Circuits, Systems and Computers 12, no. 06 (2003): 691–710. http://dx.doi.org/10.1142/s0218126603001112.

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This paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and distributed image memory on a common silicon substrate. The chip was designed and fabricated in a standard 0.5 μm CMOS technology and contains approximately 500 000 transistors. It consists of 1024 processing units arranged into a 32×32 grid. Each processing element contains two coupled CNN cores, thus, constituting two parallel layers of 32×32 nodes. The functional features of the chip are in accordance with the 2nd Order Complex Cell CNN-UM architecture. It is composed of two CNN layers with programmable inter- and intra-layer connections between cells. Other features are: cellular, spatial-invariant array architecture; randomly selectable memory of instructions; random storage and retrieval of intermediate images. The chip is capable of completing algorithmic image processing tasks controlled by the user-selected stored instructions. The internal analog circuitry is designed to operate with 7-bits equivalent accuracy. The physical implementation of a CNN containing second order cells allows real-time experiments of complex dynamics and active wave phenomena. Such well-known phenomena from the reaction–diffusion equations are traveling waves, autowaves, and spiral-waves. All of these active waves are demonstrated on-chip. Moreover this chip was specifically designed to be suitable for the computation of biologically inspired retina models. These computational experiments have been carried out in a developmental environment designed for testing and programming the analogic (analog-and-logic) programmable array processors.

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Chen-Yang Pan and Kwang-Ting Cheng. "Pseudorandom testing for mixed-signal circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 10 (1997): 1173–85. http://dx.doi.org/10.1109/43.662678.

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Berroth, M., V. Hurm, M. Lang, et al. "Hemt circuits for signal/data processing." Solid-State Electronics 41, no. 10 (1997): 1407–12. http://dx.doi.org/10.1016/s0038-1101(97)00083-x.

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Ralston, R. "Signal processing: Opportunities for superconductive circuits." IEEE Transactions on Magnetics 21, no. 2 (1985): 181–85. http://dx.doi.org/10.1109/tmag.1985.1063646.

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