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Dissertations / Theses on the topic 'Mixed-signal system'

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Published: 4 June 2021

Last updated: 1 February 2022

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1

Hajjar, Ara. "An integrable mixed-signal test system /." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21298.

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The growing need for integrable test solutions has prompted the creation of various test bus standards. A mixed-signal test core is an ideal complement to these standards. This work presents the design and implementation of an integrable test system. The design consists of two major components: a stimulus generator, and a waveform extractor.
A memory-based generator is used to construct the stimulus generation component. Such a circuit repeats a finite portion of an infinite-length PDM sequence in order to produce any arbitrary analog waveform. The circuitry is simple to design---it is comprised of a scan chain, and a 1-bit DAC; it is also area-efficient and robust (mostly digital design). Furthermore, since the analog signal is generated from a digital bit-stream, it is both stable and repeatable.
The extraction component of the test system focuses on the capture of steady-state type responses. A novel A/D algorithm is presented: the Multi-Pass technique. By taking advantage of repetitive waveforms, the Multi-Pass convertor achieves both area-efficiency and high-speed performance. A single on-chip comparator and sample-and-hold circuit is sufficient to extract analog waveforms. In addition, a novel, area-efficient, integrable, and highly-linear voltage reference design is presented.
Experimental results from two prototype boards serve to validate the proposed test system design. The first board implements the system using discrete components; the second makes use of a custom IC fabricated in a 0.5 mum CMOS process. The work presented in this thesis provides the groundwork for obtaining a practical and fully integrable mixed signal test system.

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2

Hajjar, Ara. "An integrable mixed-signal test system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0027/MQ50616.pdf.

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3

Xiao, Rui. "Dynamically reconfigurable mixed signal system design /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1407501391&sid=17&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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4

Hannu, J. (Jari). "Embedded mixed-signal testing on board and system level." Doctoral thesis, Oulun yliopisto, 2013. http://urn.fi/urn:isbn:9789526200996.

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Abstract This thesis studies the methods to test mixed-signal devices and circuits on board and system level with embedded test instrumentation. The study is divided in three continuous sections, development of embedded test methods for discrete components, integration of test instruments on board level and development of test and health monitoring strategy for large scale system. The developed embedded test methods for mixed signal circuitry on board level are based on the standard for mixed signal test bus IEEE 1149.4. The standardized embedded test infrastructure is utilized for testing discrete components with emphasis on testing active components as diodes and transistors. The developed embedded tests are evaluated with PCOLA/SOQ method for manufacturing testing and also the usability of the tests is discussed. A solution for embedded mixed-signal test controller is presented with discussion of test communication and the possibilities of implementing embedded test control. The target in the development of the test control is to enable launch mixed signal tests on device remotely. The test controller is IEEE 1149.4 compatible and can generate and measure analog test signals while controlling boundary-scan enabled devices. The final section of the thesis focuses on an embedded test solution for aerospace bus system (MIL-STD-1553). Current solutions are based on testing the bus system during maintenance on ground. The developed test and monitoring method allows on-line monitoring of the bus to detect and locate possible defects which only occur during use of the aeroplane
Tiivistelmä Väitöstyössä tutkittiin sekasignaalilaitteiden ja -piirien testausmenetelmiä levy- ja järjestelmätasolla hyödyntäen sulautettuja testilaitteita. Työ jakaantuu kolmeen osaan; sulautettujen testausmenetelmien kehitys diskreeteille komponenteille, testi-instrumenttien integrointi piirilevytasolle sekä testaus- ja kunnonmonitorointimenetelmän kehitys laajemmalle järjestelmälle. Sulautettujen testimenetelmien kehitys sekasignaalipiireille piirilevytasolla perustuu sekasignaalitestiväylän standardiin IEEE 1149.4. Standardoitua sulautettua testi-infrastruktuuria käytettiin diskreettien komponenttien testaukseen painottuen aktiivikomponentteihin, kuten diodeihin ja transistoreihin. Kehitetyt sulautetut testit on arvioitu PCOLA/SOQ menetelmällä, jota hyödynnetään tuotantotestauksen testikattavuuden arvioinnissa. Lisäksi testimenetelmien käytettävyyttä arvioitiin. Sulautettu sekasignaalilaitteiden testikontrollerin tavoite on käynnistää ja suorittaa sekasignaalitestejä laitteessa etäältä. Kehitetty testikontrolleri on IEEE 1149.4 yhteensopiva ja voi generoida ja mitata analogista testisignaalia sekä samanaikaisesti ohjata testiväylää. Lisäksi etätestauksen mahdollistavasta testikommunikaatiomenetelmiä arvioitiin kuten myös erilaisia toteutustasoja sulautetuille testimenetelmille. Laajemman järjestelmän kehityksessä tutkittiin sulautettua testausratkaisua lentokoneen väyläjärjestelmälle, joka perustuu standardiin MIL-STD-1553B. Nykyiset menetelmät perustuvat väyläjärjestelmän testaukseen huollon yhteydessä, mutta osa virheistä ilmenee vain käytön aikana. Kehitetty testaus- ja monitorointimenetelmä mahdollistaa käytönaikaisen jatkuvan virheiden monitoroinnin sekä niiden paikantamisen lennon aikana

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5

Al-Junaid, Hessa Jassim. "SystemC-A : analogue and mixed-signal language for high level system design." Thesis, University of Southampton, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.427468.

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6

YELAMANCHILI, VEENA RAO. "A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449.

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7

Omeni, Okundu Chukwuemeke. "Advanced mixed signal strategies for micropower CMOS system on chip." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.420136.

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8

Zaum, Daniel [Verfasser]. "System Level Analysis of Mixed-Signal Systems using State Space Models / Daniel Zaum." München : Verlag Dr. Hut, 2011. http://d-nb.info/1017353360/34.

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9

Zakizadeh, Jila. "Built-in self-test techniques for analog and mixed signal circuits." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/27094.

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The present thesis attempts to develop new techniques for testing analog parts of embedded cores-based mixed signal integrated circuits and systems. In particular, the oscillation based test methodologies have been investigated in the thesis. In the oscillation based test methods, the circuit under test (CUT) is first converted to an oscillator in the test mode and the oscillation parameters, viz. frequency, amplitude, etc. are then measured. Any deviation of these parameters causes either the oscillation frequency of the converted CUT to differ from its nominal value, or the converted CUT stops oscillation altogether. For evaluation purpose, a program has been written in C to help us in simulating our test methodologies. The program is used to inject faults to the circuit under test. The detailed experimental results provided give frequency and amplitude measurements data performed on the individual circuit blocks together with fault coverage. In this work, however, only catastrophic faults were considered. The simulation experiments carried out on different circuits not only demonstrate that the developed approaches are quite feasible but show in addition that the fault coverage is quite satisfactory (100%) in all cases.

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Suparjo, Bambang Sunaryo. "Testing analogue circuits : design for testability structures and an investigation into supply current modelling." Thesis, University of Southampton, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239871.

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11

Newbould, Rexford D. "Garnet: A graph-based octilinear mixed-signal Steiner tree routing system." Diss., The University of Arizona, 2004. http://hdl.handle.net/10150/298732.

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A compatibility graph-based, general area router for integrated circuit (IC) designs is presented. The highly flexible constraint system allows a number of modern and mixed-signal routing requirements to be handled, even for a large number of nets. The IC router can efficiently construct near-minimal Steiner trees for multi-terminal nets in both classical rectilinear, or Manhattan, geometry as well as octilinear geometries. These Steiner trees can be constructed around blockages, and in the presence of obstacles such as other nets. A method for routing trees through weighted areas is also introduced. The routing system can predict congested routing areas before routing is performed, and appropriately weight congested areas in order to reduce net congestion. Finally, a fast crosstalk violation checker can run alongside the routing engine. Each portion of the router is bounded by O(n log(n)) runtime, or less, making the entire routing process bounded by the same runtime. The system thus scales well to handle a very large number of exact routes in a fully mixed-signal aware engine, in either rectilinear or newly-introduced octilinear geometries.

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12

Babb, Charles F. "Mixed signal processor for a robust symmetrical number system direction finding antenna." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2002. http://library.nps.navy.mil/uhtbin/hyperion-image/02sep%5FBabb.pdf.

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Thesis (M.S. in Systems Engineering)--Naval Postgraduate School, September 2002.
Thesis advisor(s): Phillip E. Pace, David C. Jenn. Includes bibliographical references (p. 97). Also available online.

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13

Li, Wei. "On the study of mixed signal interface circuit for inertial navigation system." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691765.

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14

Fisher, John Sheridan. "Application of model driven architecture design methodologies to mixed-signal system design projects." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1143218375.

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15

Mauderer, Andreas [Verfasser]. "Optimierung des modellbasierten Entwurfs durch automatisierte Übergänge zwischen System- und Mixed-Signal-Entwurfsumgebung / Andreas Mauderer." München : Verlag Dr. Hut, 2014. http://d-nb.info/1050331680/34.

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16

Van, Blerkom Daniel A. "Mixed-signal CMOS circuits for digital free-space optical interconnects : design, optimization and system integration /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9975035.

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17

Zheng, Geng. "Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams." Thesis, University of North Texas, 2013. https://digital.library.unt.edu/ark:/67531/metadc271923/.

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This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution.

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18

Iorga, Cosmin. "Measurement, suppression, and prediction of digital switching noise coupling in mixed-signal system-on-chip applications /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Govind, Vinu. "Design of Baluns and Low Noise Amplifiers in Integrated Mixed-Signal Organic Substrates." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7208.

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The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems. A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed. The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.

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20

Choi, Jinwoo. "Noise Suppression and Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/10417.

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With the evolution of technologies, mixed-signal system integration is becoming necessary for combining heterogeneous functions such as high-speed processors, radio frequency (RF) circuits, memory, microelectromechanical systems (MEMS), sensors, and optoelectronic devices. This kind of integration is required for convergent microsystems that support communication and computing capabilities in a tightly integrated module. A major bottleneck with such heterogeneous integration is the noise coupling between the dissimilar blocks constituting the system. The noise generated by the high-speed digital circuits can couple through the power distribution network (PDN) and this noise can transfer to sensitive RF circuits, completely destroying the functionality of noise-sensitive RF circuits. One common method used for mixed-signal integration in the package is splitting the power and/or ground planes. The gap in the power and ground planes can partially block the propagation of electromagnetic waves. However, electromagnetic energy can still couple through the split, especially at frequencies greater than 1 GHz. The AI-EBG structure in this dissertation has been developed to suppress unwanted noise coupling in mixed-signal systems and this AI- EBG structure shows excellent isolation (-80 dB ~ -140 dB), which results in a noise coupling-free environment in mixed-signal systems. The AI-EBG structure would be part of the power distribution network (PDN) in systems and is expected to have a significant impact on noise suppression and isolation in mixed-signal systems in future.

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21

Rosen, Julius von [Verfasser], Lars [Akademischer Betreuer] Hedrich, and Uwe [Akademischer Betreuer] Brinkschulte. "A highly dependable, analog multi-core mixed-signal task distribution system / Julius von Rosen. Gutachter: Lars Hedrich ; Uwe Brinkschulte." Frankfurt am Main : Univ.-Bibliothek Frankfurt am Main, 2015. http://d-nb.info/1079361987/34.

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22

Zheng, Qinghua (Cindy). "A DSP feedback system on a mixed signal tester and its application in ADC test by Quinghua (Cindy) Zheng." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38114.

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23

Adams, René [Verfasser]. "Systemkonzeption und Entwicklung eines Mixed-Signal Front-End-Chips für ein maritimes S-Band Phased Array Radar System / René Adams." München : Verlag Dr. Hut, 2017. http://d-nb.info/1149579358/34.

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24

Fabris, Eric Ericson. "A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6226.

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O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutura de programação em circuitos reconfiguráveis analógicos. A emprego da programação no domínio digital abre espaço para usos da vasta gama de ferramentas disponíveis para o projeto em alto nível de abstração, simulação e síntese automática para implementar a aplicação alvo com excelente predição do desempenho final. A abordagem proposta baseia-se no conceito de translação em freqüência (mixagem) do sinal de entrada seguida pela sua conversão para o domínio ΣΔ. A estrutura de processamento possibilita o emprego de um bloco analógico constante, e também, um processamento uniforme de sinais de entrada indo de DC até altas freqüências. A aplicação é configurada no domínio ΣΔ onde a performance pode ser predita de acordo com as especificações alvo. Objetivando a exploração do espaço de projeto foi desenvolvido o modelo de performance teórico e de simulação. Os modelos desenvolvidos auxiliam no também no projeto físico da interface proposta. Objetivando, tanto a validação dos modelos propostos, bem como o desenvolvimento de aplicações, foram construídos dois protótipos. São apresentados os usos da interface como um ADC paramétrico multi-banda e como um multiplicador e um somador de sinais analógicos. É proposta também uma arquitetura para uma interface analógica multi-canal. Os resultados experimentais empregados para a caracterização da interface proposta suportam as vantagens da mesma.
The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

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England, Troy Daniel. "SiGe BiCMOS circuit and system design and characterization for extreme environment applications." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41216.

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This thesis describes the architecture, verification, qualification, and packaging of a 16-channel silicon-germanium (SiGe) Remote Electronics Unit (REU) designed for use in extreme environment applications encountered on NASA's exploration roadmap. The SiGe REU was targeted for operation outside the protective electronic "vaults" in a lunar environment that exhibits cyclic temperature swings from -180ºC to 120ºC, a total ionizing dose (TID) radiation level of 100 krad, and heavy ion exposure (single event effects) over the mission lifetime. The REU leverages SiGe BiCMOS technological advantages and design methodologies, enabling exceptional extreme environment robustness. It utilizes a mixed-signal Remote Sensor Interface (RSI) ASIC and an HDL-based Remote Digital Control (RDC) architecture to read data from up to 16 sensors using three different analog channel types with customizable gain, current stimulus, calibration, and sample rate with 12-bit analog-to-digital conversion. The SiGe REU exhibits excellent channel sensitivity throughout the temperature range, hardness to at least 100 krad TID exposure, and single event latchup immunity, representing the cutting edge in cold-capable electronic systems. The SiGe REU is the first example within a potential paradigm shift in space-based electronics.

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Hirmer, Katrin [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Dirk [Akademischer Betreuer] Killat. "Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips / Katrin Hirmer ; Klaus Hofmann, Dirk Killat." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2019. http://d-nb.info/1199006408/34.

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Hirmer, Katrin [Verfasser], Klaus Akademischer Betreuer] Hofmann, and Dirk [Akademischer Betreuer] [Killat. "Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips / Katrin Hirmer ; Klaus Hofmann, Dirk Killat." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2019. http://d-nb.info/1199006408/34.

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Schlottmann, Craig Richard. "A coordinated approach to reconfigurable analog signal processing." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/49021.

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The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA, which was designed explicitly for interfacing with external digital systems. This compatibility creates a streamlined workflow for dropping the FPAA hardware into mixed-signal embedded systems. The second phase, algorithm analysis and modeling, is important to create a useful and reliable library of components for the system designer. We discuss the concept and procedure of analog abstraction that empowers non-circuit design engineers to take full advantage of analog techniques. We use the analog vector-matrix multiplier as an example for a detailed discussion on computational analog analysis and system mapping to the FPAA. Lastly, we describe high-level software tools, which are an absolute necessity for the design of large systems due to the size and complexity of modern FPAAs. We describe the Sim2Spice tool, which allows system designers to develop signal processing systems in the Simulink environment. The tool then compiles the system to the FPAA hardware. By coordinating the development of these three phases, we've created a solid unified framework that empowers engineers to utilize FPAAs.

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Le, hir Juliette. "Conception mixte d’un capteur d’images intelligent intégré à traitements locaux massivement parallèles." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLC107/document.

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Les capteurs intelligents permettentaux systèmes embarqués d’analyser leurenvironnement sans transmission de donnéesbrutes, consommatrice d’énergie. Ce mémoireprésente donc un travail sur un imageur intégrantdu traitement d’image. Deux figures de méritesont introduites pour classer l’état de l’art desimageurs intelligents en fonction de leurversatilité et de leur préservation de la surfacephotosensible. Cela met en évidence uncompromis que ce travail essaie d’améliorer enexplorant une approche par macropixels. Eneffet, en regroupant les éléments de calculs (PEs)pour plusieurs pixels, les traitements sont à lafois massivement parallèles et potentiellementplus versatiles à surface photosensible donnée.Une adaptation du filtrage spatial et du filtragetemporel en adéquation avec une architecture parmacropixels est proposée (sous-échantillonnagepar 3x3 pixels et par 2x2 pixels respectivement),et validée fonctionnellement. Une architectured’imageur en macropixels asymétriques est doncprésentée. Le PE conçu est un circuit analogiqueà capacités commutées, programmable par uncontrôle numérique extérieur à la matrice. Sondimensionnement est discuté pour descompromis entre surface et précision des calculs,avant d’être implémenté en calcul approximépour notre cas. La matrice proposée a été simuléeen vue extraite et présente des images de résultatsde détection de contours ou de différencetemporelle corrects, avec un facteur deremplissage de 28%
Smart sensors allow embeddedsystems for analysing their environment withoutany transmission of raw data, which consumes alot of power. This thesis presents an imagesensor integrating image processing tasks. Twofigures of merit are introduced in order toclassify the state of the art of smart imagersregarding their versatility and their preservationof photosensitive area. This shows a trade-offthat this work aims at improving by using amacropixel approach. By merging processingelements (PEs) between several pixels,processing tasks are both massively parallel andpotentially more versatile at givenphotosensitive area. An adaptation of spatial andtemporal filtering, matching such anarchitecture is proposed (downsampling by3x3 and 2x2 pixels respectively for eachprocessing task) and functionnally validated. Anarchitecture of asymmetric macropixels is thuspresented. The designed PE is an analogswitched capacitor circuit that is controlled byout-of-matrix digital electronics. The sizing ofthe PE is discussed over the trade-off betweenaccuracy and area, and implemented in anapproximate computing approach in our study.The proposed matrix of pixels and PEs issimulated in post-layout extracted views andshows good results on computed images of edgedetection or temporal difference, with a 28% fillfactor

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Pai, Hung-Chuan. "Analytical methods for mixed signal processing systems /." The Ohio State University, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487949508368344.

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Kuhl, Matthias [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Full-custom analog-mixed signal components for CMOS integrated autonomous microelectronic systems = Anwendungsbezogene analog-mixed Signal Komponenten für CMOS-integrierte autonome mikroelektronische Systeme." Freiburg : Universität, 2014. http://d-nb.info/1123479879/34.

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Ravi, Sanjay. "Inter-pulse interval based mixed signal representations/." Full text open access at:, 2008. http://content.ohsu.edu/u?/etd,656.

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33

Ozev, Sule. "High level test approaches for mixed-signal systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2002. http://wwwlib.umi.com/cr/ucsd/fullcit?p3070993.

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34

Stehlík, Jiří. "Obvody s proudovou zpětnou vazbou pro zpracování analogových signálů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233459.

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This dissertation thesis deals with design of new functional blocks usable in area of analogue signal processing, focusing on sensor signal processing. Versatility of these circuits will find applications in programmable analogue array structures that will be possible to control and configure via a digital signal. Hereby build-up array would be fully a reconfigurable digital control system for sensor signal processing and usable for a wide range of different sensors. It offers possibility to build-up a control code for each specific sensor system, with which it would be possible to achieve optimal results of the entire system and consequently place the system on a chip. The presented programmable array is designed from configurable analogue blocks. The current feedback circuits, which in a suitable configuration can operate in voltage or current mode, are used here. This allows to achieve very good results in the systems with very low power supply, which is closely associated with mobility and autonomous behavioral (that are very important and observed parameters today) of the entire sensor-based framework. The work deals in detail with particular blocks, which are described theoretically and evaluated for using in the programmable analogue array. Design of the structure of programmable analogue array as well the use of these circuits in the part of whole system (that will be realized on a chip) are presented at the end of this thesis.

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35

Zheng, Li-Rong. "Design, analysis and integration of mixed-signal systems for signal and power industry /." Stockholm, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3233.

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36

Roh, Jeongjin. "Mixed-signal signature analysis for systems-on-a-chip." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035971.

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37

GANESAN, SREELAKSHMI. "SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.

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38

Mert, Yakup Murat. "Systemc Implementation With Analog Mixed Signal Modeling For A Microcontroller." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/2/12608360/index.pdf.

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In this thesis, an 8-bit microcontroller, PIC 16F871, has been implemented using SystemC with classical hardware design methods. Analog modules of the microcontroller have been modeled behaviorally with SystemC-AMS which is the analog and mixed signal extensions for the SystemC. SystemC-AMS provides the capability to model non-digital modules and synchronization with the SystemC kernel. In this manner, electronic systems that have both digital and analog components can be described and simulated very effectively. The PIC 16F871 is a well known and very common microcontroller. Its architecture, peripheral modules and analog components makes this microcontroller pretty good model for a System on Chip (SoC) concept. Designed microcontroller&rsquo
s peripheral modules, instruction set and addressing modes have been verified utilizing the test codes. Besides, designed microcontroller has been tested with 16-bit CRC code. Moreover, a synchronous demodulator system that involves designed microcontroller and additional analog units has been constructed and simulated. Finally, SystemC to hardware flow has been demonstrated with implementation of arithmetic logic unit of the 16F871 into FPGA based hardware.

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39

Adil, Farhan. "Applications of floating-gate based programmable mixed-signal reconfigurable systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54272.

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A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this research is the implementation and application of mixed-signal reconfigurable systems utilizing floating-gate transistors and field programmable analog/digital arrays. Basic analog circuits using floating-gate CMOS devices have been developed for this research. Floating-gate based analog circuits reduce the effects of inherent property mismatch present in analog circuits. Various circuit blocks including current mirrors, gilbert multipliers, and $G_m-C$ filters were designed and experimentally demonstrated to show reduced mismatch effects. Such floating-gate transistors and circuits are the basis for the reconfigurable systems developed in this research. To enable high-performance reconfigurable systems, sub-micron and sub-$100 nm$ CMOS process nodes were used in this research. Scaling of Floating-gate devices is a key issue at small nodes. Test structures were created to verify the programming capability for floating-gate devices at various process nodes. Experimental results show scalability of floating-gate devices along with effective charge programming ability. A floating-gate based reconfigurable mixed-signal platform using Field-Programmable Array of Analog-Digital Devices (FPAADD) has been created and experimentally verified. Further FPAADD systems augmented with a CPU based digital back-end were developed to enable greater applications for such reconfigurable systems. Experimental functionality and circuits/systems created using FPAADD based systems were demonstrated for this research work.

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40

Wunderlich, Richard Bryan. "Floating-gate-programmable and reconfigurable, digital and mixed-signal systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51815.

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This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.

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41

Evans, Peter Sidney Albert. "Transient response testing of linear components within mixed-signal systems." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239743.

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42

Sengupta, Arindam. "Multidimensional Signal Processing Using Mixed-Microwave-Digital Circuits and Systems." University of Akron / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=akron1407977367.

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43

Shen, Meigen. "Concurrent chip and package design for radio and mixed-signal systems." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-476.

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44

DURBHA, SRIRAM. "A METHODOLOGY FOR ANALYZING HARDWARE ACCELERATED CONTINUOUS-TIME METHODS FOR MIXED SIGNAL SIMULATION." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1091060658.

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45

Alhajj, Tarek. "TCSIM: a top-down approach to mixed-signal circuits and systems design." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19236.

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Design methodologies have evolved over the years, especially due to shrinking transistors in CMOS technology. This has encouraged the use of behavioural modelling in Matlab and Simulink over other less accurate or time consuming options for design and simulation, hence the development of TCSIM (Top-down Circuit Simulation In Matlab). The following components are modelled for this initial prototype: the output voltage limitation of operational amplifiers (opamps), the current limitation and parasitic capacitances of operational transconductance amplifiers (OTAs), the finite and nonlinear variation of on resistance in switches, and the nonideal behaviour of switched capacitor (SC) integrators. This is complemented by an analysis of the noise in these circuits. The models are verified with Cadence simulations and are shown to be both accurate and easy to map to the circuit level. It is also possible to optimize complete systems to efficiently meet specifications. The top-down methodology is demonstrated with the design of a delta-sigma analog-to-digital converter (ADC) to be both accurate and simple with TCSIM.
Les methodologies de conception ont evolue au fil des annees, notamment en raison de la diminution de la taille des transistors dans la technologie CMOS. Ceci a favorise l'utilisation de la modelisation comportementale a l'aide de Matlab et Simulink, en remplacement des anciennes techniques qui etaient moins precises et demandaient plus de temps, ce qui a mene au developpement de TCSIM (Topdown Circuit Simulation In Matlab). Dans le cadre de ce prototype initial, les composantes suivantes ont ete modelisees: la limitation du voltage de sortie des amplificateurs operationnels (opamps), la limitation du courant et de la capacitance parasitique des amplificateurs-transconductance operationnels (OTAs), les variations finies et non-lineaire de la resistance des interrupteurs et le comportement non-ideal des integrateurs a condensateur commute. A ces modelisations s'ajoute une analyse du bruit dans ces circuits. Les modeles ont ete valides a l'aide de simulations dans Cadence. Ces simulations demontrent la precision des modeles mais aussi la facilite avec laquelle ils peuvent etre transposes au niveau circuit. Les modeles permettent l'optimisation de systemes complets en vue d'atteindre les specifications. La methodologie "top-down" est illustree a l'aide du design d'un convertisseur analogue-a-digital (ADC) delta-sigma. Le travail demontre la facilite avec laquelle ce design peut etre effectue grace a TCSIM.

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46

Carr, Caitriona. "Automatic generation of VHDL-AMS from UML representations of mixed signal systems." Thesis, University of Ulster, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416791.

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47

Checka, Nisha 1980. "Substrate noise analysis and techniques for mitigation in mixed-signal RF systems." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34979.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 151-158).
Mixed-signal circuit design has historically been a challenge for several reasons. Parasitic interactions between analog and digital systems on a single die are one such challenge. Switching transients induced by digital circuits inject noise into the common substrate creating substrate noise. Analog circuits lack the large noise margins of digital circuits, thus making them susceptible to substrate voltage variations. This problem is exacerbated at higher frequencies as the effectiveness of standard isolation technique diminishes considerably. Historically, substrate noise was not a problem because each system was fabricated in its own package shielding it from such interactions. The work in this thesis spans all areas of substrate noise: generation, propagation, and reception. A set of guidelines in designing isolation structures was developed to assist designers in optimizing these structures for a particular application. Furthermore, the effect of substrate noise on two key components of the RF front end, the voltage controlled oscillator (VCO) and the low noise amplifier (LNA), was analyzed. Finally, a CAD tool (SNAT) was developed to efficiently simulate large digital designs to determine substrate noise performance.
(cont.) Existing techniques have prohibitively long simulation times and are only suitable for final verification. Determination of substrate noise coupling during the design phase would be extremely beneficial to circuit designers who can incorporate the effect of the noise and re-design accordingly before fabrication. This would reduce the turn around time for circuits and prevent costly redesign. SNAT can be used at any stage of the design cycle to accurately predict (less than 12% error when compared to measurements) the substrate noise performance of any digital circuit with a large degree of computational efficiency.
by Nisha Checka.
Ph.D.

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48

Taillefer, Chris. "Reducing measurement uncertainty in a DSP-based mixed-signal test environment." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84104.

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FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements.
A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test.
An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.

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49

Lundgren, Jan. "Behavioral Level Simulation Methods for Early Noise Coupling Quantification in Mixed-Signal Systems." Licentiate thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-3434.

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In this thesis, noise coupling simulation is introduced into the behavioral level. Methods and models for simulating on-chip noise coupling at a behavioral level in a design flow are presented and verified for accuracy and validity. Today, designs of electronic systems are becoming denser and more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. This raises problems when the electronics components start to interfere with each other. Often, digital components disturb analog components, introducing noise into the system causing degradation of the performance or even introducing errors into the functionality of the system. Today, these effects can only be simulated at a very late stage in the design process, causing large design iterations and increased costs if the designers are required to return and make alterations, which may have occurred at a very early stage in the process. This is why the focus of this work is centered on extracting noise coupling simulation models that can be used at a very early design stage such as the behavioral level and then follow the design through the various design stages. To realize this, SystemC is selected as a platform and implementation example for the behavioral level models. SystemC supports design refinement, which means that when designs are being refined and are crossing the design levels, the noise coupling models can also be refined to suit the current design. This new way of thinking in primarily mixed-signal designs is called Behavioral level Noise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costs of design iterations due to component cross-talk and simplifies the work for mixed-signal system designers.
Electronics Design Division

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50

Huang, Hu. "High-performance FPAA design for hierarchical implementation of analog and mixed-signal systems." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/6924.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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