Relevant bibliographies by topics / Mixed signal test

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Mixed signal test'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Mixed signal test"

1

Cron, A. "P1149.4 Mixed-Signal Test Bus." IEEE Design & Test of Computers 13, no. 3 (1996): 98. http://dx.doi.org/10.1109/mdt.1996.536100.

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Dufils, M., J. L. Carbonero, P. Planelle, and P. Raynaud. "Mixed-signal simulation and test generation." International Journal of Electronics 95, no. 3 (2008): 239–48. http://dx.doi.org/10.1080/00207210701827954.

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Kramer, Randy. "Test throughput for mixed-signal devices." IEEE Instrumentation & Measurement Magazine 8, no. 1 (2005): 12–15. http://dx.doi.org/10.1109/mim.2005.8465942.

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Modi, M. "Mixed-signal test bus, embedded core test efforts advance." IEEE Design & Test of Computers 16, no. 2 (1999): 5–93. http://dx.doi.org/10.1109/mdt.1999.765189.

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Baker, K., A. M. Richardson, and A. P. Dorey. "Mixed signal test — techniques, applications and demands." IEE Proceedings - Circuits, Devices and Systems 143, no. 6 (1996): 358. http://dx.doi.org/10.1049/ip-cds:19960904.

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Stratigopoulos, Haralampos-G., and Christian Streitwieser. "Adaptive Test With Test Escape Estimation for Mixed-Signal ICs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 10 (2018): 2125–38. http://dx.doi.org/10.1109/tcad.2017.2783302.

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Haurie, X., and G. W. Roberts. "Arbitrary-precision signal generation for mixed-signal built-in-self-test." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 11 (1998): 1425–32. http://dx.doi.org/10.1109/82.735354.

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Barragán, Manuel J., Diego Vázquez, and Adoración Rueda. "Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications." Journal of Electronic Testing 27, no. 3 (2011): 305–20. http://dx.doi.org/10.1007/s10836-010-5192-5.

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Ruan, Xiaoli, and Zheying Li. "Mixed-signal SoC test based on task flow." JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT 24, no. 11 (2010): 1024–30. http://dx.doi.org/10.3724/sp.j.1187.2010.01024.

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Kerkhoff, Hans G., and Bozena Kaminska. "Analog and mixed signal test techniques for SoCs." Microelectronics Journal 34, no. 10 (2003): 887–88. http://dx.doi.org/10.1016/s0026-2692(03)00234-9.

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Dissertations / Theses on the topic "Mixed signal test"

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Hajjar, Ara. "An integrable mixed-signal test system /." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21298.

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The growing need for integrable test solutions has prompted the creation of various test bus standards. A mixed-signal test core is an ideal complement to these standards. This work presents the design and implementation of an integrable test system. The design consists of two major components: a stimulus generator, and a waveform extractor.<br>A memory-based generator is used to construct the stimulus generation component. Such a circuit repeats a finite portion of an infinite-length PDM sequence in order to produce any arbitrary analog waveform. The circuitry is simple to design---it is comprised of a scan chain, and a 1-bit DAC; it is also area-efficient and robust (mostly digital design). Furthermore, since the analog signal is generated from a digital bit-stream, it is both stable and repeatable.<br>The extraction component of the test system focuses on the capture of steady-state type responses. A novel A/D algorithm is presented: the Multi-Pass technique. By taking advantage of repetitive waveforms, the Multi-Pass convertor achieves both area-efficiency and high-speed performance. A single on-chip comparator and sample-and-hold circuit is sufficient to extract analog waveforms. In addition, a novel, area-efficient, integrable, and highly-linear voltage reference design is presented.<br>Experimental results from two prototype boards serve to validate the proposed test system design. The first board implements the system using discrete components; the second makes use of a custom IC fabricated in a 0.5 mum CMOS process. The work presented in this thesis provides the groundwork for obtaining a practical and fully integrable mixed signal test system.
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Hajjar, Ara. "An integrable mixed-signal test system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0027/MQ50616.pdf.

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Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.

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Liu, Dong. "Analog and mixed-signal test and fault diagnosis." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1177701780.

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Ozev, Sule. "High level test approaches for mixed-signal systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2002. http://wwwlib.umi.com/cr/ucsd/fullcit?p3070993.

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Chowdhury, Azhar. "A probabilistic test instrument using sigma-delta phase signal generation technique for mixed signal embedded test." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=107696.

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A probabilistic test instrument is proposed for mixed-signal embedded test applications. The system architecture of the instrument and its implementation is presented. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. Using statistical methods, the probability distributions associated with these signals can be extracted using a simple circuit called a probability extraction unit, consisting of a few simple digital logic gates. At the core of this work is the use of ΣΔ phase-encoding technique to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. This technique is also used for generating the test stimulant for the device-under-test, or DUT as a shorthand notation. Experimental results reveal the sampling time strobe can be programmed over a phase range of 45 degrees with a phase step of 1 degree at a fixed voltage reference. The DUT stimulant and the timing and voltage references are all programmable in software. This provides additional flexibility and versatility when conducting a test. A prototype of the proposed test instrument was implemented using discrete components assembled on a printed-circuit board and shown to be capable of measuring the output jitter distribution associated with a clock and data signal of a DUT. It was further extended to measure the phase and frequency response of various analog channels associated with the DUT. The performance of the instrument was evaluated by comparing the test results with those obtain using other test techniques, independent of the instrument.<br>Un instrument pour les tests "mixed-signal" basé sur une approche statistique est proposé. L'architecture du système ainsi que son implémentation sont présentés. L'instrument peut être utilisé afin d'injecter ou de capturer des informations en temps et voltage associé aux signaux de hautes fréquences dans les systèmes de communication. En utilisant une approche statistique, la distribution de probabilité associée à un signal peut être calculée à l'aide d'un circuit appelé « probability extraction unit » implémenté de façon digital. De plus, l'utilisation de ΣΔ pour encoder des signaux dans la phase afin de générer des signaux dans le temps ainsi que des références pour du « high speed sampling » est démontré. Les résultats expérimentaux démontrent que des variations de phase de 45 degrés avec des intervalles de1 degré est possible. Ceci permet donc plus de flexibilité pour générer des signaux de tests qui sont programmables. Un prototype de cette technique fut implémenté sur « PCB » afin de démontrer que la technique est fonctionnelle. Les résultats des tests furent également comparés à ceux obtenus avec des instruments de mesures traditionnels et démontrent une excellente corrélation entre la méthode développée et les méthodes existantes.
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Hafed, Mohamed M. "Analog and mixed-signal test methods using on-chip embedded test cores." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=38487.

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A robust method has been developed for the test and characterization of analog and mixed-signal integrated circuits. The method relies on a compact, robust, and easily synthesized integrated test core capable of emulating the function of external automatic test equipment. The core consists of a 2 x N memory whose contents are periodically circulated, a coarse analog filter, and a voltage comparator. One half of the circular memory is used to generate analog signals without the need for multi-bit digital-to-analog converters. The second half is used to generate extremely accurate DC levels, the latter being programmed using a clever software encoding technique that relies on some form of sigma-delta modulation. The DC levels, in combination with the comparator, enable multi-bit digitization using a progressive multiple conversion pass procedure. In order to accommodate broadband circuit phenomena, a delayed-clock sub-sampling mechanism is also employed, in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. One method of delaying the clock is to use a voltage-controlled delay line tuned by a delay-locked loop. The timing resolution of this approach is determined by the value of the consistent clock delay and not its period.<br>A divide-and-conquer approach to the test of deeply embedded analog integrated circuits using the proposed test core is described. Multiple test configurations are presented that can span a wide range of phenomena to be tested both internally to the integrated circuit and externally through I/O interfaces. The applicability of these configurations to increasing test parallelism both at the core and die levels is investigated. Performance limits of the proposed test core are also derived by drawing a comparison to conventional circuits used for data-conversion applications. The same fundamental limitations on integrated circuit performance are shown to affect the test core electronics, although test-specific requirements, such as forcing periodicity and the reliance on software signal processing, help further enhance on-chip measurement accuracy and repeatability. Finally, several successful experimental prototypes that demonstrate the viability of the proposed approach are presented. The prototypes range from concept proving test core integrated circuits to ones containing multiple simultaneously operated test cores and completely embedded circuits under test. In total, several hundred different test cores have been demonstrated, which is further testimony to the practicality of the proposed techniques.
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Ahmad, Shakeel. "Stimuli Generation Techniques for On-Chip Mixed-Signal Test." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61712.

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With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer. Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author. Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques. A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.
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Liu, Zhi-Hong. "Mixed-signal testing of integrated analog circuits and modules." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.

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Chen, Jin. "Fault modeling and test techniques for analog and mixed-signal circuits /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Books on the topic "Mixed signal test"

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Demystifying mixed-signal test methods. Newnes, 2003.

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Critchlow, E. A. J. Automatic generation of mixed-signal test programs. UMIST, 1997.

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Sánchez, Gloria Huertas, Diego Vázquez García de la Vega, Adoración Rueda Rueda, and José Luis Huertas Díaz. Oscillation-Based Test in Mixed-Signal Circuits. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5315-0.

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1959-, Roberts Gordon W., ed. An introduction to mixed-signal IC test and measurement. Oxford University Press, 2001.

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Roberts, Gordon W. Analog signal generation for built-in-self-test of mixed-signal integrated circuits. Kluwer Academic Publishers, 1995.

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Roberts, Gordon W. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Springer US, 1995.

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Roberts, Gordon W., and Albert K. Lu. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3.

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Huertas, José L. Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004.

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Diamant, P. E. Automatic generation of mixed signal test programs from circuitsimulation data. UMIST, 1994.

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Huertas, José L. Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004.

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Book chapters on the topic "Mixed signal test"

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Schneider, Birger. "Mixed-Signal Test." In Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9_2.

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Dufort, Benoit, та Gordon W. Roberts. "Mixed-Signal Testing". У Analog Test Signal Generation Using Periodic ΣΔ-Encoded Data Streams. Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4377-0_2.

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Bertrand, Y., F. Azaïs, M.-L. Flottes, and R. Lorival. "Mixed-Signal Test Training at CRTC." In Microelectronics Education. Springer Netherlands, 2000. http://dx.doi.org/10.1007/978-94-015-9506-3_58.

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Sánchez, Gloria Huertas, Diego Vázquez García de la Vega, Adoración Rueda Rueda, and José Luis Huertas Díaz. "Oscillation-Based Test Methodology." In Oscillation-Based Test in Mixed-Signal Circuits. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5315-0_1.

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Soma, Mani. "System Test Methodologies Using IEEE 1149.4." In Analog and Mixed-Signal Boundary-Scan. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4499-6_4.

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Loukusa, Veikko. "Behavioral Testing of Mixed-Signal Circuits." In Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9_6.

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Azaïs, Florence, and Pascal Nouet. "Analog and Mixed-Signal Test Bus: IEEE 1149.4 Test Standard." In Test and Design-for-Testability in Mixed-Signal Integrated Circuits. Springer US, 2004. http://dx.doi.org/10.1007/978-0-387-23521-9_3.

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Sánchez, Gloria Huertas, Diego Vázquez García de la Vega, Adoración Rueda Rueda, and José Luis Huertas Díaz. "OBT Methodology for Discrete-Time Filters." In Oscillation-Based Test in Mixed-Signal Circuits. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5315-0_3.

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Sánchez, Gloria Huertas, Diego Vázquez García de la Vega, Adoración Rueda Rueda, and José Luis Huertas Díaz. "OBT Implementation in Discrete-Time Filters." In Oscillation-Based Test in Mixed-Signal Circuits. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5315-0_5.

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Sánchez, Gloria Huertas, Diego Vázquez García de la Vega, Adoración Rueda Rueda, and José Luis Huertas Díaz. "OBT-OBIST silicon validation." In Oscillation-Based Test in Mixed-Signal Circuits. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5315-0_7.

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Conference papers on the topic "Mixed signal test"

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Jurga, Krzysztof, and Stephen Sunter. "Measuring mixed-signal test stimulus quality." In 2018 IEEE European Test Symposium (ETS). IEEE, 2018. http://dx.doi.org/10.1109/ets.2018.8400688.

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Hulse, R. "A mixed signal analog test bus framework." In Proceedings International Test Conference 1992. IEEE, 1992. http://dx.doi.org/10.1109/test.1992.527873.

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Dufils, M., J. L. Carbonero, P. Planelle, and P. Raynaud. "Mixed-signal simulation and test generation." In International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. IEEE, 2006. http://dx.doi.org/10.1109/dtis.2006.1708704.

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"Session B1: Analog/mixed signal test." In 2017 International Test Conference in Asia (ITC-Asia). IEEE, 2017. http://dx.doi.org/10.1109/itc-asia.2017.8097099.

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Shanbhag, N., and A. Singer. "System-assisted analog mixed-signal design." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763242.

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O'Riordan, J. J. "Mixed signal test development in a virtual test environment." In IEE Colloquium on Testing Mixed Signal Circuits and Systems. IEE, 1997. http://dx.doi.org/10.1049/ic:19971199.

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Kruseman, Bram, Bratislav Tasic, Camelia Hora, et al. "Defect Oriented Testing for analog/mixed-signal devices." In 2011 IEEE International Test Conference (ITC). IEEE, 2011. http://dx.doi.org/10.1109/test.2011.6139127.

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Sunter, Stephen, Alessandro Valerio, and Riccardo Miglierina. "Measuring defect tolerance within mixed-signal ICs." In 2016 IEEE European Test Symposium (ETS). IEEE, 2016. http://dx.doi.org/10.1109/ets.2016.7519320.

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Stratigopoulos, Haralampos-G., and Christian Streitwieser. "Adaptive test flow for mixed-signal ICs." In 2017 IEEE 35th VLSI Test Symposium (VTS). IEEE, 2017. http://dx.doi.org/10.1109/vts.2017.7928919.

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Park, Joonsung, Hongjoong Shin, and Jacob A. Abraham. "Parallel Loopback Test of Mixed-Signal Circuits." In 26th IEEE VLSI Test Symposium (vts 2008). IEEE, 2008. http://dx.doi.org/10.1109/vts.2008.53.

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