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Hajjar, Ara. "An integrable mixed-signal test system /." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21298.
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The growing need for integrable test solutions has prompted the creation of various test bus standards. A mixed-signal test core is an ideal complement to these standards. This work presents the design and implementation of an integrable test system. The design consists of two major components: a stimulus generator, and a waveform extractor.<br>A memory-based generator is used to construct the stimulus generation component. Such a circuit repeats a finite portion of an infinite-length PDM sequence in order to produce any arbitrary analog waveform. The circuitry is simple to design---it is comprised of a scan chain, and a 1-bit DAC; it is also area-efficient and robust (mostly digital design). Furthermore, since the analog signal is generated from a digital bit-stream, it is both stable and repeatable.<br>The extraction component of the test system focuses on the capture of steady-state type responses. A novel A/D algorithm is presented: the Multi-Pass technique. By taking advantage of repetitive waveforms, the Multi-Pass convertor achieves both area-efficiency and high-speed performance. A single on-chip comparator and sample-and-hold circuit is sufficient to extract analog waveforms. In addition, a novel, area-efficient, integrable, and highly-linear voltage reference design is presented.<br>Experimental results from two prototype boards serve to validate the proposed test system design. The first board implements the system using discrete components; the second makes use of a custom IC fabricated in a 0.5 mum CMOS process. The work presented in this thesis provides the groundwork for obtaining a practical and fully integrable mixed signal test system.
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Hajjar, Ara. "An integrable mixed-signal test system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0027/MQ50616.pdf.
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Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.
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Liu, Dong. "Analog and mixed-signal test and fault diagnosis." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1177701780.
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Ozev, Sule. "High level test approaches for mixed-signal systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2002. http://wwwlib.umi.com/cr/ucsd/fullcit?p3070993.
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Chowdhury, Azhar. "A probabilistic test instrument using sigma-delta phase signal generation technique for mixed signal embedded test." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=107696.
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A probabilistic test instrument is proposed for mixed-signal embedded test applications. The system architecture of the instrument and its implementation is presented. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. Using statistical methods, the probability distributions associated with these signals can be extracted using a simple circuit called a probability extraction unit, consisting of a few simple digital logic gates. At the core of this work is the use of ΣΔ phase-encoding technique to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. This technique is also used for generating the test stimulant for the device-under-test, or DUT as a shorthand notation. Experimental results reveal the sampling time strobe can be programmed over a phase range of 45 degrees with a phase step of 1 degree at a fixed voltage reference. The DUT stimulant and the timing and voltage references are all programmable in software. This provides additional flexibility and versatility when conducting a test. A prototype of the proposed test instrument was implemented using discrete components assembled on a printed-circuit board and shown to be capable of measuring the output jitter distribution associated with a clock and data signal of a DUT. It was further extended to measure the phase and frequency response of various analog channels associated with the DUT. The performance of the instrument was evaluated by comparing the test results with those obtain using other test techniques, independent of the instrument.<br>Un instrument pour les tests "mixed-signal" basé sur une approche statistique est proposé. L'architecture du système ainsi que son implémentation sont présentés. L'instrument peut être utilisé afin d'injecter ou de capturer des informations en temps et voltage associé aux signaux de hautes fréquences dans les systèmes de communication. En utilisant une approche statistique, la distribution de probabilité associée à un signal peut être calculée à l'aide d'un circuit appelé « probability extraction unit » implémenté de façon digital. De plus, l'utilisation de ΣΔ pour encoder des signaux dans la phase afin de générer des signaux dans le temps ainsi que des références pour du « high speed sampling » est démontré. Les résultats expérimentaux démontrent que des variations de phase de 45 degrés avec des intervalles de1 degré est possible. Ceci permet donc plus de flexibilité pour générer des signaux de tests qui sont programmables. Un prototype de cette technique fut implémenté sur « PCB » afin de démontrer que la technique est fonctionnelle. Les résultats des tests furent également comparés à ceux obtenus avec des instruments de mesures traditionnels et démontrent une excellente corrélation entre la méthode développée et les méthodes existantes.
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Hafed, Mohamed M. "Analog and mixed-signal test methods using on-chip embedded test cores." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=38487.
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A robust method has been developed for the test and characterization of analog and mixed-signal integrated circuits. The method relies on a compact, robust, and easily synthesized integrated test core capable of emulating the function of external automatic test equipment. The core consists of a 2 x N memory whose contents are periodically circulated, a coarse analog filter, and a voltage comparator. One half of the circular memory is used to generate analog signals without the need for multi-bit digital-to-analog converters. The second half is used to generate extremely accurate DC levels, the latter being programmed using a clever software encoding technique that relies on some form of sigma-delta modulation. The DC levels, in combination with the comparator, enable multi-bit digitization using a progressive multiple conversion pass procedure. In order to accommodate broadband circuit phenomena, a delayed-clock sub-sampling mechanism is also employed, in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. One method of delaying the clock is to use a voltage-controlled delay line tuned by a delay-locked loop. The timing resolution of this approach is determined by the value of the consistent clock delay and not its period.<br>A divide-and-conquer approach to the test of deeply embedded analog integrated circuits using the proposed test core is described. Multiple test configurations are presented that can span a wide range of phenomena to be tested both internally to the integrated circuit and externally through I/O interfaces. The applicability of these configurations to increasing test parallelism both at the core and die levels is investigated. Performance limits of the proposed test core are also derived by drawing a comparison to conventional circuits used for data-conversion applications. The same fundamental limitations on integrated circuit performance are shown to affect the test core electronics, although test-specific requirements, such as forcing periodicity and the reliance on software signal processing, help further enhance on-chip measurement accuracy and repeatability. Finally, several successful experimental prototypes that demonstrate the viability of the proposed approach are presented. The prototypes range from concept proving test core integrated circuits to ones containing multiple simultaneously operated test cores and completely embedded circuits under test. In total, several hundred different test cores have been demonstrated, which is further testimony to the practicality of the proposed techniques.
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Ahmad, Shakeel. "Stimuli Generation Techniques for On-Chip Mixed-Signal Test." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61712.
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With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer. Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author. Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques. A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.
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Liu, Zhi-Hong. "Mixed-signal testing of integrated analog circuits and modules." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.
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Chen, Jin. "Fault modeling and test techniques for analog and mixed-signal circuits /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
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Butler, I. C. "Signal quantization and its implications for transient response testing." Thesis, University of Huddersfield, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.338603.
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Gómez, Pau Álvaro. "Mixed-signal alternate test and binning using digitally encoded signatures." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/457633.
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Integrated circuit industry has always faced the necessity of testing and verifying the fabricated ICs in order to guarantee that no faulty circuits reach the market as well as the fabricated devices function within design specifications throughout their entire service life. In the current frame, the accomplishment of this objective entangles considerable economic implications and great technological challenges. Analog and mixed-signal circuit testing becomes an even more challenging endeavor since no efficient nor systematic procedures are available. Further, these challenges are strongly related to the process variability induced by the constant feature size miniaturization as well as by circuit operating conditions (i.e. PVTA variations). As opposed to the classic or specification based testing, alternate testing techniques have been lately adopted as a promising solution in such challenging scenario.
In this thesis, a novel methodology to encode the pass/fail regions in the alternate measurements space is proposed. The method relies on two phases. The training phase digitally encodes the test acceptance/rejection regions in the alternate measurements space using octrees. The testing phase corresponds to the actual production testing using the previously computed octree data structure. Such digital encoding approach presents a number of benefits, specially in terms of computational efficiency since the resulting octree structures are inherently sparse, what yields to fast training and testing times. Octrees have the advantage of being generalized to an arbitrary number of dimensions without any extra issue. Regarding such generalization potential, octrees can extend their clustering capabilities to more than two clusters, therefore facilitating the proposed IC quality binning approach without any incurred overhead. Further, the octree encoding algorithm is deterministic as it does not rely on a minimization algorithm as many of the state of the art clustering methods do. This is a desirable feature since the resulting encoding does not depend on convergence issues or the considered initial conditions. The simplistic recursive implementation, both for training and testing, make them affordable and easy to implement in stand alone systems as well as convenient for BIST applications.
Within the current "more than Moore" scenario, testing heterogeneous devices entangles a series of non trivial challenges which are even harder to cope than the ones existing in traditional CMOS circuits. This is so because of their inherently non electrical nature, depending on the exploited transduction principle, creates the need of complex stimuli generation. For the particular case of MEMS accelerometers, a mechanical excitation stimulus is needed in order to emulate in field operation. In this thesis, a method consisting on a variable speed vertical spinning wheel mounting the device under test has been proposed. The composition of output signals under such excitation conditions yields to an analog trace characterizing the defect level. The analog signature is used to test the device based on the octree encoding of the alternate measurements space or used for diagnosis purposes by means of a signature compaction and feature extraction procedure.
The selection and acquisition of analog signatures for alternate mixed-signal testing is an issue of major concern in the field. This thesis proposes a selection algorithm based on redundancy avoidance within the selected set of indirect measurements yet keeping the maximum information to perform the test decision. The application of such selection algorithm immediately translates into better test results.<br>La industria de fabricación de circuitos integrados siempre se ha enfrentado a la necesidad de testar y verificar los circuitos con el objetivo de garantizar que ningún dispositivo defectuoso llega al mercado y que los circuitos fabricados cumplen sus especificaciones de diseño durante toda su vida de servicio. En el marco actual, la consecución de este objetivo conlleva considerables implicaciones económicas así como desafíos tecnológicos importantes. El test de circuitos analógicos y de señal mixta supone un reto todavía mayor ya que no existen metodologías eficientes ni sistemáticas para afrontarlo. Estos retos están fuertemente ligados a las variaciones de proceso inducidas por la continua miniaturización de los transistores así como también las condiciones de operación de cada circuito (variaciones PVTA). Contrariamente al test clásico o basado en especificaciones, se han ido adoptando técnicas de test alternativo como una solución prometedora en el escenario mencionado. Esta tesis propone una metodología novedosa para codificar las regiones de pass/fail en test alternativo de circuitos analógicos y de señal mixta. El método se fundamenta en dos fases. La fase de entrenamiento codifica digitalmente las regiones de aceptación/rechazo en el espacio de medidas alternativas usando octrees. La fase de test se corresponde con el proceso de test en producción usando la estructura de datos previamente computada. Esta codificación digital presenta una serie de ventajas, principalmente en términos de eficiencia computacional ya que la estructura octree resultante es inherentemente dispersa, lo que implica un rápido entrenamiento y test. Los octrees presentan la ventaja de ser fácilmente generalizables a un número arbitrario de dimensiones sin mayores inconvenientes. Con respecto a esta capacidad de generalización, sus capacidades de clasificación pueden extenderse a más de dos clusters, permitiendo así su uso en binning de calidad sin mayor overhead. El algoritmo de codificación con octrees es determinista ya que no depende de algoritmos de minimización como la mayoría de los métodos de clasificación del estado del arte. Esta es una cualidad deseable pues la codificación resultante no presenta problemas de convergencia ni depende de las condiciones iniciales consideradas. La implementación recursiva, tanto para la fase de entrenamiento como de test, los hace asequibles para su implementación en sistemas autónomos y convenientes para aplicaciones BIST. Dentro del escenario "más que Moore" actual, el test de sistemas heterogéneos conlleva una serie de retos no triviales ya que son incluso más difíciles de solventar que los existentes en circuitos CMOS clásicos. Esto es así debido a su inherente naturaleza no eléctrica pues crea la necesidad de generación de estímulos complejos. Par el caso particular de acelerómetros MEMS, se requiere una excitación mecánica para emular el funcionamiento en campo del dispositivo. Esta tesis propone el uso de una rueda vertical de velocidad variable en la cual se monta el dispositivo bajo test. La composición de las señales de salida da lugar a una firma analógica que caracteriza el nivel de defecto. Esta signatura analógica se usa para testar el dispositivo usando una codificación con octrees del espacio de medidas alternativas o bien para diagnóstico mediante un proceso de compactación y extracción de características. La selección y adquisición de signaturas analógicas para test alternativo de circuitos de señal mixta es un tema importante en el campo. Esta tesis propone un algoritmo de selección cuyo objetivo es evitar la redundancia dentro del conjunto de medidas indirectas seleccionado mientras se intenta mantener la máxima información de éstas para tomar la decisión de test. La aplicación de este algoritmo de selección se traduce en la mejora inmediata de los resultados de test.
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Taillefer, Chris. "Reducing measurement uncertainty in a DSP-based mixed-signal test environment." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84104.
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FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements.<br>A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test.<br>An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.
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Povazanec, Juraj. "Test process evaluation techniques for analogue and mixed signal integrated circuits." Thesis, Leeds Beckett University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.309793.
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Zakizadeh, Jila. "Built-in self-test techniques for analog and mixed signal circuits." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/27094.
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The present thesis attempts to develop new techniques for testing analog parts of embedded cores-based mixed signal integrated circuits and systems. In particular, the oscillation based test methodologies have been investigated in the thesis. In the oscillation based test methods, the circuit under test (CUT) is first converted to an oscillator in the test mode and the oscillation parameters, viz. frequency, amplitude, etc. are then measured. Any deviation of these parameters causes either the oscillation frequency of the converted CUT to differ from its nominal value, or the converted CUT stops oscillation altogether. For evaluation purpose, a program has been written in C to help us in simulating our test methodologies. The program is used to inject faults to the circuit under test. The detailed experimental results provided give frequency and amplitude measurements data performed on the individual circuit blocks together with fault coverage. In this work, however, only catastrophic faults were considered. The simulation experiments carried out on different circuits not only demonstrate that the developed approaches are quite feasible but show in addition that the fault coverage is quite satisfactory (100%) in all cases.
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Alani, Alaa Fadhil. "A steady-state response test generation technique for mixed-signal integrated circuits." Thesis, Brunel University, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316941.
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Gopalan, Anand. "Built-in-self-test of RF front-end circuitry /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/942.
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Bell, Ian M. "Developments in testing and design for test of mixed signal electronic circuits and systems." Thesis, University of Hull, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.441756.
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Binns, Richard James. "Testing analogue macros in mixed-signal systems using transient response testing and dynamic supply current monitoring." Thesis, University of Huddersfield, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.338600.
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Xing, Hanqing. "Fully digital-compatible built-in self-test solutions to linearity testing of embedded mixed-signal functions." [Ames, Iowa : Iowa State University], 2008.
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Gomes, Alfred Vincent. "Alternate Test Generation for Detection of Parametric Faults." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5285.
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Tests for detecting faults in analog and mixed-signal circuits have been traditionally
derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important
aspects of the device, in many cases these application oriented tests are costly to implement
and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening.
In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The
test generator is uses a search-based procedure that requires evaluation of a large number
of candidate tests. Test evaluation is expensive because of complex fault models and slow
fault simulation techniques. A tester-resident test evaluation technique is developed to
address this issue. This method is not limited by simulation complexity nor does it require
an explicit fault model. Making use of these two developments, an efficient and automated
test generation method is developed. Theoretical development and a number of examples
are used to illustrate various concepts that are presented in this thesis.
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Zheng, Qinghua (Cindy). "A DSP feedback system on a mixed signal tester and its application in ADC test by Quinghua (Cindy) Zheng." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38114.
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Goyal, Shalabh. "Efficient Testing of High-Performance Data Converters Using Low-Cost Test Instrumentation." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14552.
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Test strategies were developed to reduce the overall production testing cost of high-performance data converters. A static linearity testing methodology, aimed at reducing the test time of A/D converters, was developed. The architectural information of A/D converters was used, and specific codes were measured. To test a high-performance A/D converters using low-performance and low-cost test equipment a dynamic testing methodology was developed. This involved post processing of measurement data. The effect of ground bounce on accuracy of specification measurement was analyzed, and a test strategy to estimate the A/D converter specifications more accurately in presence of ground bounce noise was developed.
The proposed test strategies were simulated using behavioral modeling techniques and were implemented on commercially available A/D converter devices. The hardware experiments validated the proposed test strategies. The test cost analysis was done. It suggest that a significant reduction in cost can be obtained by using the proposed test methodologies for data converter production testing.
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Andrade, Junior Antonio de Quadros. "Planejamento de teste de sistemas baseados em núcleos de hardware de sinal misto usando bist." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/8296.
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Atualmente, os sistemas eletrônicos integrados seguem o paradigma do projeto baseado em núcleos de hardware. Além de núcleos digitais, tais sistemas podem incluir núcleos analógicos, que, neste caso, dominam os requisitos de teste, como tempo de teste e número adicional de pinos. Consequentemente, há um aumento do custo total de manufatura do dispositivo. O presente trabalho propõe o uso de técnicas de autoteste integrado (BIST) analógico, baseado no reuso de núcleos digitais presentes no mesmo sistema, com objetivo de reduzir os custos relativos ao teste do sistema. Além disso, uma estratégia satisfatória requer um adequado planejamento de teste, de forma a melhor explorar as possibilidades de teste simultâneo de mais de um núcleo e o escalonamento do teste de cada um destes, diminuindo custos associados ao teste. Adaptando uma ferramenta computacional voltada ao planejamento de sistemas compostos exclusivamente de núcleos digitais para o universo dos sistemas mistos e considerando a possibilidade do uso de BIST, pode-se avaliar o impacto da estratégia proposta em termos de tempo de teste, acréscimo de área em virtude das estruturas de teste e pinos extras. Restrições de dissipação de potência também são consideradas. Para validação das hipóteses levantadas, sistemas mistos foram descritos a partir de benchmarks industriais e acadêmicos puramente digitais, através da inclusão de núcleos analógicos. Os resultados obtidos através de simulações com a ferramenta apontam para uma redução no tempo de teste e otimização de custos de pinos e área, além da redução no custo de equipamentos automatizados de teste (ATE), para o caso de teste de produção. Com isso, uma redução no custo total do procedimento de teste de tais sistemas pode ser alcançada.<br>Currently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.
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Devarakond, Shyam Kumar. "Signature driven low cost test, diagnosis and tuning of wireless systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47594.
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With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.
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Mozuelos, García Román. "Test basado en sensores de corriente internos para circuitos integrados mixtos (analógicos-digitales)." Doctoral thesis, Universidad de Cantabria, 2009. http://hdl.handle.net/10803/10708.
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En esta tesis se propone un método de diseño para test orientado hacia circuitos mixtos empotrados. El método de test está basado en el análisis del consumo de corriente dinámica (IDDX) tanto estacionaria como transitoria.Con objeto de procesar adecuadamente la información de los transitorios de corriente, la medida se efectúa internamente integrando dentro del chip un bloque sensor de corriente (BICS) junto al circuito bajo test (CUT). Se ha desarrollado una estructura del módulo sensor para otorgar más peso específico al muestreo de las componentes de alta frecuencia de la corriente.El método de test estructural propuesto busca disminuir el tiempo necesario para realizar el test y reducir la complejidad de los equipos de medida comúnmente utilizados en el test analógico. Por ello, el circuito sensor de corriente realiza un procesado de la información para proporcionar una firma digital que codifica el funcionamiento del circuito. La tesis también extiende la propuesta de test a circuitos de capacidades conmutadas (SC) utilizando un circuito sensor de carga integrado junto al circuito bajo test.<br>This thesis describes a design-for-test method for embedded mixed signal circuits. It is based on the analysis of the dynamic current consumption (IDDX), both quiescent and transient.In order to correctly process the information contained in the transient current, the measurement is performed by a built-in current sensor circuit (BICS) integrated within the circuit under test (CUT). A structure for the sensor block has been developed to give more specific weight to the high-frequency components of the current.The proposed structural test method aims to reduce the test time and the complexity of the measurement equipment commonly used in analog tests. Therefore, the current sensor performs internal data processing to provide a digital signature that encodes the circuit behaviour.The thesis also extends the test method to switched capacitor circuits (SC) using a charge sensor circuit integrated within the circuit under test.
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Dogaru, Emanuel. "Built-In Self-Test of Flexible RF Transmitters Using Nonuniform Undersampling." Thesis, CentraleSupélec, 2015. http://www.theses.fr/2015SUPL0004/document.
Full textAbstract:
Le secteur de communications sécurisés et portables connait une véritable révolution avec l’apparition des plateformes dites radios logiciels (Software Defined Radios, SDRs). Les performances exceptionnelles de ces systèmes sont les résultats d’une interaction assez complexe et souvent peu évidente entre le logiciel embarqué, le circuit de traitement numérique et les blocs mixtes analogiques/RF. Cette complexité limite la testabilité du produit fini. La méthodologie de test utilisée actuellement a atteint ses limites dues au cout élevé, le long temps de test et le bas degré de généralisation. De plus, les plateformes SDRs peuvent évoluer sur le terrain et elles vont supporter des standards et des scénarios qui n’ont pas été considérés pendant le la phase de conception. Donc, une stratégie de test sur le terrain (en ligne) n’est plus une caractéristique optionnelle mais une nécessité. Dans ce contexte, le but de notre recherche est d’inventer et développer une méthodologie de test capable de garantir le bon fonctionnement d’une plateforme SDR après la production et pendant sa vie. Notre objectif final est de réduire le coût du test en profitant de la reconfigurabilité de la plateforme. Pour les radios tactiques qui doivent être mises à jour sur le terrain sans équipement spécial, les stratégies Built-In Self-Test (BIST) sont, sans doute, la seule moyenne de garantir la conformité aux spécifications. Dans cette mémoire, nous introduisons une nouvelle architecture de test RF BIST qui utilise la technique de de sous-échantillonnage nonuniform à la sortie de l’émetteur (TX) d’une SDR afin d’évaluer la conformité de la masque spectrale. Notre solution s’appuie sur une implémentation autonome, est modulable et peut être appliquée pour le test sur le terrain avec des modifications minimes. Par rapport aux autres techniques de test analogiques/RF, cet approche ne dépends pas de la architecture du TX, ni d’un modèle ad-hoc, ce qui est idéale pour le test des SDRs<br>The advent of increasingly powerful Integrated Circuits (IC) has led to the emergence of the Software Defined Radio (SDR) concept, which brought the sector of secured mobile communications into a new era. The outstanding performance of these systems results from optimal trade-offs among advanced analog/Radio Frequency (RF) circuitry, high-speed reconfigurable digital hardware and sophisticated real-time software. The inherent sophistication of such platforms poses a challenging problem for product testing. Currently deployed industrial test strategies face rising obstacles due to the costlier RF test equipment, longer test time and lack of flexibility. Moreover, an SDR platform is field-upgradeable, which means it will support standards and scenarii not considered during the design phase. Therefore, an in-field test strategy is not anymore 'a nice to have' feature but a mandatory requirement. In this context, our research aims to invent and develop a new test methodology able to guarantee the correct functioning of the SDR platform post-fabrication and over its operational lifetime. The overall aim of our efforts is to reduce post-manufacture test cost of SDR transceivers by leveraging the reconfigurability of the platform.For tactical radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this study we introduce a novel RF BIST architecture which uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. Our solution supports a stand-alone implementation, is scalable across a wide set of complex specifications and can be easily applied for in-field testing with small added hardware. Compared to existing analog/RF test techniques, this approach is not limited to a given TX architecture and does not rely on an ad-hoc TX model, which makes it ideal for SDR testing
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Srinivasan, Ganesh Parasuram. "Efficient Production Testing of High-Performance RF Modules and Systems using Low-Cost ATE." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14113.
Full textAbstract:
The proliferation of wireless communication devices in the recent past has increased the pressure on semiconductor manufacturers to produce quality radio frequency (RF) modules and systems at a low cost. This entails reducing their test cost as well, since the cost of testing modern RF devices can be up to 40% of their manufacturing cost. The high test cost of these devices can be mainly attributed to (a) the expensive nature of the RF automated test equipment (ATE) used to perform wafer-level and fully packaged RF functionality tests, (b) limited test point access for the application and capture of test signals, (c) the long test development and application times, and (d) the lack of diagnostic tools to evaluate and improve the performance of loadboards and test resources in high-volume tests.
In this thesis, a framework for the efficient production testing of high-performance RF modules and systems using low-cost ATE is presented. This framework uses low-speed, low-resolution test resources to generate reliable tests for complex RF systems. Also, the test resources will be evaluated and improved ahead of high-volume tests to improve test yield and throughput. The components of the proposed framework are:
(1) Genetic ATPG for reliable test stimulus generation using low-resolution test resources: A genetic algorithm (GA) based automatic test pattern generator (ATPG) to optimize the alternate test stimulus for reliable testing of complex RF systems using low-resolution, low-cost test resources. These test resources may be on-chip or off-chip.
(2) Concurrent voltage/current alternate test methodology: A testing framework for efficiently testing the high-frequency specifications of RF systems using low-frequency spectral and/or transient current signatures. Suitable on-chip and/or off-chip design-for-test (DfT) resources are used to enable the source and capture operations at lower frequencies.
(3) Loadboard checker: A checker tool to accurately characterize/diagnose the DfT resources on the RF loadboards used to enable test of RF devices/systems using low-cost ATE.
(4) Advanced test signal processing algorithms: The performance of the low-cost ATE resources, in terms of their linearity/resolution, will be evaluated and improved to enable the accurate capture of the test response signals.
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Souza, Junior Adao Antonio de. "Digital approach for the design of statistical analog data acquisition on SoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/11491.
Full textAbstract:
With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:
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Dubois, Matthieu. "Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633056.
Full textAbstract:
L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
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Perkins, Andrew John. "Structural testing and DFT insertion for analogue and mixed signal integrated circuits." Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299287.
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Rummens, François. "Systèmes intégrés pour l'hybridation vivant-artificiel : modélisation et conception d'une chaîne de détection analogique adaptative." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0431/document.
Full textAbstract:
La bioélectronique est un domaine transdisciplinaire qui oeuvre, entre autres, àl’interconnexion entre des systèmes biologiques présentant une activité électrique et le mondede l’électronique. Cette communication avec le vivant implique l’observation de l’activitéélectrique des cellules considérées et nécessite donc une chaine d’acquisition électronique.L’utilisation de Multi/Micro Electrodes Array débouche sur des systèmes devantacquérir un grand nombre de canaux en parallèle, dès lors la consommation etl’encombrement des circuits d’acquisition ont un impact significatif sur la viabilité dusystème destiné à être implanté.Cette thèse propose deux réflexions à propos de ces circuits d’acquisition. Une ces desréflexions a trait aux circuits d’amplification, à leur impédance d’entrée et à leurconsommation ; l’autre concerne un détecteur de potentiels d’action analogique, samodélisation et son optimisation.Ces travaux théoriques ayant abouti à des résultats concrets, un ASIC a été conçu,fabriqué, testé et caractérisé au cours de cette thèse. Cet ASIC à huit canaux comporte doncdes amplificateurs et des détecteurs de potentiels d’action analogiques et constitue le principalapport de ce travail de thèse<br>Bioelectronics is a transdisciplinary field which develops interconnection devicesbetween biological systems presenting electrical activity and the world of electronics. Thiscommunication with living tissues implies to observe the electrical activity of the cells andtherefore requires an electronic acquisition chain.The use of Multi / Micro Electrode Array leads to systems that acquire a large numberof parallel channels, thus consumption and congestion of acquisition circuits have asignificant impact on the viability of the system to be implanted.This thesis proposes two reflections about these acquisition circuits. One of thesereflections relates to amplifier circuits, their input impedance and consumption; the otherconcerns an analogue action potentials detector, its modeling and optimization.These theoretical work leading to concrete results, an ASIC was designed,manufactured, tested and characterized in this thesis. This eight-channel ASIC thereforeincludes amplifiers and analogue action potentials detector and is the main contribution of thisthesis
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Lu, Chin-Ben, and 盧清本. "Mixed Signal Test Bench." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/27509418588437655933.
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Chen, Yue-Tsang, and 陳雨蒼. "Metrology for Mixed-Signal Test Bus." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/44742331246281254463.
Full textAbstract:
博士<br>國立中央大學<br>電機工程研究所<br>88<br>The methodologies are proposed, designed, and implemented for the removal of the parasitic and crosstalk effects associated with IEEE Std. 1149.4 mixed signal test buses. For this, this thesis defines the intrinsic response and derives the extraction algorithms. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effects. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects and crosstalk. The test results using HSPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects, crosstalk, and the variations in the test signals. The proposed methodology is further tested in the real circuit environment using the MNABST-1 test chip designed by Mastsushita/Panasonic and provided by 1149.4 working group.
The test results show that the intrinsic response has an improvement of at least 15 dB as compared to the direct measurement and reassert the claimed advantages. Moreover, the proposed extraction algorithms are robust enough to handle not only the parasitic effects but also the noise in the real measurement environment.
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Lee, Chih Chiang, and 李志強. "Mixed Signal VLSI Design and Test." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/35893616854807827086.
Full textAbstract:
碩士<br>國立清華大學<br>電機工程研究所<br>81<br>The mixed signal ICs attract a great deal of attention from the
industries because of their advantages in economy, performance
and reliability . The design and test of mixed signal VLSI
circuits are more difficult than those of pure digital or
analog circuits because digital circuits and analog circuits
have different characteristics in nature. Sigma delta converter
provides an alternative way to implement a high resolution
analog-to- digital converter which has weaker requirement on
analog components and is cost-effective in production. It uses
the oversampling technique to achieve high resolution. A second-
order fully- pipelined sigma delta modulator is presented in
this thesis. It is a RC structure modulator rather than the
conventional switched-capacitor structure in order to speed up
the performance of the modulator. The behavior simulation,
circuit simulation, circuit layout and functional testing
method are discussed in detail. The sigma delta modulator that
we propose has been manufactured with UMC 0.8 .mu m DPDM CMOS
technology. An analog pole-zero fault model is proposed in this
thesis. Therefore, it helps in generation of test patterns for
detecting AC faults of analog devices. It can be used in
testing of mixed-signal circuits because these test patterns
can be generated by digital testers. We propose a time-domain
test method for analog components such as operational amplifier
in mixed- signal IC based on our fault model. It can detect
both DC and AC faults of analog circuits. Furthermore, it is
cost-effective compared with functional testing method.
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Tabatabaei-Zavareh, Sassan. "Embedded test circuits and methodologies for mixed-signal ICs." Thesis, 2000. http://hdl.handle.net/2429/11198.
Full textAbstract:
The rapid pace of the integrated circuit industry towards more miniaturization is making
system-on-chip (SOC) a reality. For practical implementations of SOC, however, the test
issues of such devices must be addressed through the integration of design-for-testability
(DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital,
memory, and mixed-signal circuits.
This thesis presents two novel embedded test solutions for mixed-signal circuits. The
first one is a built-in current monitor (BICM) suitable for power supply current (IDD) testing.
The B I CM includes a built-in current sensor (BICS) which provides high measurement
sensitivity without introducing a large impedance in the IDD path. Although the BICS
structure has been proposed before, the new circuit analysis and chip measurement results
provide important insights into the BICS characteristics and design trade-offs. The BICM
also includes a mixed-signal built-in current integrator (BICI) which generates a digital signature
proportional to the average IDD (IDD)- TWO different circuits have been developed
for BICI: a single-phase and a double-phase BICI; the first is less accurate but requires less
silicon area. These new BICI architectures offer an advantage over previously proposed
circuits because they can perform integration over large time windows (T > 1 ms) while
occupying a chip area equivalent to a only few hundred NAND gates. The BICM is compact, accurate (error < 2%), and insensitive to process and temperature variations.
The second embedded test circuit is designed for non-intrusive functional testing of
high-speed clock-recovery units (CRU) and clock-synthesis units (CSU). To the author's
knowledge, this new structure is the first circuit which can perform on-chip, single-shot jitter
measurement with high resolution and precision without requiring element matching.
The simulation and analysis predict a jitter measurement resolution of 10ps and a precision
of 11ps in a 0.35 μm CMOS technology under typical power supply and thermal noise conditions.
Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer
characteristics of CRUs and CSUs. The circuit is digital, partially synthesizable, and automatically
placeable and routable. Novel gate delay model and analysis techniques, supported
by simulation, are also introduced to evaluate the accuracy of the circuit.
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You, Jian-Jhih, and 尤建智. "High-Performance Component Design for SOC Test Platforms with Mixed-Signal Test Capability." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/32379442278953153186.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>With the development of process of semi-conductor, more and more functionalities will be provided in a single chip. However, the SOC-based design methodology also introduces many new challenges. In order to test an SOC, the ATE-based testing methodology requires ATE with high frequency, great accuracy and large memory. This ATE will result in high test cost. Moreover, with the increase of SOC complexity, the possibly long test time will also be an important issue. Hence, how to reduce the test cost for SOC becomes an important problem.
In order to address the problems above, in this thesis, we propose the high-performance components for SOC which has high operation speed and supports various types of test methodologies including scan-based testing, memory BIST and ADC BIST. These components contain a high-performance test controller and the test bus. The improved test controller has the ability of 300MHz at-speed testing. As for the test bus, we develop a hierarchical test bus technique. With the aid of this technique, the SOC test platform can support testing of a large number of cores without performance degradation. Experimental results show that by using the proposed techniques, the SOC test platform can be greatly improved.
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Escobar, António José Salazar. "Mixed-signal Test and Measurement Framework for Wearable Monitoring System." Tese, 2015. https://repositorio-aberto.up.pt/handle/10216/97431.
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Dalmia, Kamal. "Built-in jitter test schemes for mixed-signal integrated circuits." Thesis, 1996. http://hdl.handle.net/2429/7771.
Full textAbstract:
Recent years have seen an unparalleled growth in the speed and complexity of VLSI
circuits. Analog and mixed-signal circuits are going through a resurgence and continue
to pose new challenges to VLSI test engineers. The state-of-the-art in the mixed-signal
and analog test domain is to use application-specific test methodologies to tackle individual
problems. The same is true for testing the high-speed clock signals used in present day
integrated circuits (ICs) for their analog attributes. Jitter is one of the ways of quantifying
the accuracy of a clock signal. Present day digital automatic test equipment (ATE) does
not possess enough resolution to be suitable for jitter tests of high-speed clock signals such
as SONET's (Synchronous Optical Network) 155.52 MHz and 622.08 MHz. In this thesis,
the jitter test problem of high-speed clocks is approached with a built-in self-test (BIST)
perspective. A BIST scheme is presented for the jitter tolerance test of clock and data
recovery units typically found in data transceiver ICs. A cost-effective scheme based on the
utilization of existing components for test purposes is presented. Some possible variations
of the presented scheme are discussed. A second BIST scheme, focused on jitter testing of
clock signals in a sampling-based digital signal processing (DSP) environment, is presented.
Again, the focus is on the re-use of typically existing blocks on such ICs.
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Escobar, António José Salazar. "Mixed-signal Test and Measurement Framework for Wearable Monitoring System." Doctoral thesis, 2015. https://repositorio-aberto.up.pt/handle/10216/97431.
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Yu, Hak-soo Abraham Jacob A. "BIST-based performance characterization of mixed-signal circuits." 2004. http://wwwlib.umi.com/cr/utexas/fullcit?p3143498.
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Shin, Hongjoong. "Built-in performance characterization of embedded mixed-signal circuits." Thesis, 2006. http://hdl.handle.net/2152/3485.
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Huang, Chien-Hsiang, and 黃建祥. "RF Specification Test and Related Mixed-Signal IC Design in Bluetooth." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/59196056510858373209.
Full textAbstract:
碩士<br>國立中山大學<br>電機工程學系研究所<br>90<br>In the first part of this thesis, RF specifications of the CSR Bluetooth module were tested rigorously by means of proper equipment setup and manipulation. The tested parameters in the transmitter include output power, spectrum and modulation characteristics. The tested parameters in the receiver include sensitivity and received signal strength indicator. The second part of this thesis was mainly focused on some mixed-signal integrated-circuit designs that can be generally applied to the Bluetooth RF front-end. The design examples include the phase frequency detector, charge pump, and frequency divider in the applications of phase-locked loop. A transconductance-capacitor low-pass filter with tunable cut-off frequencies was also designed to suppress the spurious signals from RF front-end into baseband.
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Yu, Hak-soo 1966. "BIST-based performance characterization of mixed-signal circuits." 2004. http://hdl.handle.net/2152/12706.
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Liu, Meng-Yao, and 劉孟堯. "Extreme Voltage Stress Test of Analog/Mixed Signal ICs for Reliability Enhancement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/67615990735943596106.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程研究所<br>93<br>The framework of extreme-voltage stress test system has been developed to reduce the lost yield caused by gate-oxide defects. However, the framework was developed for the gate-oxide defects that assume with 1/E model, where such a defect model is applicable for the oxide thickness above 5nm. For practical designs with the process of .18 um or below, the oxide thickness is less than 5nm, and thus the defect model with 1/E model may not be applicable accurately. In this study, the defect model with E model will be considered, where the oxide thickness is ranged between 2.7nm to 18.1nm. Therefore, the lifetime and failure rate of intrinsic oxide breakdown can be predicted for a given stress condition.
This thesis demonstrates the methodology that generates the stress vector and deals with stressability enhancement of portions of the circuit having poor stressability. A stressability enhancement strategy using additional hardware is also presented.
In order to demonstrate the developed stress test generation process, we demonstrates the applications of such process to both CMOS SRAM and PLL. It will show that both circuits may pass the conventional Iddq-tests in the presence of gate-oxide defects that occur at some transistors, causing a low reliability. Therefore, semiconductor manufacturers need to take alternative stress tests, expensive burn-in tests, to enhance gate-oxide reliability. However, with the developed stress test vectors, both circuits are fully stressed. As a result, the circuit can achieve a full gate-oxide reliability under the extreme-voltage stress tests without the need of the expensive burn-in tests.
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Chang, Soon-Jyh, and 張順志. "Testing and Built-In Self-Test Techniques for Analog and Mixed-Signal Circuits." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/59048168408304912668.
Full textAbstract:
博士<br>國立交通大學<br>電子工程系<br>91<br>This dissertation studies several topics on testing and built-in self-test for analog and mixed-signal circuits. First, it proposes a systematic method to reduce the number of testing specifications for the specification-based testing method. Next, it proposes and demonstrates two test generation techniques for generating monotone signal for testing the analog linear circuit. Finally, it proposes a simple built-in self-test (BIST) scheme for the digital-to-analog converter (DAC).
Specification reduction can reduce test time, consequently, test cost. For this topic, it starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is employed and the result shows that the specification reduction depends on “testing confidence”.
For the monotone test generation, it aims at generating the test signal for parameter faults under constraints of specifications of the linear analog circuit. It treats tolerance bounds, which are due to fabrication process fluctuations, of tested parameters with a statistical model and map them to an accepted region of the observed signature of the CUT. The generated test stimulus is derived under a proposed test confidence level. Test generation procedures for the monotonic and non-monotonic relationships between the signature and the parameter are proposed and demonstrated respectively.
Finally, a low cost BIST scheme for the DAC is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO) and further transfer these frequencies to different digital codes by using a counter. According to the input and output codes, the performances of a DAC, such as offset error gain error, differential non-linearity (DNL), integral non-linearity (INL), are effectively detected by simply using digital circuits rather than complex analogue circuits. In addition, the annoying DAC output noise problem, which usually exists for the DAC testing, can be solved.
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Chun, Ji Hwan. "Cost effective tests for high speed I/O subsystems." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4460.
Full textAbstract:
The growing demand for high performance systems in modern computing technology drives the development of advanced and high speed designs in I/O structures. Due to their data rate and architecture, however, testing of the high speed serial interfaces becomes more expensive when using conventional test methods. In order to alleviate the test cost issue, a loopback test scheme has been widely adopted. To assess the margin of the signal eye in the loopback configuration, the eye margin is purposely reduced by additional devices on the loopback path or using design for testability (DFT) features such as timing and voltage margining. Although the loopback test scheme successfully reduces the test cost by decoupling the dependency of external test equipment, it has robustness issues such as a fault masking issue and a non-ideality problem of margining circuits. The focus of this dissertation is to propose new methods to resolve the known issues in the loopback test mode. The fault masking issue in a loopback pair of analog to digital and digital to analog converters (ADC and DAC) which can be found in pulse amplitude modulation (PAM) signaling schemes is resolved using a proposed algorithm which separates the characteristics of the ADC and the DAC from a combined loopback response. The non-ideality problem of margining circuit is resolved using a proposed method which utilizes a random jitter injection technique. Using the injected random jitter, the jitter distribution is sampled by undersampling and margining, which provides the nonlinearity information using the proposed algorithm. Since the proposed method requires a random jitter source on the load board, an alternative solution is proposed which uses an intrinsic jitter profile and a sliding window search algorithm to characterize the nonlinearities. The sliding search algorithm was implemented in a low cost high volume manufacturing (HVM) tester to assess feasibility and validity of the proposed technique. The proposed methods are compatible with the existing loopback test scheme and require a minimal area and design overhead, hence they provide cost effective ways to enhance the robustness of the loopback test scheme.<br>text
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Kim, Byoung Ho 1974. "Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test." Thesis, 2007. http://hdl.handle.net/2152/3618.
Full textAbstract:
The widespread use of embedded mixed-signal cores in system-on-chip (SoC) or System-on-Package (SoP) design has been increasingly important in cost-effective manufacturing test for mixed-signal devices. A typical SoP encapsulates many of its internal functions, and its production test is performed by application of test signals to the SoP under control of external Automatic Test Equipment (ATE). However it is a problem that the external ATE does not have direct access to all the internal embedded functions of the SoP. Thus a classical test approach to SoP suffers from limited controllability and observability of its subsystems. Built-in Self-Test (BIST) and Built-off Self-test (BOST) schemes have been suggested and developed to overcome the limitations of conventional test, such as limited test Input/Output (I/O) accessibility as well as high test cost. However most BIST/BOST approaches have limited test accuracy. The focus of the dissertation is to develop a cost-effective performance-based test methodology based on BIST/BOST, while maintaining the same accuracy as conventional test. This dissertation proposes one BIST approach and two BOST schemes. Our BIST methodology presents a methodology for efficient prediction of circuit specifications with optimized signatures. The proposed Optimized Signature-Based Alternate Test (OSBAT) methodology accurately predicts the specifications of a Device Under Test (DUT) using a strong correlation mapping function. The approach overcomes the limitation that analytical expressions cannot precisely describe the nonlinear relationships between signatures and specifications. Our first BOST approach presents a practical methodology for effective prediction of individual dynamic performance parameters of differential devices with a cascaded Radio-Frequency (RF) transformer in loopback mode. The RF transformer produces differently weighted loopback responses, which are used to characterize the DUT dynamic performance. The approach overcomes the imbalance problem of Design for Test (DfT) circuitry on differential signaling, thereby accurately measuring the dynamic performance of differential mixed-signal circuits. The second BOST scheme is an efficient methodology for accurate prediction of aperture jitter using cost-effective loopback methodology. Aperture jitter is precisely separated from input and clock jitter as well as additive noise present in the DUT, by using an efficient loopback scheme. Hardware measurements were performed for all our approaches, and good results were obtained. This fact verifies that all approaches can be practically used for production test in industry.
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Park, Joon Sung. "System level methodology for low cost performance characterization of analog and mixed-signal circuits." 2009. http://hdl.handle.net/2152/6582.
Full textAbstract:
Conventionally, the performances of Analog and Mixed-Signal (AMS)
circuits have been characterized using specification-based functional tests. In
these test methods, the correct functionalities of AMS circuits are verified
by measuring pre-determined specification parameters of AMS circuits. The
conventional test methods provide accurate test results by using various test
equipments which generate functional test signals and capture the test responses
externally. However, due to rapid increase in the performance of AMS
circuits in recent years, the conventional test methods face various challenges
in the aspects of test cost, test time and testability.
The goal of this dissertation is to develop innovative functional test
methods for AMS circuits which are aimed at reducing the test cost and test
time while providing comparable test accuracy to the conventional test methods.
To achieve this goal, efforts have been made to explore the characteristics of AMS circuits in a system level and to research efficient performance characterization
methods based on the system level modeling of Devices Under Test
(DUTs). As a part of these efforts, the pseudorandom test methods for nonlinear
AMS circuits have been developed. In these methods, the pseudorandom
signal is used to excite the DUT and to generate the test response which has
sufficient information to characterize DUT performances. The pseudorandom
test methods use the Volterra series model to capture the nonlinear behaviors
of AMS circuits and to calculate various specification parameters of the
DUT using the pseudorandom test response. In doing so, the performances of
nonlinear AMS circuits can be characterized straightforwardly and accurately
using a low-cost test setup. Also, in an effort to reduce the test time, parallel
test methods of AMS circuits have been developed in which multiple DUTs
are tested simultaneously by sharing a common test setup. In these methods,
the test responses generated from different DUTs are combined together and
the resulting composite test response is used to characterize the performance
of each DUT individually. This will reduce the use of tester resources and will
increase the test throughput beyond the level limited by the test equipments.
The spectral characteristics of test stimulus are studied along with the system
level behavior of AMS circuits to develop the efficient parallel test methods.
Finally, in order to consider the practical issue of generating at-speed test stimuli
for high-speed DUTs using a low-cost test setup, a reconfigurable built-off
test interface is developed which can be used to generate various test patterns,
including high-speed pseudorandom signal, using a low-speed tester.<br>text
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Dasnurkar, Sachin. "Methods for high volume mixed signal circuit testing in the presence of resource constraints." 2012. http://hdl.handle.net/2152/19831.
Full textAbstract:
Analog and mixed signal device testing is resource intensive due to the spectral and temporal speci cations of the input/output interface signals. These devices and circuits are commonly validated by parametric speci fication tests to ensure compliance with the required performance criteria. Analog signal complexity increases resource requirements for the Automatic Test Equipment (ATE) systems used for commercial testing, making mixed signal testing resource ine cient as compared to digital structural testing. This dissertation proposes and implements a test ecosystem to address these constraints where Built In Self Test (BIST) modules are designed for internal stimulus generation. Data learning and processing algorithms are developed for output response shaping. This modi ed output response is then compared against the established performance matrices to maintain test quality with low cost receiver hardware. BIST modules reduce dependence on ATE resources for stimulus and output observation while improving capability to test multiple devices in parallel. Data analysis algorithms are used to predict specification parameters based on learning methods applied to measurable device parameters. Active hardware resources can be used in conjunction with post processing resources to implement complex speci cation based tests within the hardware limitations. This dissertation reviews the results obtained with the consolidated approach of using BIST, output response analysis and active hardware resources to reduce test cost while maintaining test quality.<br>text