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Academic literature on the topic 'Modelisation au niveau transactionnel'
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Dissertations / Theses on the topic "Modelisation au niveau transactionnel"
Belhadj, Amor Zeineb. "Validation de systèmes sur puce complexes du niveau transactionnel au niveau transfert de registres." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT083/document.
Full textThe context of this thesis is the functional verification of complex integrated circuits.The objective of our work is to create a seamless verification flow joint to the design flowand based on a proved technique called Assertions-Based Verification (ABV). The mainchallenge of TLM to RTL refinement is the disparity of these two domains : at TLM,communications are modeled as atomic function calls handling all the exchanged data.At RTL, communications are performed by signals according to a specific communicationprotocol. The proposed temporal transformation process is based on a set of formaltransformation rules. We have developed a tool performing the automatic refinement ofPSL specifications. As for design refinement assertion refinement is not fully automated.Temporal and structural information must be provided by the user, using an ergonomicinterface. The tool allows the generation of assertions in RTL but also hybrid assertions.Little work has been done before in this area, and the proposed solutions suffer from severerestrictions. To our knowledge, our prototype is the first tool that performs a temporaltransformation of assertions based on the formal semantics of a standard specificationlanguage (PSL)
Pessoa, Isaac Maia. "Simulation parallèle de systèmes multi-processeurs intégré sur puce modélisé en systemC au niveau transactionnel." Paris 6, 2011. http://www.theses.fr/2011PA066507.
Full textViaud, Emmanuel. "Modélisation SystemC d'architectures multi-processeurs intégrées sur puce au niveau transactionnel avec représentation du temps." Paris 6, 2009. http://www.theses.fr/2009PA066118.
Full textLe, Moigne Rocco. "Modélisation et simulation basée sur systemC des systèmes monopuces au niveau transactionnel pour l'évaluation de performances." Nantes, 2005. http://www.theses.fr/2005NANT2040.
Full textThe fast evolution of microelectronic technologies and their ever-improving integration capacities made possible the appearance of a new generation of components on the market: the “System-on-Chip”. The complexity involved when designing these new components and the permanent need to increase the productivity of the system design process in order to reduce the time-to-market leads designers to raise the level of abstraction of their simulation models. Thus, our goal is to provide a set of high-level models and software tools enabling designers to conduct very early in the design process the HW/SW co-simulation of systems. All models developed in this thesis are integrated to the SystemC simulation library of CoFluent Design's CoFluent Studio™ software environment. This work was done in the context of the MEDEA+ A502 MESA project
Affes, Hend. "Modélisation au niveau transactionnel de l'architecture et du contrôle relatifs à la gestion d'énergie de systèmes sur puce." Thesis, Nice, 2015. http://www.theses.fr/2015NICE4137/document.
Full textEmbedded systems-on-chip (SoC) invade our daily life. With advances in semiconductor technology, these systems integrate more and more complex and energy-intensive features which generate increasing computation load and memory size requirements. While the complexity of these systems is a key trend, energy consumption has emerged as a critical factor for SoC designers. In this context, we have studied a modeling transactional level approach allowing a description of a clock tree and its management structure to be associated with a functional model, both described at the same abstraction level. This structure developed in a separation of concerns approach provides both the interface to the power consumption management of the hardware components and the application software. All the models developed are gathered in a C++ ClkArch library. To apply to a SystemC-TLM architecture model a clock tree intent with its control part, we propose a methodology based on three steps: specification, modeling and simulation. A verification step based on simulation is also considered using contracts of assertion type. This work aims to build a modelling approach on current design tools. So we propose a representation of a clock and power management structure in the IP-XACT standard allowing a C++ description of the SoC power management structures to be generated. Finally, a power management strategy based on the global functional states of the components of the system architecture is proposed. This strategy avoids local decision-making unsuited to optimized overall power/energy management
Edy, Jérôme. "Modelisation meso-echelle de la redistribution d'especes chimiques au niveau des tropiques." Clermont-Ferrand 2, 1997. http://www.theses.fr/1997CLF21912.
Full textKHOUAS, SALIHA. "Contribution a la modelisation de la perception de haut niveau : apprentissage de descripteurs." Paris 11, 1993. http://www.theses.fr/1993PA112463.
Full textCani, Marie-Paule. "Deformations de surfaces complexes : techniques de haut niveau pour la modelisation et l'animation." Paris 11, 1990. http://www.theses.fr/1990PA112242.
Full textPoulain, Christophe. "Etude et modelisation des contacts electriques bas niveau des contacteurs electromagnetiques en regime statique et dynamique." Paris 6, 1996. http://www.theses.fr/1996PA066751.
Full textKribeche, Redha. "Facteurs physiques de l'erosion significatifs au niveau des flux exportes par les bassins versants. Identification par modelisation." Paris 6, 1999. http://www.theses.fr/1999PA066269.
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