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Relevant bibliographies by topics / Modified Carry Select Adder (MCSLA)

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Academic literature on the topic 'Modified Carry Select Adder (MCSLA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Modified Carry Select Adder (MCSLA)"

1

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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2

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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3

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

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Abstract:

Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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5

Agnes, Shiny Rachel, and Rajakumar.G. "Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2019): 407–10. https://doi.org/10.35940/ijeat.B3271.129219.

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result

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K., Periyarselvam, Saravanakumar G., and Anand M. "A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 37–42. https://doi.org/10.11591/ijeecs.v10.i1.pp37-42.

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Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined r

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K, Periyarselvam, Saravanakumar G, and Anand M. "A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 37. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp37-42.

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Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined r

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Nalina, R., S. S. Ashwini, and M. Z. Kurian Dr. "Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder." International Journal for Research in Applied Science & Engineering Technology 3, no. 7 (2015): 429–32. https://doi.org/10.5281/zenodo.33100.

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Multiplication and addition are most widely and oftenly used arithmetic computations performed in all digital signal processing applications. Multiplication is the basic arithmetic operation which is present in many part of the digital computer especially in signal processing systems such as graphics and computation system. It requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. This paper deals with the basic multiplier that is shift and add multiplier. Accurate op

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K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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Ms. Mayuri Ingole. "Modified Low Power Binary to Excess Code Converter." International Journal of New Practices in Management and Engineering 4, no. 03 (2015): 06–10. http://dx.doi.org/10.17762/ijnpme.v4i03.38.

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Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have

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Dissertations / Theses on the topic "Modified Carry Select Adder (MCSLA)"

1

Allwin, Priscilla Sharon. "A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305.

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Book chapters on the topic "Modified Carry Select Adder (MCSLA)"

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Jujjuru, Jaya Lakshmi, and Rajanbabu Mallavarapu. "Improved SQRT Architecture for Carry Select Adder Using Modified Common Boolean Logic." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_36.

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Sakshi Bhatnagar, Harsh Gupta, and Swapnil Jain. "Modified D-Latch Enabled BEC1 Carry-Select Adder with Low Power-Delay Product and Area Efficiency." In Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing. Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2638-3_51.

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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core

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Conference papers on the topic "Modified Carry Select Adder (MCSLA)"

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Dinesh, S., and S. M. Ramesh. "Speed, area, power analysis of modified carry select adder with conventional carry select adder." In PHYSICAL MESOMECHANICS OF CONDENSED MATTER: Physical Principles of Multiscale Structure Formation and the Mechanisms of Nonlinear Behavior: MESO2022. AIP Publishing, 2023. http://dx.doi.org/10.1063/5.0144638.

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Abhiram, T., T. Ashwin, B. Sivaprasad, S. Aakash, and J. P. Anita. "Modified carry select adder for power and area reduction." In 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT). IEEE, 2017. http://dx.doi.org/10.1109/iccpct.2017.8074371.

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Kavipriya, P., S. Lakshmi, T. Vino, M. R. Ebenezar Jebarani, and G. Jegan. "Booth Multiplier Design Using Modified Square Root Carry-Select-Adder." In 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS). IEEE, 2021. http://dx.doi.org/10.1109/icais50930.2021.9396032.

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Paradhasaradhi, Damarla, M. Prashanthi, and N. Vivek. "Modified wallace tree multiplier using efficient square root carry select adder." In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE). IEEE, 2014. http://dx.doi.org/10.1109/icgccee.2014.6922214.

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Reddy, B. Ravikumar, and A. Krishna Mohan. "Implementation of 64-Bit ALU Using Modified Sqrt Carry Select Adder." In National Conference on Trends in Engineering and Technology. AI Publications, 2017. http://dx.doi.org/10.22161/ijaers/nctet.2017.52.

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Joy, Mary Christina, Ansa Jimmy, Tony C. Thomas, and Manju I. Kollannur. "Modified 16 bit Carry Select and Carry Bypass Adder Architectures for High Speed Operations." In 2020 IEEE International Conference for Innovation in Technology (INOCON). IEEE, 2020. http://dx.doi.org/10.1109/inocon50539.2020.9298435.

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Hepzibha, K. Golda, and C. P. Subha. "A novel implementation of high speed modified brent kung carry select adder." In 2016 10th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2016. http://dx.doi.org/10.1109/isco.2016.7727130.

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Ranjan, Abhay Kumar, Ompal Singh, and Sandip Nemade. "VLSI Architecture for Reversible Radix-2 FFT using Modified Carry Select Adder." In 2024 7th International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2024. http://dx.doi.org/10.1109/icdcs59278.2024.10560751.

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9

Mugilvannan, L., and S. Ramasamy. "Low-power and area-efficient carry select adder using modified BEC-1 converter." In 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT). IEEE, 2013. http://dx.doi.org/10.1109/icccnt.2013.6726499.

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Nautiyal, Priyanka, Pitchaiah Madduri, and Sonam Negi. "Implementation of an ALU using modified carry select adder for low power and area-efficient applications." In 2015 International Conference on Computer and Computational Sciences (ICCCS). IEEE, 2015. http://dx.doi.org/10.1109/iccacs.2015.7361316.

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