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1
Davis, Caitlin. "Sigma delta modulation at high temperature." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/mq64995.pdf.
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Galton, Ian Posner Edward C. Posner Edward C. "An analysis of quantization noise in delta sigma modulation and its application to parallel delta sigma modulation /." Diss., Pasadena, Calif. : California Institute of Technology, 1992. http://resolver.caltech.edu/CaltechETD:etd-07202007-150751.
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Lu, Albert K. (Albert Keishi). "Analog signal generation using delta-sigma modulation." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68040.
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This thesis introduces a method by which low-frequency analog waveforms may be generated using delta-sigma modulation. The technique centers around a delta-sigma based oscillator which, with the exception of a continuous-time low-pass filter, is entirely digital and provides precise control over the oscillation frequency, amplitude, and phase. The incorporation of a delta-sigma modulator inside the resonator loop leads to an efficient implementation requiring 4 multi-bit adders, 4 delay elements, and a 2-input multiplexer. Two additional circuits, which generate multi-tone and piece-wise linear waveforms, are presented as extensions of the original single-tone design.Prototypes of the proposed designs have been assembled using Field-Programmable Gate Array, and BiCMOS technologies. The test results have successfully verified the validity of the proposed concepts indicating dynamic ranges exceeding 80 dB and 60 dB for the single and multi-tone generators respectively.
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Filiol, Norman M. "Sigma-delta modulation for FM mobile radio." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ37063.pdf.
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Ushaw, Gary. "Sigma delta modulation of a chaotic signal." Thesis, University of Edinburgh, 1996. http://webex.lib.ed.ac.uk/homes/ushaw96.html.
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Filiol, Norman M. (Norman Maurice) Carleton University Dissertation Engineering Electronics. "Sigma-delta modulation for FM mobile radio." Ottawa, 1999.
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Haurie, Xavier. "Signal generation using high-order Delta-sigma modulation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=27224.
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This work presents high-order, arbitrary-band delta-sigma oscillators. They are a class of digital circuits which, augmented with a minimum of analog circuitry requiring no trimming, generate fully programmable, high-quality analog sinusoidal signals. A generalization of previous work, they can meet arbitrary signal-band and SNR specifications at a minimum digital hardware cost, and without the previously reported stability problems. It is shown that multitone generation requires but simple modifications to the basic oscillator topology; this signal generation scheme is thus highly attractive for endowing mixed-signal integrated circuits and systems with self-test capabilities. Delta-sigma oscillators can be useful in other applications as well.An essential building block of delta-sigma oscillators is a one-bit digital delta-sigma modulator with unity Signal-Transfer-Function. A complete, computer-aided design method, relying on a novel high-order modulator topology allowing the use of power-of-two coefficients, is formulated and justified. Although the resulting modulators are aimed specifically at usage in delta-sigma oscillators, they can find applications in oversampled D/A conversion in general as they require a minimal amount of digital hardware.
DSMOD is the computer-aided design tool which was developed to automate the design, simulation and prototyping processes. It implements a number of involved design algorithms, and allows for a quick comparison of theoretical, simulated and prototype behavior, with the use of a graphical user interface. It is written mostly for MATLAB and is thus highly portable and expandable.
The measurements performed on prototypes prove the soundness, flexibility and efficiency of DSMOD. They also prove that low hardware cost and high performance levels are attainable with the novel delta-sigma modulator and oscillator topologies presented here.
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Jantzi, Stephen A. "Quadrature bandpass delta-sigma modulation for digital radio." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ27669.pdf.
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Haurie, Xavier. "Signal generation using high-order delta-sigma modulation." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ29597.pdf.
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Chang, Tsung-Yuan. "Analysis and application of bandpass delta-sigma modulation /." The Ohio State University, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487952208109629.
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Al-Janabi, Mohammed. "Design, analysis and evaluation of bandpass sigma-delta modulators." Thesis, University of Westminster, 2000. https://westminsterresearch.westminster.ac.uk/item/94359/design-analysis-and-evaluation-of-bandpass-sigma-delta-modulators.
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Andersson, Tobias, and Johan Wahlsten. "Delta-Sigma Modulation Applied to Switching RF Power Amplifiers." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9449.
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Background:
The task of this thesis is to investigate the possibility of using non-linear high efficiency switching power amplifiers with spectrally efficient varying envelope modulation schemes and, if possible, further investigate such a solution on a high level.
The thesis focuses on the theory necessary to understand the technical issues related to power amplifiers and the procedures behind simulating and measuring the characteristics of different power amplifier configurations. The thesis also covers basic theory behind Delta-Sigma-modulators. The theory is needed to draw conclusions about the feasibility of using a Delta-Sigma-modulator as input to a switching amplifier.
Results:
Using a Delta-Sigma-modulated input to a switching amplifier inherently degrades the performance, mainly because of poor coding efficiency and high switching activity. However, by merely using a switching amplifier as a mixer it is shown to be possible to transmit a non-constant envelope signal, with digital logic. The resulting circuit is, however, not an amplifier and it should not be seen as the final result. As already mentioned: the result lies in the investigation of a using Delta-Sigma-modulator as input to a switching amplifier.
Conclusion:
From this investigation we believe that the widely known technique: pulse width modulation (PWM), together with a tuned switching amplifier and some linearization technique, for example pre-distortion, is a better way to go. Much effort should be put in understanding the fundamental limits and possibilities of an efficient tuned switching power amplifier.
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Esslinger, Rolf. "One-bit Sigma-Delta Modulation for digital power amplifiers." Thesis, University of Strathclyde, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.401393.
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Cai, Hao. "Fiabilisation de convertisseurs analogique-numérique à modulation Sigma-Delta." Thesis, Paris, ENST, 2013. http://www.theses.fr/2013ENST0046/document.
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Ce travail de thèse a porté sur des problèmes de fiabilité de circuits intégrés en technologie CMOS 65 nm, en particulier sur la conception en vue de la fiabilité, la simulation et l'amélioration de la fiabilité. Les mécanismes dominants de vieillissement HCI et NBTI ainsi que la variation du processus ont été étudiés et évalués quantitativement au niveau du circuit et au niveau du système. Ces méthodes ont été appliquées aux modulateurs Sigma-Delta afin de déterminer la fiabilité de ce type de composant qui est très utiliséThis thesis concentrates on reliability-aware methodology development, reliability analysis based on simulation as well as failure prediction of CMOS 65nm analog and mixed signal (AMS) ICs. Sigma-Delta modulators are concerned as the object of reliability study at system level. A hierarchical statistical approach for reliability is proposed to analysis the performance of Sigma-Delta modulators under ageing effects and process variations. Statistical methods are combined into this analysis flow
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Saine, Sheikh. "Using Delta-Sigma Modulation to characterise embedded analogue circuits." Thesis, University of Huddersfield, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.327141.
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The proliferation of products from the consumer electronics industry (especially the communications market) has led to increasing consumer demand for cheaper, smaller form factor, efficient and low power consumption products with high computation power. This growing demand for cheaper and more efficient products has made it more desirable for Integrated Circuit (IC) manufacturers to integrate both analogue and digital circuits on the same silicon substrate in order to realise high performance mixed-signal IC's at cost effective prices. The concomitant technology advancements in the IC manufacturing process, especially in the Complementary Metal Oxide Semiconductor (CMOS) process and improvements made in the capabilities of Computer-Aided Design (CAD) tools is making greater system integration possible. However, one aspect of the process that is the bottleneck of yet further system integration and lower design lead time is test. While the digital sections of mixed-signal IC's are taking microseconds to test using well established digital structural test techniques which exploit efficient Design for Test (DFT) structures, the analogue sections are still being tested using functional test methods and consequently consume several seconds of expensive test time. The work presented in this thesis addresses the test problems associated with the analogue sections of mixed-signal IC's. Specifically, the work was aimed at developing an efficient and unified embedded mixed-signal test system capable of being adopted for both analogue circuit characterisation and production testing of mixed-signal IC's in order to reduce overall test time and cost. In this context, an Analogue Test Response Compaction Technique (ATRCT) has been developed using Delta-Sigma Modulation (AIM). This compaction technique produces a signature for an analogue macro under test, which relates to both the amplitude and frequency of the analogue output response. Fault simulation results relating to a two-stage CMOS operational amplifier and continuous-time state variable filter have shown that fault-coverage of greater than 80% is attainable when the ATRCT is employed in a production testing of linear analogue macros. Based on the ATRCT, a hardware efficient Analogue Built-In Selt-Test (ABIST) scheme is proposed. This work has also developed two characterisation techniques suitable for embedded linear analogue macros: 1) An alternative hardware efficient method of measuring the impulse response of linear analogue macros using AIM, which could be conveniently incorporated in an ABIST scheme. Simulation results of the AIM-based impulse response measurement system have shown that the accuracy of the technique is within ±0.5% of the expected impulse responses. 2) An analogue fault detection routine that uses AIM and correlation techniques to detect analogue amplitude and frequency faults within linear analogue macros. Combining the proposed AIM-based impulse response measurement technique with the proposed ABIST scheme or analogue fault detection routine will enable an efficient and unified embedded mixed-signal test system to be designed.
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Bridgett, Nicholas Arthur. "Design and analysis of nonlinear sampled-data control systems." Thesis, Coventry University, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.303000.
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davoudzadeh, mahboub sedigh Nima. "optical engineer." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/894.
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In this research an approach to all optical delta sigma modulator (ADSM) has been elaborated. Two important components of ADSM; "leaky integrator" and "inverted bi-stable quantizer" were modeled, on the basis of cross gain modulation of the Semiconductor Optical Amplifier (SOA). The simulations (via VPI photonics) were all in micrometer scale (suitable for chip fabrication). By simulating each element of ADSM the whole circuit was simulated and results have been showed and analyzed. By investigating the ADSM, the limiting factor for reaching higher frequencies (THz) was recognized to be the quantization device. Thus a new optical switch was introduced, for the first time so called "proteresis." By applying proteretic bi-stable device in the delta sigma modulator, the resonance frequency was improved minimum two fold from 295MHz to 575MHz without making any change in hysteretic bi-stable switch. The broad impact of this research is on the digital technologies that can be utilized in high-speed signal processing. The prime examples are the RF technologies used in military and civilian applications. Furthermore introduction of proteresis opens a new research gate for compensating delay in almost every system.
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Bannwarth, Stephan [Verfasser]. "Robuste Sigma-Delta Wandler durch fs/2-Modulation / Stephan Bannwarth." München : Verlag Dr. Hut, 2014. http://d-nb.info/1049361873/34.
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Jerng, Albert. "Delta-Sigma digital-RF modulation for high data rate transmitters." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38675.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 157-162).
A low power, wideband wireless transmitter utilizing [Delta]-[Sigma] direct digital modulation of an RF carrier is presented. The transmitter architecture replaces high dynamic range analog circuits with high speed digital circuits and a passive LC bandpass filter, saving power and area compared to conventional IQ modulators for wideband systems. A prototype transmitter IC built in 0.13 pm CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. The modulator consumes 187 mW and occupies a die area of 0.72 mm2. A quadrature digital-IF approach eliminates modulator LO feedthrough and image spurs from the output spectrum without requiring analog circuitry or system calibration, simplifying the design of the transmitter. The largest modulator spur is measured to be -47 dBc. Measured SNDR over a 200 MHz bandwidth is 43 dB. Successful implementation of the [Delta]-[Sigma] RF modulator requires the design of a high-Q, tunable RF bandpass filter, and a low power, high speed digital [Delta]-[Sigma] modulator. A 4th order passive LC bandpass filter with center frequency of 5.25 GHz is designed and implemented using differential coupled resonators.
(cont.) Variation of the filter response over process and temperature is removed through the design of an automatic self-tuning loop that calibrates the filter center frequency to the system LO. A 2.625 GS/s, 2nd order, 3-bit digital [Delta]-[Sigma] modulator is realized through the use of a pass-gate adder circuit optimized for low power and high speed. The digital modulator is software programmable to support multiple bandwidths, frequency channels, and modulation schemes. It can be used adaptively to transmit in selected channels with variable bit-rates, depending on channel conditions. It is envisioned that the [Delta]-[Sigma] digital-RF modulator can be used as a universal transmitter for wideband systems and applications that require high data rates and low power consumption.
by Albert Jerng.
Ph.D.
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Lin, Lu. "Adaptive signal processing in subbands using sigma-delta modulation technique." Thesis, University of Ottawa (Canada), 1994. http://hdl.handle.net/10393/6532.
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In this thesis, the use of subbanding and sigma-delta modulation in interference/noise cancellation is intensively studied and a sigma-delta modulated subbanded adaptive interference/noise cancellation system is proposed. The filter bank is fully sigma-delta modulated. The output signal from the filter bank is then used to produce the input to the adaptive filter. The adaptive filter is partially sigma-delta modulated. The output is demodulated at the final stage. Maintaining the sigma-delta modulated signal representation throughout the system results in considerable savings in complexity. The performance of the proposed system is studied and compared to the regular non sigma-delta modulated case regarding complexity, convergence speed and steady state error. The effect of the oversampling rate used in the sigma-delta modulation as well as the quality of the demodulator is also considered. It is shown that in the case of interference cancellation a comb filter is sufficient, while in the case of noise canceller a good quality demodulator is essential. The thesis concludes by highlighting the tradeoffs between the hardware complexity reduction and the overall system performance.
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Zichy, Michael Andrew. "[Sigma Delta] Quantization with the hexagon norm in C /." Electronic version (PDF), 2006. http://dl.uncw.edu/etd/2006/zichym/michaelzichy.pdf.
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Ameri, Ali. "Time-mode reconstruction IIR filters for sigma-delta phase modulation applications." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104809.
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The design of several low-pass IIR time-mode filters for use as reconstruction filters in digital-to-time conversion (DTC) applications is proposed. Previously, such reconstruction filters were implemented using phase-locked loops. The proposed filters are constructed from a simple digital-like structure involving voltage-controlled delay units. The resulting circuits require very small silicon area and consume very little power. A first-order filter design for wideband reconstruction applications was fabricated in a 0.13 um CMOS process occupying a silicon area of 170 um x 100 um and consumes 670 uW. The results prove for the first time that the concept of time-mode filtering is feasible in a CMOS monolithic process. Another design, intended for narrowband sigma-delta phase signal generation applications, is proposed that utilizes similar building blocks but uses a filter topology that is better suited for implementations with transfer functions having low-frequency poles. High-order realizations can be constructed as a cascade of several first-order sections. Such an approach will be demonstrated in the design of a sigma-delta phase-encoding signal-generation scheme.Dans cette dissertation nous proposons plusieurs filtres IIF passe-bas qui opèrent en mode temps. Ces dispositifs sont conçus pour être utilisé comme filtres de reconstruction dans les convertisseurs numérique-temps (CNT). Dans le passé, de tels filtres ont été implémenté à partir de boucles à verrouillage de phase. Les filtres proposés dans cette thèse sont construits à partir d'une simple structure numérique impliquant des unités de retards commandés en tension. Les circuits résultant de cette approche requièrent de petites surfaces sur silicium et consomment très peu d'énergie. Un filtre du premier ordre pour les applications larges bandes a été fabriqué dans un processus CMOS 0.13 um. Le filtre occupe une surface de silicium de 170 um x 100 um et consomme 670 uW. Les résultats montrent pour la première fois que la notion de filtrage en mode temps est possible dans un processus CMOS monolithique. Un autre filtre destiné à des applications de génération de signal de phase sigma-delta à bande étroite est aussi proposé. Ce filtre utilise des blocs de construction similaire au premier mais utilise une topologie qui est mieux adapté pour les implémentations de fonctions de transfert ayant des pôles à forte valeur de Q. Les filtre d'ordre supérieur peuvent être construits en cascadant plusieurs filtres du premier ordre. Une telle approche sera démontrée par la conception d'un système de génération de signaux de phase codes en sigma-delta.
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Peev, Pavel. "An anti-aliasing filter based on continuous-time delta-sigma modulation." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86920.
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An anti-aliasing filter that incorporates a sampler is proposed. Its architecture is inspired by the anti-aliasing filtering property of continuous-time (CT) delta-sigma (DS) modulators. However, contrary to CT DS modulators, the proposed sampling anti-aliasing filter is not sensitive to clock jitter. Furthermore, its key characteristics include: 1) high suppression of aliases - for example, compared to a Butterworth filter of the same order - owing to its notches at multiples of the sampling frequency; 2) high-pass shaping of sampling errors, similar to the shaping of quantization noise in DS modulators; and 3) its alias suppression is preserved over a broad range of sampling frequencies, thereby enabling its use as a general-purpose intellectual property (IP) block. Thus, the proposed sampling anti-aliasing filter is particularly attractive at the input of noise-shaping analog-to-digital converters (ADCs), such as discrete-time (DT) DS ADCs. Its performance advantages are derived theoretically and confirmed through simulations.Un filtre anticrénelage qui incorpore un échantillonneur est proposé ci-après. Son architecture s'inspire des proprietés d'anticrénelage des modulateurs delta-sigma (DS) en temps continu (TS). Néanmoins, contrairement aux modulateurs DS TC, le filtre proposé n'est pas victime de la sensibilité au bruit d'horloge. De plus, ce filtre anticrénelage possède entre autres les qualités suivantes: 1) Réduction élevée des créneaux non désirés - en comparaison par exemple aux crénaux d'un filter Butterworth du même ordre - ceci grâce à la présence de points rejet dans le réponse du filtre aux multiples de la fréquence d'èchantillonnage; 2) Transformation passe-haut des erreurs d'échantillonnage, de façon similaire à la transfomation du bruit de quantification dans les modulateurs DS; 3) Préservation de la suppression des créneaux a travers une bande large de fréquences d'échantillonnage; ce qui en permet l'usage banalisé sous forme de block de propriété intellectuelle (PI). Ainsi, le filtre d'échantillonnage anticrénelage proposé ci-après est particulièrement adéquat à l'entrée de la transformation de bruit d'un convertisseur analogue-numérique (CAN) comme les CAN a temps discrets. La performance de ce filtre est dérivée de manière théorique et confirmée par des simulations.
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Zrilić, D., D. Skendzić, S. Pajavić, R. Ghorishi, F. Fu, and G. Kandus. "A Charge-Balancing Incremental Analog to Digital Converter for Instrumental Applications." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615013.
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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, NevadaA switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.
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Balasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.
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Kulchycki, Scott Douglas. "Continuous-time [sigma-delta] modulation for high-resolution, broadband A/D conversion /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Gao, Xi. "Digital RF-over-Fiber Links Based on Continuous-Time Delta Sigma Modulation." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1579018039888542.
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Khushk, Hasham Ahmed. "Modulateur sigma delta passe-haut et application dans la réception RF multistandards." Paris, Télécom ParisTech, 2009. https://pastel.hal.science/pastel-00006055.
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Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3. 84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamiqueIn this thesis, research has been carried out at various abstraction levels to optimize the High Pass(HP) ∆Σ modulator operation. A top-down approach is adopted to achieve this objective. Beginning with the RF receiver architecture, the newly created Fs/2 receiver is selected for its enhanced compatibility with HP ∆Σ modulator as compared to other state of the art receiver architectures namely zero-IF and low-IF receivers. After the receiver topology, the next level of design i-e ∆Σ modulator architecture is addressed. We propose a new second-order unity-STF architecture which is advantageous over other topologies in terms of complexity and performance. Since the second-order modulator is unable to provide the required performance, the cascaded or MASH structures for HP operation are explored. GMSCL(Generalized Multi-Stage Closed Loop) topology is chosen and a recently proposed technique is applied to linearise the feedback DAC. This technique eliminates the need of Dynamic Element Matching (DEM) and increases the dynamic range of the converter as well. Next, after a thorough comparative analysis, the best HP filter is chosen for this modulator. It has reduced power consumption, surface area and noise. Finally the proposed GMSCL HP architecture is validated in 65nm CMOS process. Much attention is given to the design of operational transconductance amplifier since it is the major building block of high pass filters and is the most power consuming element. The target applications are UMTS with 3. 84MHz conversion band at 80dB dynamic range and WiMAX with 25MHz bandwidth at 52dB dynamic range
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Neitola, M. (Marko). "Characterizing and minimizing spurious responses in Delta-Sigma modulators." Doctoral thesis, Oulun yliopisto, 2012. http://urn.fi/urn:isbn:9789514297496.
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Abstract Oversampling data converters based on Delta-Sigma modulation are a popular solution for modern high-resolution applications. In the design of digital-to-analog or analog-to-digital Delta-sigma converters there are common obstacles due to the difficulties on predicting and verifying their performance. Being a highly nonlinear system, a Delta-Sigma modulator’s (DSM) quantization noise and therefore the spurious tones are difficult to analyze and predict. Multi-bit DACs can be used to improve the performance and linearize the behavior of DSMs. However, this will give rise to the need for linearizing the multi-bit DAC. A popular DAC linearization method, data weighted averaging (DWA) shapes the DAC mismatch noise spectrum. There are many variants of DWA, for low-pass and band-pass DSMs. This thesis proposes a generalization which integrates a few published variants into one, broader DWA scheme. The generalization enables expanding the tone-suppression studies into a larger concept. The performance of one- or multibit DSMs is usually verified by simulations. This thesis proposes a simulation-based qualification (characterization) method that can be used to repeatedly verify and compare the performance of multibit DSM with a DAC mismatch shaping or scrambling scheme. The last contribution of this thesis is a very simple model for tonal behavior. The model enables accurate prediction of spurious tones from both DSMs and DWA-DACs. The model emulates the tone behavior by its true birth-mechanism: frequency modulation. The proposed prediction model for tone-behavior can be used for developing new tone-cancelation methods. Based on the model, a DWA linearization method is also proposedTiivistelmä Delta-Sigma modulaatio on suosituin tekniikka ylinäytteistävissä datan muuntimissa. Riippumatta toteutustarkoituksesta (analogia-digitaali- tai digitaali-analogia-muunnos), Delta-Sigma (DS) modulaatiossa on yleisesti tunnettuja käyttäytymisen ennustamiseen liittyviä ongelmia. Nämä ongelmat ovat peräisin modulaattorin luontaisesta epälineaarisuudesta: DS-muunnin on nimittäin vahvasti epälineaarinen takaisinkytketty systeemi, jonka harhatoistojen ennustaminen ja analysointi on erittäin hankalaa. Yksibittisestä monibittiseen DS-muuntimeen siirryttäessä muuntimen suorituskyky paranee, ja muuntimen kohinakäyttäytyminen on lineaarisempaa. Tämä kuitenkin kostautuu tarpeena linearisoida DS-muuntimen digitaali-analogia (D/A) muunnin. Tällä hetkellä tunnetuin linearisointimenetelmä on nimeltään DWA (data weighted averaging) algoritmi. Tässä työssä DWA:lle ja sen lukuisille varianteille esitellään eräänlainen yleistys, jonka avulla algoritmia voidaan soveltaa sekä alipäästö- että kaistanpäästö-DS-muuntimelle. Kuten tunnettua, DS-modulaattorin analyyttinen tarkastelu on raskasta. Yksi- ja monibittisten DS-muuntimien suunnitellun käyttäytymisen varmistaminen tapahtuukin yleensä simulointien avulla. Työssä esitetään simulointiperiaate, jolla voidaan kvalifioida (karakterisoida) monibittinen DS-muunnin. Tarkemmin, kvalifioinnin kohteena on DWA:n kaltaiset D/A -muuntimien linearisointimentelmät. Kyseessä on pyrkimys ennen kaikkea toistettavaan menetelmään, jolla eri menetelmiä voidaan verrata nopeasti ja luotettavasti. Tämän väitöstyön viimeinen kontribuutio on matemaattinen malli harhatoistojen syntymekanismille. Mallilla sekä DS-muunnoksen että DWA-D/A -muunnokseen liittyvät harhatoistot voidaan ennustaa tarkasti. Harhatoistot mallinnetaan yksinkertaisella havaintoihin perustuvalla FM-modulaatiokaavalla. Syntymekanismin mallinnus mahdollistaa DS-muuntimien ennustettavuuden ja täten auttaa harhatoiston kumoamismenetelmien kehittämistä. Työssä esitetään yksi matemaattisen mallin avulla kehitetty DWA-D/A -muunnoksen linearisointimenetelmä
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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
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Garcia, Julian. "Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95447.
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The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative.QC 20120528
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Abcarius, John 1972. "High-speed low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20898.
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As digital electronics becomes increasingly popular, the need for efficient data conversion to provide the link to our analog world grows all the more important. To sustain the current rate of technological advancement, the requirements on the data conversion systems are becoming more stringent. Wireless communication systems demand high speed, high performance analog-to-digital conversion front-ends. Furthermore, consumers demand quality electronics at low cost, which precludes the use of expensive analog processes.This thesis investigates the potential of DeltaSigma modulation techniques in addressing both of these issues through the design, implementation and experimentation of several prototype integrated circuits. Delta-Sigma modulation has recently become widely recognized for its ability to perform high performance data conversion without the use of high precision components. To extend these benefits to wireless applications, a novel eighth-order bandpass DeltaSigma modulator for A/D conversion will be presented. The modulator design is developed beginning at the signal processing level and realized in a 0.8mu BiCMOS process using the switched-capacitor (SC) technique. To address the cost issue, the design of a data conversion system based on the DeltaSigma modulation technique using an economical purely digital CMOS implementation is investigated. The distortion performance of experimental prototypes implemented using switched-capacitor (with capacitors realized using MOSFETs) and switched-current techniques is assessed.
This work therefore contributes to the ongoing drive to improve the performance and applicability of the DeltaSigma modulation technique in meeting modern-day data conversion needs.
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Abcarius, John. "High-speed/low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0027/MQ50588.pdf.
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Frappé, Antoine. "All-digital RF signal generation using delta-sigma modulation for mobile communication terminals." Lille 1, 2007. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2007/50376-2007-Frappe.pdf.
Full textAbstract:
Dans le cadre de la radio logicielle, un transmetteur numérique, basée sur la modulation delta-sigma, est proposé. Son architecture est construite autour de deux modulateurs delta-sigma passe-bas suréchantillonnés du 3ème ordre qui fournissent un signal multiplexé sur 1 bit à haute cadence, qui code directement le signal RF dans le domaine numérique. La séquence de sortie peut ensuite être appliquée à l'entrée d'un amplificateur de puissance commuté ayant une bonne efficacité. Le standard UMTS a été choisi comme exemple d'application et un générateur de signaux RF 1 bit à 7. 8Géch/s a été réalisé dans une technologie 90nm CMOS. Une arithmétique redondante comprenant des signaux complémentaires, une quantification de sortie non exacte et une évaluation anticipée de la sortie ont été implémentées pour parvenir à la cadence désirée. Une logique dynamique différentielle sur 3 phases d'horloge, générées par une DLL, a été utilisée au niveau circuit. Le circuit intégré du transmetteur prototype démontre une fonctionnalité complète jusqu'à une fréquence d'horloge de 4GHz, permettant ainsi d'atteindre une bande passante de 50MHz autour d'une fréquence porteuse de 1GHz. Si la bande image est utilisée, la fréquence d'émission peut être déplacée jusqu'à 3GHz. Avec une fréquence d'horloge de 2. 6GHz et un canal WCDMA de 5MHz modulé autour d'une fréquence porteuse à 650MHz, 53. 6dB d'ACLR sont obtenus pour une puissance de canal en sortie de -3. 9dBm. Pour la bande image (1. 95GHz), l'ACPR est de 44. 3dB pour une puissance maximale du canal en sortie de -15. 8dBm, ce qui rentre dans les spécifications UMTS. L'aire active du circuit est de 0. I5mm² et sa consommation de 69mW sous IV à cette fréquence.
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Šiška, Martin. "Impulzové modulace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220215.
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This work deals with the analysis of pulse modulation issues, work is divided into six chapters. The first chapter of the thesis deals with pulse modulations as a whole. It explains the concept of modulation, the distinction between analog and digital modulation, and there is the basic classification of pulse modulation done. The second chapter focuses on the issue of non-quantized pulse modulation. For each modulation belonging to this group is verbally and graphically explains the principle of its activities. In the third chapter, which is similar to the second chapter, the work focuses on quantized pulse modulation. Again, each of these modulations explained its basic principle. It is also in this chapter outlines the design models in Matlab-Simulink. The fourth chapter presents calculations and tables with calculated values needed for simulations. In the fifth chapter, a comparison waveforms. It contains a discussion about the dependence of modulation on their parameters, parameters of the input signal and the sampling frequency. In the final sixth chapter deals with the early design concepts and detailed diagrams for the production of demonstration products.
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Vrána, Jaroslav. "Kvadraturní zrcadlové banky filtrů se sigma-delta modulátory." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-233436.
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Dissertation thesis is focused on real digital signal processing by quadrature mirror digital filter banks. In the first part a dual channel quadrature mirror digital filter bank is described briefly. Mainly transfer functions for distorted subband signals are described. In the next part generalized sigma-delta modulator and its linear model are described. Subsequently the generalized sigma-delta modulator is used in decomposition part of quadrature mirror digital filter bank. Designed structure is analyzed. Two design method of transfer functions are designed for the structure on the basis of analysis results. The first method is suitable for hand-made design by intuitive distribution of zeros and poles. The second method is more suitable for computer design. It is iterative method based on correlation. Transfer functions for quadrature mirror digital filter bank with sigma-delta modulators design examples are also part of thesis. Application of designed structure of quadrature mirror digital filter bank can lead to bigger compression ration in lossy data compression.
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Jabbour, Chadi. "Conversion analogique numérique Sigma Delta reconfigurable à entrelacement temporel." Phd thesis, Télécom ParisTech, 2010. http://pastel.archives-ouvertes.fr/pastel-00609650.
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De nos jours, les systèmes de communications supportent un nombre croissant de normes radios dont les exigences en termes de bande et de vitesse sont diverses. Ceci rend la conception d'un convertisseur analogique numérique (CAN) unique convenant à toutes ces normes, une tache très problématique. La reconfigurabilité est une solution à ce problème, où la résolution serait échangée contre la bande passante. Les CANs Sigma Delta offrent un moyen facile d'effectuer cet échange en ajustant leur rapport de sur-échantillonnage. Cependant, ils ne sont adaptés pour les applications larges bandes. La parallélisation des CANs Sigma Delta surmonte ce problème et en plus augmente la reconfigurabilité du CAN. Dans ce travail, la conception d'un CAN Sigma Delta reconfigurable et parallèle est présentée. Sa reconfigurabilité permet de faire des échanges entre bande de conversion et résolution ainsi qu'entre consommation de puissance et bande de conversion. Ceci est possible grâce à un contrôle sur le nombre actifs de canaux, sur le rapport de sur-échantillonnage, sur la fréquence d'opération et sur l'ordre des modulateurs. Une nouvelle technique d'interpolation est également proposée. Elle permet de réduire les tailles des capacités et les contraintes sur le filtre anti-repliement. Un prototype du CAN a été fabriquée dans une technologie CMOS 65 nm. Il a été conçu pour satisfaire les exigences des normes GSM, UMTS, EDGE, DVB-T, WiFi et WiMax. Pour le scénario GSM/EDGE, le CAN a une résolution de 13 bits pour une consommation de 1.74 mW. Pour le reste des scénarios, les performances visées ne sont pas atteintes cependant la fonctionnalité a été testée avec succès.
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Boujelben, Sonia. "Etude et réalisation d'un convertisseur A/N d'architecture Sigma Delta à courants commutés." Bordeaux 1, 2001. http://www.theses.fr/2001BOR12479.
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La cellule mémoire S2I de courant peut être considérée comme un opérateur réalisant les fonctions d'inversion, de sommation et de retard. En se basant sur cet opérateur, il est possible de développer des architectures de circuits élémentaires (intégrateur. . . ). Le but de notre travail est de réaliser un modulateur Sigma Delta d'ordre deux à base d'une nouvelle architecture d'intégrateur différentiel doublement échantillonné, S2I. Dans un premier temps, on a modélisé la cellule mémoire S2I. La finalité du travail consiste a déterminer un modèle permettant d'étudier le comportement du modulateur Sigma Delta. Ensuite, on a intégré le modulateur sur le silicium en technologie AMS 0. 6um triple niveau de métal. Puis, les diverses mesures expérimentales ont été réalisées avec le système de caractérisation CANTEST. Dans une seconde étape, on a conçu la chaîne de décimation qui permet de restituer le signal délivré par le modulateur sur 13 bits à une fréquence proche de Nyquist. La simulation du filtre de décimation à été réalisée avec MATLAB puis sur le logiciel SPW (Signal Pocessing Workstation) qui est un outil de conception de système, le code VHDL est généré par compilation. La troisième partie de la thèse, consiste à tester toute la chaîne de conversion analogique numérique en rassemblant le modulateur et le filtre décimateur.
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Leong, Choon-Haw. "New architectures for high-order bandpass sigma-delta modulation in digital-to-analog converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0033/MQ50636.pdf.
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Park, Matthew (Matthew J. ). "An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33332.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.In title on t.p., [Sigma] and [Delta] appear as the upper-case Greek letters.
Includes bibliographical references (p. 87-89).
This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power.
by Matthew Park.
M.Eng.
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Aguirre, Paulo Cesar Comassetto de. "Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/105065.
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Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit.Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.
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Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.
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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs.QC 20150422
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Lahouli, Rihab. "Etude et conception de convertisseur analogique numérique large bande basé sur la modulation sigma delta." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0074/document.
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Les travaux de recherche de cette thèse de doctorat s’inscrivent dans le cadre de la conception d’unconvertisseur analogique-numérique (ADC, Analog-to-Digital Converter) large bande et à haute résolution afinde numériser plusieurs standards de communications sans fil. Il répond ainsi au concept de la radio logiciellerestreinte (SDR, Software Defined Radio). L’objectif visé est la reconfigurabilité par logiciel et l’intégrabilité envue d’un système radio multistandard. Les ADCs à sur-échantillonnage de type sigma-delta () s’avèrent debons candidats dans ce contexte de réception SDR multistandard en raison de leur précision accrue. Bien queleur bande passante soit réduite, il est possible de les utiliser dans une architecture en parallèle permettantd’élargir la bande passante. Nous nous proposons alors dans cette thèse de dimensionner et d’implanter unADC parallèle à décomposition fréquentielle (FBD) basé sur des modulateurs à temps-discret pour unrécepteur SDR supportant les standards E-GSM, UMTS et IEEE802.11a. La nouveauté dans l’architectureproposée est qu’il est programmable, la numérisation d’un signal issu d’un standard donné se réalise enactivant seulement les branches concernées de l’architecture parallèle avec des sous-bandes defonctionnement et une fréquence d’échantillonnage spécifiée. De plus, le partage fréquentiel des sous-bandesest non uniforme. Après validation du dimensionnement théorique par simulation, l’étage en bande de base aété dimensionné. Cette étude conduit à la définition d’un filtre anti-repliement passif unique d’ordre 6 et detype Butterworth, permettant l’élimination du circuit de contrôle de gain automatique (AGC). L’architectureFBD requière un traitement numérique permettant de combiner les signaux à la sortie des branches enparallèle pour reconstruire le signal de sortie finale. Un dimensionnement optimisé de cet étage numérique àbase de démodulation a été proposé. La synthèse de l’étage en bande de base a montré des problèmes destabilité des modulateurs . Pour y remédier, une solution basée sur la modification de la fonction detransfert du signal (STF) afin de filtrer les signaux hors bande d’intérêt par branche a été élaborée. Unediscontinuité de phase a été également constatée dans le signal de sortie reconstruit. Une solution deraccordement de phase a été proposée. L’étude analytique et la conception niveau système ont étécomplétées par une implantation de la reconstruction numérique de l’ADC parallèle. Deux flots de conceptionont été considérés, un associé au FPGA et l’autre indépendant de la cible choisie (VHDL standard).L’architecture proposée a été validée sur un FPGA Xilinx de type VIRTEX6. Une dynamique de 74 dB a étémesurée pour le cas d’étude UMTS, ce qui est compatible avec celle requise du standard UMTSThe work presented in this Ph.D. dissertation deals with the design of a wideband and accurate Analog-to-Digital Converter (ADC) able to digitize signals of different wireless communications standards. Thereby, itresponds to the Software Defined Radio concept (SDR). The purpose is reconfigurability by software andintegrability of the multistandard radio terminal. Oversampling (Sigma Delta) ADCs have been interestingcandidates in this context of multistandard SDR reception thanks to their high accuracy. Although they presentlimited operating bandwidth, it is possible to use them in a parallel architecture thus the bandwidth isextended. Therefore, we propose in this work the design and implementation of a parallel frequency banddecomposition ADC based on Discrete-time modulators in an SDR receiver handling E-GSM, UMTS andIEEE802.11a standard signals. The novelty of this proposed architecture is its programmability. Where,according to the selected standard digitization is made by activating only required branches are activated withspecified sub-bandwidths and sampling frequency. In addition the frequency division plan is non-uniform.After validation of the theoretical design by simulation, the overall baseband stage has been designed. Resultsof this study have led to a single passive 6th order Butterworth anti-aliasing filter (AAF) permitting theelimination of the automatic gain control circuit (AGC) which is an analog component. FBD architecturerequires digital processing able to recombine parallel branches outputs signals in order to reconstruct the finaloutput signal. An optimized design of this digital reconstruction signal stage has been proposed. Synthesis ofthe baseband stage has revealed modulators stability problems. To deal with this problem, a solution basedon non-unitary STF has been elaborated. Indeed, phase mismatches have been shown in the recombinedoutput signal and they have been corrected in the digital stage. Analytic study and system level design havebeen completed by an implementation of the parallel ADC digital reconstruction stage. Two design flows havebeen considered, one associated to the FPGA and another independent of the chosen target (standard VHDL).Proposed architecture has been validated using a VIRTEX6 FPGA Xilinx target. A dynamic range over 74 dB hasbeen measured for UMTS use case, which responds to the dynamic range required by this standard
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Frappé, Antoine. "Génération numérique de signaux RF pour les terminaux de communication mobile par modulation delta-sigma." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2007. http://tel.archives-ouvertes.fr/tel-00280968.
Full textAbstract:
Dans le cadre de la radio logicielle, un transmetteur numérique, basé sur la modulation ΔΣ, est proposé. Son architecture est construite autour de deux modulateurs ΔΣ passe-bas suréchantillonnés du 3ème ordre qui fournissent un signal multiplexé sur 1 bit à haute cadence, qui code directement le signal RF dans le domaine numérique. La séquence de sortie peut ensuite être appliquée à l'entrée d'un amplificateur de puissance commuté ayant une bonne efficacité.Le standard UMTS a été choisi comme exemple d'application et un générateur de signaux RF 1 bit à 7,8Géch/s a été réalisé dans une technologie 90nm CMOS. Une arithmétique redondante comprenant des signaux complémentaires, une quantification de sortie non exacte et une évaluation anticipée de la sortie ont été implémentées pour parvenir à la cadence désirée. Une logique dynamique différentielle sur 3 phases d'horloge, générées par une DLL, a été utilisée au niveau circuit.
Le circuit intégré du transmetteur prototype démontre une fonctionnalité complète jusqu'à une fréquence d'horloge de 4GHz, permettant ainsi d'atteindre une bande passante de 50MHz autour d'une fréquence porteuse de 1GHz. Si la bande image est utilisée, la fréquence d'émission peut être déplacée jusqu'à 3GHz. Avec une fréquence d'horloge de 2,6GHz et un canal WCDMA de 5MHz modulé autour d'une fréquence porteuse à 650MHz, 53,6dB d'ACLR sont obtenus pour une puissance de canal en sortie de -3,9dBm. Pour la bande image (1,95GHz), l'ACPR est de 44,3dB pour une puissance maximale du canal en sortie de -15,8dBm, ce qui rentre dans les spécifications UMTS. L'aire active du circuit est de 0,15mm² et sa consommation de 69mW sous 1V à cette fréquence.
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Chopp, Philip. "Frequency-translating delta-sigma modulation for bandpass analog-to-digital conversion of high- frequency signals." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110454.
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A traditional heterodyne receiver downconverts its input signal to one or more intermediate frequencies (IFs) before digitizing it at baseband. In a digital-IF receiver, the input signal is digitized directly at an IF using a bandpass analog-to-digital converter (ADC). Accordingly, the digital-IF receiver replaces the image-reject mixers and baseband filters of a heterodyne receiver with accurate and effcient digital functions, and therefore provides greater potential for reconfigurability. In order to maximize the advantages of a digital-IF receiver, a common design objective is to position the bandpass ADC as close as possible to the antenna, and to operate on the input signal at a high IF.A bandpass ADC is effciently implemented using a delta-sigma modulator, which can provide high-resolution A/D (analog-to-digital) conversion over a relatively narrow band around an IF. In order to operate on high-IF signals, conventional bandpass delta-sigma modulators require high-frequency filters and high sampling rates, which can result in high sensitivity to circuit non-idealities and high power consumption. These disadvantages are addressed by the frequency-translating delta-sigma modulator, which uses downconversion mixing inside its delta-sigma loop to process high-IF signals using low sampling rates and primarily low-frequency filters.This thesis investigates frequency-translating delta-sigma modulators for direct A/D conversion of high-IF signals. It first analyses the system architecture and performance limitations of an existing type of frequency-translating delta-sigma modulator that is based on image-reject mixing. This analysis is supported by an initial study on the effect of timing errors in a conventional delta-sigma modulator. The thesis then introduces a novel frequency-translating delta-sigma modulator that is based on single-path mixing. The advantages of the presented single-path architecture are demonstrated using an experimental delta-sigma modulator.The experimental delta-sigma modulator is designed to digitize a 4 MHz input-signal band that is centred at an IF of 225 MHz. It uses a local oscillation signal with a frequency of 200 MHz to downconvert this input-signal band to an IF of 25 MHz inside its delta-sigma loop, and samples at 100 MHz. The experimental prototype was fabricated in a standard 65 nm CMOS process. It achieves a peak SNDR of 55 dB and a dynamic range of 57.5 dB, while consuming 13 mW from a 1-V power supply. It has a full-scale range of 700 mVp-p.Un recepteur heterodyne traditionnel transpose un signal en entree vers une ou plusieurs frequences intermediaires (FI) avant de le numeriser a la bande de base. Dans un recepteur numerique FI, le signal en entree est numerise directement a la frequence FI a l'aide d'un convertisseur analogique-numerique passe-bande. Par consequent, le recepteur numerique FI remplace les melangeurs de rejection d'image et les filtres a bande de base d'un recepteur heterodyne traditionnel par des fonctions numeriques precises et efficaces. De ce fait, le recepteur numerique FI offre plus de possibilites de reconfiguration. Afin de maximiser les avantages d'un recepteur numerique FI, un objectif de conception frequent consiste a placer le convertisseur analogique-numerique passe-bande aussi pres que possible de l'antenne et de numeriser le signal en entree a une frequence FI elevee.Un convertisseur analogique-numerique passe-bande peut etre realise efficacement en utilisant un modulateur delta-sigma. En effet, ce dernier procure une conversion A/N (analogique-numerique) a haute resolution sur une bande relativement restreinte centree autour d'une frequence FI. Afin de fonctionner sur des signaux a frequences FI elevees, les modulateurs delta-sigma passe-bande classiques requierent des filtres hautes-frequences et des frequences d'echantillonnage elevees, ce qui peut les rendre tres sensibles aux non-idealites du circuit et mener a une consommation electrique importante. Il est possible de remedier a ces inconvenients en utilisant un modulateur delta-sigma a transposition de frequence. En effet, ce dernier utilise des melangeurs dans sa boucle delta-sigma pour traiter des signaux a frequence FI elevee a des frequences d'echantillonnage faibles avec principalement des filtres basses-frequences.Cette these etudie l'utilisation de modulateurs delta-sigma a transposition de frequence pour une conversion A/N directe de signaux a frequence FI elevee. Elle analyse d'abord l'architecture et les limitations de performance d'un modulateur delta-sigma a transposition de frequence base sur un melangeur de rejection d'image. Cette analyse est appuyee par une etude initiale effectuee sur l'effet d'erreurs d'horloge sur un modulateur delta-sigma classique. Cette these introduit ensuite un nouveau modulateur delta-sigma a transposition de frequence base sur un melangeur de mono-trajet. Les avantages de cette architecture sont demontres a l'aide d'un prototype de modulateur delta-sigma.Le prototype de modulateur delta-sigma est concu afin de numeriser une bande de signaux en entree de 4 MHz centree autour d'une FI de 225 MHz. Il utilise un signal a oscillation locale d'une frequence de 200 MHz pour transposer cette bande de signaux en entree vers 25 MHz a l'interieur de sa boucle delta-sigma et effectue l'echantillonnage a 100 MHz. Ce prototype a ete realise en utilisant un procede CMOS standard de 65 nm. Il a un SNDR de 55 dB et une gamme dynamique de 57.5 dB tout en consommant 13 mW pour une alimentation de 1-V. Sa plage d'amplitude maximale est de 700 mVp-p.
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Eriksson, Christer, and Erik Lindahl. "Design av FPGA-baserad PCM-till-PWM-modulator för klass D-audioförstärkare." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19488.
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I detta examensarbete har metoder för design av en FPGA-baserad PCM-till-PWM-modulator för klass D-audioförstärkare testats och utvärderats. Rapporten diskuterar med stöd av matematisk analys och simuleringar interpoleringsmetoder, pulsbreddsmodulering, samplingsprocesser och sigma-delta-modulatorer. Den föreslagna designen bygger på uppsampling, förkompensering, brusformning och pulsbreddsmodulering. Designens prestanda har verifierats genom simulering av modell och implementering i hårdvara.
This thesis experiments and evaluates methods for design of an FPGA based PCM-to-PWM modulator to be used in a class D audio amplifier. By utilizing mathematical analysis and simulations interpolation methods, pulse width modulation, cross point derivers and sigma delta modulators are discussed. The proposed design consists of upsampling, predistortion, noise shaping and pulse width modulation. The design has been validated through model based simulation and implementation in hardware.
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Kolesar, Joseph Dennis. "Sigma delta modulation and correlation criteria for the construction of finite frames arising in communication theory." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/1410.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2004.Thesis research directed by: Mathematics. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Ausiello, Ludovico <1979>. "Two-and-Three level representation of analog and digital signals by means of advanced sigma-delta modulation." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2009. http://amsdottorato.unibo.it/2184/.
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Pham, Dang Kien Germain. "Conversion analogique-numérique Sigma-Delta large bande appliquée à la mesure des non-linéarités des amplificateurs de puissance." Thesis, Paris, ENST, 2013. http://www.theses.fr/2013ENST0003/document.
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Les amplificateurs de puissance, éléments constitutifs essentiels de tout système de télécommunication, vont jouer un rôle capital dans le développement des futurs systèmes de communication. Aujourd'hui l'amélioration des amplificateurs de puissance nécessite un progrès technologique au niveau du composant lui même mais doit aussi tenir compte d'une approche plus globale. En particulier, le progrès dans les traitements numériques permet aujourd'hui de corriger en amont certaines distorsions qui seront générées en aval de la chaîne de communication. La pré-distorsion numérique est une technique de correction des amplificateurs de puissance qui connaît un intérêt grandissant de par son intégration complètement numérique et par les gains en linéarité et en consommation. Cette technique nécessite une voie de retour dont un élément critique est le convertisseur analogique-numérique. Ce composant doit répondre à des contraintes de résolution, de bande passante et de linéarité élevées. Dans cette thèse, nous proposons une nouvelle architecture de convertisseur analogique-numérique à base de modulateurs Sigma-Delta passe-bande. Cette architecture tire partie du fonctionnement passe bande des modulateurs que nous faisons travailler en parallèle, chacun centré sur différentes fréquences, mais aussi d'un agencement en cascade particulier pour éliminer le signal utile, qui est de forte puissance, dans le but de diminuer les contraintes de dynamique.La conception haut niveau et les simulations ont été menées pour des systèmes à temps discret et aussi à temps continu et a nécessité le développement d'outils adaptés de simulation se basant sur la boîte à outils Delta Sigma Toolbox de Richard SchreierPower amplifiers, which are essential elements of any communication system, will play a crucial role in the development of future communication systems. Today improving power amplifiers requires technological advances at the circuit device level, but one also must consider a more global approach. In particular, advances in digital processing can now correct in the early stage of the communication chain some distortions that are generated downstream in the chain. Digital pre-distortion is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and of its gains in linearity and energy consumption. This technique requires a feedback path where the analog-to-digital converter is a critical element. This component must satisfy the constraints of high resolution , wide bandwidth, and high linearity. In this thesis, we propose a new architecture of analog-to-digital converter based on bandpass Delta-Sigma modulators. This architecture takes advantage of operating bandpass modulators that are designed to work in parallel, each focusing on different frequencies, but also of a particular cascading arrangement to eliminate the useful signal, which has a high power, in order to reduce dynamics constraints. High-level design and simulations were carried out for discrete time and continuous time systems and also required the development of appropriate simulation tools
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Cheng, Yongjie. "Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1561.pdf.
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