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Longo, Lorenzo L. Carleton University Dissertation Engineering Electrical. "Multi-stage sigma delta modulators." Ottawa, 1988.
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Hussain, Arshad. "High-resolution passive and active-passive switched-capacitor delta-sigma modulator design techniques in nanoscale CMOS." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691845.
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Tam, Yiu-Ming. "A tri-mode sigma-delta modulator for wireless receivers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TAM.
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Chen, Zheng. "Very large scaled integrated circuit (VLSI) implementation of a high-speed delta-sigma analog to digital converter." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1177445405.
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Nathany, Sumit Kumar. "Design of a 14-bit fully differential discrete time delta-sigma modulator /." Online version of the thesis, 2006. https://ritdml.rit.edu/dspace/handle/1850/2799.
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Berglund, Krister, and Oskar Matteusson. "On the realization of switched-capacitor integrators for sigma-delta modulators." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10570.
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<p>The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive.</p><p>This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator.</p><p>The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system.</p><p>To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.</p>
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Zareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.
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The design of high-speed and high-resolution data converters is very difficult due to complexity of architectures used for converting analog signals into their digital representation. Since the introduction of the simplest conversion technique called parallel or flash technique numerous other architectures have been developed, for example n-stage pipeline, reference feed-forward architecture, folding and interpolating technique. The variety of A/D converter architectures additionally complicates design process due to fact that there is no available behavioral simulator, which can be utilized to support verification of particular converter's design. Many effects and imperfections present in A/D converters influence their performance, for example: switching imperfections, finite gain, clock jitter, and switching and coupling (Electro-Magnetic and substrate perturbations). In most cases several simulation tools have to be used to very performance of designed A/D converter. In this work a new methodology for behavioral simulation of A/D converters has been presented. Novel approach in behavioral modeling of A/D converters is based on utilization of Dynamic Linked Libraries (DLLs) to encapsulate behavior of basic modules of A/D converters. Predefined Basic Building Modules (BBMs) of A/D converters such as comparators, folding circuits, analog switches, binary encoders and many others are used to form a behavioral model of various types of A/D converters. Imperfections of BBMs are separated from the simulator framework and included into behavioral description of BBMs kept in DLL modules. Utilization of DLL modules gives a very convenient way for modifying BBMs independently from the simulator framework, and because DLL modules are executable files simulation time is significantly reduced (no translation or interpretation of simulation language commands is needed). Developed Behavioral Simulator of A/D converters is implemented in Visual C++ language and is partially based on an event driven simulation scheme and a data flow technique. The data flow technique was introduced into the simulator architecture to reduce number of events generated during simulation process, which additionally reduces simulation time. Several BBMs have been defined and constructed as DLL modules to support simulation of various types of A/D converters including flash, multi-stage, pipelined, and folding A/D converters.
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Louis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.
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Gustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.
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Javidan, Mohammad. "Design of high-order sigma-delta modulators for parallel analog-to-digital converters." Paris 11, 2009. http://www.theses.fr/2009PA112303.
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Les travaux menés se situent dans le contexte de la radio logicielle ou l'élément bloquant est le CAN. Une voie pour la réalisation de ce bloc, à savoir une structure EFBD, est proposé. Les différentes spécifications auxquelles un modulateur sigma-delta doit satisfaire dans ce système sont énumérés. Après avoir dressé un état de l'art des différentes technologies d'implantation du résonanteur (l'élément clé du modulateur), l'utilisation d'un résonateur à onde de Lamb est proposé. Un circuit de commande permettant la compensation de l'antirésonance et la réduction des impédances de connexions est présenté. Une méthode pour optimiser les performances de chaque modulateur en fonction des imperfections de l'électronique utilisée pour l'implémentation et en fonction de la fréquence centrale de chacun d'entre eux est développé. Il s'agit ici d'un travail conséquent et surtout nécessaire avant d'envisager la réalisation des modulateurs. Finalement la réalisation d'un modulateur d'ordre 2 est fait<br>This work is about design of convenient high-order continuous-time sigma-delta modulators for EFBD systems. Of all studied sorts of the resonators, Lamb wave resonators are chosen to obtain the required Q-factor. Also, solutions are proposed to overcome the issues of piezo-electique resonators. A new structure of 6th-order modulators based on weighted feedforward techniques is proposed. This structure provides moreover a filtering STF without modifying the NTF. An optimization method on the modifiable parameters of the proposed topology is developed to recover the performance of the modulator accounting analog imperfections. Finally, a second-order modulator is implemented to benchmark the proposed solutions
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Macedo, Marco. "Calibration and high speed techniques for CMOS analog-to- digital converters." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110482.
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The main focus of the work carried in this dissertation is to find the best design solution for an ultra high-speed Analog-to-Digital converter. Designing CMOS Analog-to-Digital converters in the gigahertz range for a good resolution is a challenge due to a lower power supply and smaller transistors. As a result, critical analog components (e.g., comparator, pre-amplifiers, band-gap) become more susceptible to process variation and make it hard to achieve a good resolution (e.g., higher than 6-bit). The traditional approach to design Analog-to-Digital converters does not work well with current CMOS technology and yields unpractical designs since it does not take advantage of the technology scaling down. For these reasons, this work investigates new designs topologies for the track-and-hold circuits needed at the front-end of ultra high-speed Analog-to- Digital converters and also investigates a digital foreground technique aimed at reducing the impact of process mismatch. For this purpose, two chips have been designed to investigate the best track-and-hold architecture based on a differential switch source-follower and to validate a proposed digital foreground calibration technique using resistive loads.<br>L'objectif de cette dissertation est de trouver la meilleure méthode de conception pour les convertisseurs de type analogique à digital. La conception de convertisseurs de type analogique à digital en CMOS qui soient capables de fournir une résolution élevée est un défi de taille à des fréquences très élevées comme les gigahertz, car en CMOS les sources de voltages sont très petites et les dimensions des transistors rendent les composantes analogues (e.g., comparateur, amplicateur, et references de voltage) de plus en plus susceptibles aux variations physiques et chimiques qui se produisent durant la fabrication des puces microélectroniques.Les méthodes traditionnelles de conception pour les convertisseurs de type analogique à digital ne sont plus a la hauteur pour fournir des convertisseurs capables d'une bonne resolution, car elles ne prennent pas avantage des percés technologiques qui ont été réalisées avec la diminution de la taille physique des transistors en CMOS. Par conséquent, le travail de recherche éffectué dans cette thèse consiste à étudier des nouvelles structures de circuits pour faire la conception de track-and-hold qui est necessaire au bon fonctionnement de convertisseurs analogique à digital de très hautes fréquences. De plus, une méthode de calibration digitale qui a pour objectif de corriger les défectuosités engendrées par la fabrication des puces microélectroniques est aussi proposée afin d'ameliorer la performance et la résolution des convertisseurs analogique à digital. Finalement, deux puces microélectroniques ont été fabriquées a des fins expérimentales pour démontrer la performance d'un nouveau track-and-hold ainsi que valider une nouvelle technique de calibration digitale de type foreground qui utilise des résistances.
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Taherzadeh-Sani, Mohammad. "Reconfigurable pipelined analog-to-digital converters in low -voltage nanometer CMOS." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114247.
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The growing demand for multi-mode/multi-standard wireless terminals is fuelling interest in analog-to-digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions. Furthermore, for power-efficiency, these ADCs must be power-scalable (i.e., their power scales with their bandwidth and resolution), thereby maintaining a constant figure-of-merit (FOM) over their entire reconfigurability space. Such reconfigurable power-scalable ADCs must be implemented in a standard digital CMOS process, for higher integration of the analog and digital functions in a communication system and for lower fabrication costs. However, in nanometer CMOS technologies, the decreasing supply voltages and the shrinking devices with poor analog-signal-processing capabilities, complicate the design of low-power ADCs. This thesis proposes a pipelined ADC that is reconfigurable over a continuous range of sampling frequencies fs = 0.4 to 44 MS/s (bandwidths BW = 0.2 to 22 MHz), and over resolutions N = 10, 11, 12 bits. Fabricated in a 1.2-V 90-nm digital CMOS process, it achieves low power (FOM = 0.35 to 0.5 pJ/conversion step) over its full bandwidth-resolution space. Thus, this ADC is suitable for multiple wireless and cellular standards, ranging from GSM up to LTE/WiMax and 802.11g. Furthermore, owing to its power efficiency, this ADC is attractive for various applications over a wide bandwidth-resolution space, thereby saving on development costs and reducing the time-to-market. Compared to the state-of-the-art power-efficient (FOM < 2 pJ/conversion step) reconfigurable pipelined or Delta-Sigma ADCs, this ADC provides a wide bandwidth-resolution reconfigurability space, while achieving a highly-competitive FOM over this entire space. For power scalability, the ADC bandwidth and resolution are reconfigured using current-scaling and stage-bypass methods, respectively. The following techniques are also introduced to achieve low-power performance for the ADC over its wide reconfigurability space, and to enable its implementation in low-voltage nanometer CMOS: 1) low-power digital background gain calibration to enable designing the ADC using low-gain/low-power opamps; 2) pseudo-cascode compensation for the low-power design of low-voltage current-scalable opamps; and 3) design of switched-capacitor dynamic comparators with low input loading.<br>La demande croissante de terminaux sans fil multimode et multistandard alimente l'intérêt pour des convertisseurs analogique-numérique (CAN) qui soient largement reconfigurables en terme de bande passante et de résolution. En outre, et pour des raisons d'efficacité énergétique, l'alimentation de ces CANs doit être modulable dans le but de maintenir une constante figure de mérite (FOM) dans tout l'espace de reconfigurabilité. Aussi, ces CANs doivent pouvoir être implémentés dans un technologie CMOS standard pour bénéficier d'un niveau d'intégration élevé de ses composants digitaux et analogiques ainsi qu'un plus faible cout de fabrication. Ceci dit, dans les technologies CMOS nanométriques, la diminution des tensions d'alimentation et la diminution de la taille des dispositifs sont des éléments contraignant la conception des CANs faible puissance. Cette thèse propose un CAN de type pipeline qui est reconfigurable sur une gamme continue de fréquences d'échantillonnage fs = 0.4 à 44 MS/s (bande passante de 0.2 à 22 MHz), pour les résolutions N = 10, 11, et 12 bits. Fabriqué dans une technologie digitale CMOS de 90-nm et 1.2-V, ce CAN est caractérisé par une faible consommation de puissance (FOM = 0.35 to 0.5 pJ/conversion step) sur tout son espace bande-resolution. Ainsi, ce CAN est approprié pour de multiples standards sans fil et cellulaire allant du GSM au LTE/iMax et 802.11g. Aussi, et en raison de son efficacité énergétique, ce CAN est attrayant pour diverses applications ce qui permet des économies de développements ainsi qu'une rapide mise sur le marché.Comparé à ce qui ce se fait aujourd'hui en terme d'efficacité énergétique (FOM < 2 pJ/conversion step), par exemple CAN de type pipeline ou Delta-Sigma, ce CAN offre un large espace de reconfiguration bande-resolution tout en réalisant un FOM hautement concurrentiel sur tout le dit espace. Pour varier la tension d'alimentation, la bande passante et la resolution du CAN sont reconfigurés en utilisant les méthodes dites de current-scaling et de stage-bypass respectivement. Les techniques suivantes sont également introduites pour obtenir des performances faible puissance dans l'espace de reconfigurabilite du CAN et permettre son implémentation dans une technologie CMOS nanométrique basse tension: 1) calibration digitale de gain type background pour permettre la conception du CAN à l'aide d'amplificateurs opérationnels faible gain et faible puissance; 2) compensation pseudo-cascode pour les amplificateurs opérationnels à courants variables; 3) la conception de comparateurs dynamiques type switch-cap à faible charge d'entrée.
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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.<br>The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.<br>This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.<br>These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.<br>The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
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Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.
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Hou, Xiaobo Rosen Warren A. Daryoush Afshin S. "A leaky waveguide all-optical analog-to-digital converter /." Philadelphia, Pa. : Drexel University, 2004. http://dspace.library.drexel.edu/handle/1860/437.
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Wong, Si Seng. "Design of analog-to-digital converters with binary search algorithm and digital calibration techniques." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493310.
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Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.
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This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, respectively, while the INL profile is 0.16LSB and 13LSBs for the first and second designs. The array is suited for applications requiring a set of digitally-controlled high-voltage signals.
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Leong, Choon-Haw. "New architectures for high-order bandpass sigma-delta modulation in digital-to-analog converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0033/MQ50636.pdf.
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
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A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.
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Early, Adrian Bruce. "A high-accuracy, DC-calibrated, monolithic, delta-sigma analog-to-digital converter." Diss., The University of Arizona, 1990. http://hdl.handle.net/10150/185072.
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Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, Delta-Sigma Analog-to-Digital converter in monolithic form. Autocalibration gives endpoint correction, and chopper stabilization minimizes the effect of parameter shifts, drift, and flicker noise. A digital filter, needed for all Delta-Sigma converters, serves as a signal processor to reject out-of-band noise and resonant responses of the external system. A 3-micron, double-poly CMOS process is used. Power requirements are +/- 5 Volts. A six-pole Gaussian IIR digital filter is chosen for good transient response and no overshoot. The filter algorithm and hardware solve the difference equations of a low-pass switched-capacitor prototype filter in digital form. Due to the low bandwidth needed, an area-efficient shift-and-add architecture is used. The area is further reduced with a novel multiplication algorithm, and the logic is reused to perform the calculations required for calibration. The system level device performance is verified in FORTRAN. The analog subcircuits are simulated over process and temperature corners in HSPICE. Measurements show differential and integral linearlity, DC accuracy and noise near the 20-bit level. Power supply rejection, and out-of-band signal attenuation are good, and the step response is monotonic. The circuit is marketed as Crystal Semiconductor CSC5503 and CSC5501 (20 and 16-bit resolutions, respectively).
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
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<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p><br>Report code: LiU-Tek-Lic-2005:68.
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Jalali, Farahani Bahar. "Adaptive digital calibration techniques for high speed, high resolution SIGMA DELTA ADCs for broadband wireless applications." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1133192371.
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Soell, Sven. "Theory and applications of delta-sigma analogue-to-digital converters without negative feedback." Thesis, Connect to e-thesis, 2008. http://theses.gla.ac.uk/369/.
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Thesis (Ph.D.) - University of Glasgow, 2008.<br>Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.
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Puidokas, Vytenis. "Design and Research on Sigma-Delta Digital-to-Analog Converters for Audio Power Amplifiers." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2011. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20111220_133108-90590.
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The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis.<br>Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objektas – skaitmeninis Sigma-Delta garso galios SA keitiklis, jo sandaros tobulinamas bei eksperimentinis tyrimas. Disertacijos tikslas – pasiūlyti skaitmeninio Sigma-Delta garso galios SA keitiklio interpoliatoriaus struktūros tobulinimo bei keitiklio tyrimo metodus.
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Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.
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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.
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Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.
Full textAbstract:
Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance.
The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18µ<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required.
A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control.
The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
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Dinc, Huseyin. "A high-speed two-step analog-to-digital converter with an open-loop residue amplifier." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39572.
Full textAbstract:
It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.
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Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.
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Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.
Full textAbstract:
Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacés<br>High speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized
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Kohnen, William. "A prototype investigation of a multi-GHz multi-channel analog transient recorder /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65462.
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Janse, van Rensburg HP. "Development of a digitising workstation for the electronics laboratory utilising the personal computer." Thesis, Cape Technikon, 1994. http://hdl.handle.net/20.500.11838/1081.
Full textAbstract:
Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1994<br>This thesis describes the design, development and
implementation of a digitising workstation for the
electronics laboratory that utilises the personal computer.
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.
Full textAbstract:
Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications.
Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL).
This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
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Hagerty, David Joseph. "Designing and Simulating a Multistage Sampling Rate Conversion System Using a Set of PC Programs." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4697.
Full textAbstract:
The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of the filter is normalized to accommodate filters that have a gain greater than one (as in the case of a lowpass filter used in an interpolator). We have also changed the input specifications from digital to analog. Thus, the user supplies the sampling rate, passband frequency, stopband frequency, gain, and the respective maximum band errors. The program converts the specifications to digital. Then, the program iteratively estimates the filter length and interacts with the McClellan-Parks Program to determine the actual filter length that minimizes the maximum band errors. Once the actual length is known, the filter is designed and the filter coefficients may be saved to a file. Another new finding that we present is the condition that determines when to add a lowpass filter to a multistage decimator in order to reduce the total number of filter taps required to implement the system. In a typical example, we achieved a 34% reduction in the total required number of filter taps. The third program is a new program that optimizes the design of a multistage sampling rate conversion system based upon the sum of weighted computational rates and storage requirements. It determines the optimum number of stages and the corresponding upsampling and downsampling factors of each stage of the design. It also determines the length of the required lowpass digital filters using the second program. Quantization of the filter coefficients may have a significant impact on the frequency response. Consequently, we have included a routine within our program that determines the effects of such quantization on the allowable error margins within the passband and stopband. Once the filter coefficients are calculated, they can be saved to files and used in an appropriate implementation. The only requirements of the user are the initial sampling rate, final sampling rate, passband frequency, stopband frequency, corresponding maximum errors for each band, and the weighting factors to determine the optimization factor. We also present another new program that implements a sampling rate conversion from CD (44.1 kHz) to DAT (48 kHz) for digital audio. Using the third program to design the filter coefficients, the fourth program converts an input sequence (either samples of a sine wave or a unit sample sequence) sampled at the lower rate to an output sequence sampled at the higher rate. The frequency response is then plotted and the output block may be saved to a file.
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Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.
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Volkmann, Mark Hans. "A superconducting software defined radio frontend with application to the Square Kilometre Array." Thesis, Stellenbosch : Stellenbosch University, 2013. http://hdl.handle.net/10019.1/85798.
Full textAbstract:
Thesis (PhD)-- Stellenbosch University, 2013.<br>ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a
better instrument. The largest radio telescope in the world will consist of
several arrays, the largest of which, consisting of more than 3000 dishes, will
be situated primarily in South Africa. The ambitions of the SKA are grand
and their realisation requires technology that does not exist today.
Current plans see signals in the band of interest ampli ed, channelised,
mixed down and then digitised. An all-digital frontend could simplify receiver
structure and improve its performance. Semiconductor (analog-to-digital converters)
ADCs continue to make great progress and will likely nd applications
in the SKA, but superconductor ADCs bene t from higher clock speeds
and quantum accurate quantisation. We propose a superconducting softwarede
ned radio frontend.
The key component of such a frontend is a superconducting
ash ADC.
We show that employing such an ADC, even a small- to moderately-sized one,
will signi cantly improve the instantaneous bandwidth observable by the SKA,
yet retain adequate signal-to-noise ratio so as to achieve a net improvement
in sensitivity. This improvement could approach factor 2 when compared to
conventional technologies (at least for continuum observations). We analyse
key components of such an ADC analytically, numerically and experimentally
and conclude that fabrication of such an ADC for SKA purposes is certainly
possible and useful.
Simultaneously, we address the power requirements of high-performance
computing (HPC). HPC on a hitherto unprecedented scale is a necessity for
processing the vast raw data output of the SKA. Utilising the ultra-low-energy
switching events of superconducting switches (certain Josephson junctions),
we develop rst demonstrators of the promising eSFQ logic family, achieving
experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the
applicability of the eSFQ design concept to arbitrary (unclocked) gates.<br>AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre
Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike
skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik
in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat
nog nie vandag bestaan nie.
Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer,
afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur
kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier
analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik
toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit
hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier
sagteware-gede nieerde radio kopstuk voor.
Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \
ash" ADO.
Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte,
die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal
verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n
netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke
met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum
waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities,
numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir
SKA doeleindes beide moontlik en nuttig is.
Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars
aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid
vir die verwerking van die enorme rou data uitset van die SKA. Deur
die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende
eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters
en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor
en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep
na arbitr^ere (ongeklokte) hekke uit te brei.
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Li, Bo. "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00782429.
Full textAbstract:
Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.
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"Chopper-stabilized high-pass delta-sigma modulators." 2011. http://library.cuhk.edu.hk/record=b5894824.
Full textAbstract:
Zhao, Yinsheng.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references (leaves 90-93).<br>Abstracts in English and Chinese.<br>ABSTRACT --- p.I<br>摘要 --- p.II<br>CONTENTS --- p.III<br>LIST OF FIGURES --- p.V<br>LIST OF TABLES --- p.VII<br>ACKNOWLEDGEMENT --- p.VIII<br>Chapter CHAPTER 1 --- INTRODUCTION --- p.1<br>Chapter 1.1 --- MOTIVATION --- p.1<br>Chapter 1.2 --- ORGANIZATION OF THE THESIS --- p.5<br>Chapter CHAPTER 2 --- BASIC THEOREMS OF DELTA SIGMA ADC --- p.6<br>Chapter 2.1 --- INTRODUCTION TO SAMPLING TECHNIQUE --- p.6<br>Chapter 2.2 --- DELTA-SIGMA ORDER & NOISE-SHAPING ORDER --- p.8<br>Chapter 2.2.1 --- FIRST ORDER CLELTA-SIGMA MODULATOR --- p.8<br>Chapter 2.2.2 --- HIGH ORDER DELTA-SIGMA MODULATOR --- p.11<br>Chapter 2.3 --- CHOPPER-STABILIZATION TECHNIQUE --- p.13<br>Chapter 2.4 --- MIRRORED INTEGRATOR --- p.16<br>Chapter 2.5 --- PERFORMANCE METRICS --- p.18<br>Chapter 2.5.1 --- SIGNAL TO NOISE RATIO (SNR) --- p.18<br>Chapter 2.5.2 --- SIGNAL TO NOISE AND DISTORTION RATIO (SNDR) --- p.19<br>Chapter 2.5.3 --- DYNAM IC RANGE --- p.19<br>Chapter 2.5.4 --- EFFECTIVE NUMBER OF BITS --- p.19<br>Chapter 2.5.5 --- "OVERLOAD LEVER, XOL" --- p.19<br>Chapter 2.6 --- CONCLUSION --- p.20<br>Chapter CHAPTER 3 --- NON-IDEALITIES IN SYSTEM MODELING --- p.21<br>Chapter 3.1 --- CLOCK JITTER --- p.21<br>Chapter 3.2 --- NON-IDEAL EFFECT OF OPERATIONAL AMPLIFIER --- p.23<br>Chapter 3.2.1 --- FINITE OPEN-LOOP GAIN --- p.23<br>Chapter 3.2.2 --- FINITE BANDWIDTH AND SLEW-RATE --- p.24<br>Chapter 3.3 --- CAPACITOR RATIO ERROR --- p.26<br>Chapter 3.4 --- THERMAL NOISE --- p.27<br>Chapter 3.5 --- SWITCH CHARGE INJECTION ERROR --- p.30<br>Chapter 3.6 --- CONCLUSION --- p.34<br>Chapter CHAPTER 4 --- A CHOPPER-STABILIZED HIGH-PASS DELTA-SIGMA MODULATOR IN 1.8V 0.18MM CMOS --- p.35<br>Chapter 4.1 --- STRUCTURE SELECTION --- p.35<br>Chapter 4.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.38<br>Chapter 4.3 --- CIRCUIT IMPLEMENTATION --- p.42<br>Chapter 4.3.1 --- OPERATIONAL AMPLIFIER --- p.42<br>Chapter 4.3.2 --- QUANTIZER --- p.44<br>Chapter 4.3.3 --- FREQUENCY DIVIDER --- p.47<br>Chapter 4.3.4 --- OVERALL CIRCUIT --- p.48<br>Chapter 4.4 --- LAYOUT IMPLEMENTATION --- p.50<br>Chapter 4.4.1 --- LAYOUT SYMMETRIC TECHNIQUE --- p.50<br>Chapter 4.4.2 --- CIRCUIT LAYOUT --- p.53<br>Chapter 4.4.3 --- FLOOR PLANNING AND TOP LEVEL INTER-CONNECT!ON --- p.56<br>Chapter 4.5 --- MEASUREMENT RESULTS --- p.58<br>Chapter CHAPTER 5 --- A LOW-POWER CHOPPER-STABILIZED DELTA-SIGMA MODULATOR IN 1.2V0.18MM CMOS --- p.63<br>Chapter 5.1 --- STRUCTURE SELECTION --- p.63<br>Chapter 5.2 --- SYSTEM MODELING AND PARAMETER SELECTION --- p.67<br>Chapter 5.3 --- CIRCUIT IMPLEMENTATION --- p.70<br>Chapter 5.3.1 --- OPERATIONAL AMPLIFIER --- p.70<br>Chapter 5.3.2 --- QUANTIZER --- p.73<br>Chapter 5.3.3 --- LARGE DELAY GENERATION --- p.73<br>Chapter 5.3.4 --- OVERALL CIRCUIT --- p.75<br>Chapter 5.4 --- SIMULATION RESULTS --- p.77<br>Chapter CHAPTER 6 --- DECIMATION FILTER DESIGN --- p.79<br>Chapter 6.1. --- THE WHOLE VIEW OF DECIMATION FILTER --- p.79<br>Chapter 6.2. --- THE DECIMATION FILTER IN SIMULINK --- p.80<br>Chapter 6.2.1 --- SINE FILTER DESIGN --- p.80<br>Chapter 6.2.2 --- HALF-BAND FILTER DESIGN --- p.82<br>Chapter CHAPTER 7 --- CONCLUSIONS AND FUTURE WORKS --- p.88<br>Chapter 7.1. --- CONCLUSIONS --- p.88<br>Chapter 7.2. --- FUTURE WORKS --- p.89<br>REFERENCES --- p.90<br>PUBLICATION --- p.93
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Lin, Haiqing. "Multi-bit delta-sigma switched-capacitor DACs employing element-mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33995.
Full textAbstract:
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital and digital-to-analog converters (ADCs and DACs). Most
delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback,
the use of multi-bit quantization would improve a delta-sigma modulator's performance
by increasing the modulator's resolution or increasing the modulators's bandwidth, while
at the same time whitening the quantization noise and improving modulator stability. This
thesis explores the element-mismatch-shaping technique, which attenuates the noise
caused by static element mismatch in a multi-level DAC by a method similar to delta-sigma
modulation.
Existing element-matching techniques are reviewed and some analytical and
architectural work related to the realization of mismatch-shaping logic is presented. A
custom switched-capacitor (SC) DAC is used to verify various element mismatch-shaping
algorithms. Experiments show that mismatch-shaping can reduce harmonic distortion
by up to 30 dB.<br>Graduation date: 1998
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Gao, Xiaoran. "A survey on continuous-time [delta sigma] modulators : theory, designs and implementations /." 2008. http://hdl.handle.net/1957/8386.
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Shui, Tao 1969. "Lowpass and bandpass current-mode delta-sigma DACs employing mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33910.
Full textAbstract:
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
These oversampled data converters have several advantages over conventional Nyquist-rate
converters, including an insensitivity to many analog component imperfections, a
simpler antialiasing filter and reduced accuracy requirements in the sample and hold. A
recent development in the realm of delta-sigma-based ADC and DAC systems is the use of
multilevel (as opposed to binary) quantization. This development owes its existence to the
discovery of a variety of techniques which cause linearity errors of the embedded
multilevel DAC to be attenuated in the frequency band of interest.
This thesis presents several methods for shaping the DAC element mismatch error
and reducing the dynamic error in the band of interest. To demonstrate the effectiveness of
the proposed algorithms, a current-mode unit element DAC is designed and used as a test
bed. Both theoretical analysis and experimental results show that these methods can
greatly attenuate the noise in the band of interest. The methods presented in this thesis will
allow high performance, high-frequency wideband delta-sigma modulators to be constructed.<br>Graduation date: 1998
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Dalal, Vineet R. "A switched-current bandpass delta-sigma modulator." Thesis, 1993. http://hdl.handle.net/1957/35637.
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Lee, Sang Hyeon. "High efficiency wideband low-power delta-sigma modulators." Thesis, 2012. http://hdl.handle.net/1957/30022.
Full textAbstract:
Delta-sigma analog-to-digital converters traditionally have been used for low speed, high
resolution applications such as measurements, sensors, voice and audio systems.
Through continued device scaling in CMOS technology and architectural and circuit
level design innovations, they have even become popular for wideband, high
dynamic range applications such as wired and wireless communication systems.
Therefore, power efficient wideband low power delta-sigma data converters that bridges
analog and digital have become mandatory for popular mobile applications today.
In this dissertation, two architectural innovations and a development and
realization of a state-of-the-art delta-sigma analog to digital converter with effective design
techniques in both architectural and circuit levels are presented. The first one is
timing-relaxed double noise coupling which effectively provides 2nd order noise
shaping in the noise transfer function and overcomes stringent timing requirement
for quantization and DEM. The second one presented is a noise shaping SAR
quantizer, which provides one order of noise shaping in the noise transfer function.
It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion
delta-sigma modulator which is suitable for adopting SAR quantizer.
Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for
WLAN applications is presented. It uses a noise folding free double sampling
technique and an improved low-distortion architecture with an embedded-adder
integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm
CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz
bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27
pJ/conv-step. The measurement results indicate that the proposed design ideas are
effective and useful for wideband, low power delta-sigma analog-to-digital converters with
low oversampling ratio.<br>Graduation date: 2012<br>Access restricted to the OSU Community at author's request from June 19, 2012 - June 19, 2013
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da, Silva Jose Barreiro. "High-performance delta-sigma analog-to-digital converters." Thesis, 2004. http://hdl.handle.net/1957/29846.
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Yang, Yaohua 1969. "Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators." Thesis, 1993. http://hdl.handle.net/1957/36354.
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Zhang, Bo. "Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs." Thesis, 1996. http://hdl.handle.net/1957/34675.
Full textAbstract:
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital and digital-to-analog converters. These oversampled data
converters have several advantages over conventional Nyquist-rate converters, including
an insensitivity to many analog component imperfections, a simpler antialiasing filter and
reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma
modulators were in the audio field, the development of bandpass modulators opened
up the application range to radar systems, digital communication systems and instruments
which convert IF, or even RF, analog signals directly to digital form.
This thesis presents a method used to analyze and synthesize continuous-time
delta-sigma modulators for given specifications. A fourth-order prototype continuous-time
bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on
a PCB board and measurement results corroborate the theory. To allow the construction of
very high performance delta-sigma modulators, this thesis presents an architecture for a
multibit DAC constructed from unit elements which shapes element mismatches. Theoretical
analysis and simulation shows that this architecture greatly increases the noise attenuation
in the band-of-interest and facilitates the use of multibit quantization in delta-sigma
modulators. The methods presented in this thesis will allow high-frequency wideband
bandpass delta-sigma modulators to be constructed.<br>Graduation date: 1996
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Guo, Yuhua. "A study of basic building blocks of analog-to-digital delta-sigma modulators." Thesis, 2004. http://hdl.handle.net/1957/30047.
Full textAbstract:
In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is
proposed, which can settle much faster than regular switch-capacitor integrators. A
new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also
introduced, which can effectively spread or shape the nonlinearity error of multi-bit
DAC in the feedback path, thus improve the SNDR and THD performance of overall
delta-sigma modulators. A three-bit quantizer design example is presented, which is
embedded in a MASH2-0 structure delta-sigma modulator prototype and has been
fabricated in AMI CMOS 1.5μm technology. Testing results indicate this quantizer
works well.<br>Graduation date: 2004
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Rajaee, Omid. "Design of low OSR, high precision analog-to-digital converters." Thesis, 2010. http://hdl.handle.net/1957/19654.
Full textAbstract:
Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from
the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.<br>Graduation date: 2011
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"Design techniques for low voltage wideband delta-sigma modulator." Thesis, 2010. http://library.cuhk.edu.hk/record=b6074846.
Full textAbstract:
Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced.<br>Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the amplifier's inputs for this type of modulators. Simulation results show that it improves the modulator's SNDR by 11%.<br>In this thesis, we present research works on developing a low-voltage delta-sigma modulator with a wide signal bandwidth. Specifically, a 0.5V complex low-pass continuous-time (CT) third-order delta-sigma modulator that has a single-sided signal bandwidth of 1MHz, targeting for application in Bluetooth receivers, is presented without using any internal voltage boosting techniques which are potentially harmful to the reliability of the device. The wide bandwidth of the modulator at this low supply voltage is enabled by a special common-mode (CM) level arrangement in the system level and by new low-voltage amplifies. Realized in a 0.13mum CMOS process the proposed modulator achieves a 61.9-dB peak signal-to-noise-and-distortion ratio at the nominal supply of 0.5V with 3.4mW consumption, and occupies an active area of 0.9mm2. The modulator achieves the best figure-of-merit among its class.<br>The development of low-voltage design techniques for analog circuits has recently received a lot of attention due to the continuous shrinking of the supply voltage in modern CMOS technologies, which is projected to reduce to 0.5V for low power applications within ten years in the International Technology Roadmap for Semiconductor. This thesis focuses on developing circuit techniques for low-voltage delta-sigma modulator, a functional block that is widely used in mixed-signal integrated circuits. Several delta-sigma modulators operating at supply voltages below 0.9V have been reported in the open literature. However, none of them supports a signal bandwidth wider than 100kHz with a reasonable performance.<br>He, Xiaoyong.<br>Adviser: Kong Pang Pun.<br>Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: .<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2010.<br>Includes bibliographical references (leaves 104-111).<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Abstract also in Chinese.
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Yang, Yuqing Ph D. "System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications." 2008. http://hdl.handle.net/2152/18176.
Full textAbstract:
As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challenges to achieve power efficiency and cost targets for modern day high precision converter design. The main goal of this work is to study various approaches and then propose and validate the most suitable topology to achieve the desired performance and power efficiency specifications, up to 100 kHz bandwidth with 16-21 bits of resolution. This work will first study various analog-to-digital conversion architectures ranging from Nyquist converters such as flash, pipeline, to the delta sigma architecture. Advantages and limitations of each approach will be compared to develop the criteria for the optimal modulator architecture. Second, this work will study analog sub-circuit blocks such as opamp, comparator and reference voltage generator, to compare the advantages and limitations of various design approaches to develop the criteria for the optimal analog sub circuit design. Third, this work will study noise contributions from various sources such as thermal noise, flicker noise and coupling noise, to explore alternative power and die area efficient approaches to suppress the noise. Finally, a new topology will be proposed to meet all above criteria and adopt the new noise suppression concepts, and will be demonstrated to be the optimal approach. The main difference between this work from previous ones is that current work places emphasis on the integration of the modulator architecture design and analog sub-circuit block research efforts. A high performance stereo analog-to-digital modulator is designed based on the new approach and manufactured in silicon. The chip is measured in the lab and the measurement results reported in the dissertation.<br>text