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Dissertations / Theses on the topic 'Modulators (Electronics) Digital-to-analog converters'

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Published: 4 June 2021

Last updated: 7 February 2022

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1

Longo, Lorenzo L. Carleton University Dissertation Engineering Electrical. "Multi-stage sigma delta modulators." Ottawa, 1988.

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2

Hussain, Arshad. "High-resolution passive and active-passive switched-capacitor delta-sigma modulator design techniques in nanoscale CMOS." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691845.

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3

Tam, Yiu-Ming. "A tri-mode sigma-delta modulator for wireless receivers /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TAM.

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4

Chen, Zheng. "Very large scaled integrated circuit (VLSI) implementation of a high-speed delta-sigma analog to digital converter." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1177445405.

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5

Nathany, Sumit Kumar. "Design of a 14-bit fully differential discrete time delta-sigma modulator /." Online version of the thesis, 2006. https://ritdml.rit.edu/dspace/handle/1850/2799.

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6

Berglund, Krister, and Oskar Matteusson. "On the realization of switched-capacitor integrators for sigma-delta modulators." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10570.

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<p>The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive.</p><p>This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator.</p><p>The first activity is to scale the inputs to each integrator in order to make sure that the produce

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7

Zareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.

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The design of high-speed and high-resolution data converters is very difficult due to complexity of architectures used for converting analog signals into their digital representation. Since the introduction of the simplest conversion technique called parallel or flash technique numerous other architectures have been developed, for example n-stage pipeline, reference feed-forward architecture, folding and interpolating technique. The variety of A/D converter architectures additionally complicates design process due to fact that there is no available behavioral simulator, which can be utilized t

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8

Louis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.

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9

Gustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.

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10

Javidan, Mohammad. "Design of high-order sigma-delta modulators for parallel analog-to-digital converters." Paris 11, 2009. http://www.theses.fr/2009PA112303.

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Les travaux menés se situent dans le contexte de la radio logicielle ou l'élément bloquant est le CAN. Une voie pour la réalisation de ce bloc, à savoir une structure EFBD, est proposé. Les différentes spécifications auxquelles un modulateur sigma-delta doit satisfaire dans ce système sont énumérés. Après avoir dressé un état de l'art des différentes technologies d'implantation du résonanteur (l'élément clé du modulateur), l'utilisation d'un résonateur à onde de Lamb est proposé. Un circuit de commande permettant la compensation de l'antirésonance et la réduction des impédances de connexions e

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11

Macedo, Marco. "Calibration and high speed techniques for CMOS analog-to- digital converters." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110482.

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The main focus of the work carried in this dissertation is to find the best design solution for an ultra high-speed Analog-to-Digital converter. Designing CMOS Analog-to-Digital converters in the gigahertz range for a good resolution is a challenge due to a lower power supply and smaller transistors. As a result, critical analog components (e.g., comparator, pre-amplifiers, band-gap) become more susceptible to process variation and make it hard to achieve a good resolution (e.g., higher than 6-bit). The traditional approach to design Analog-to-Digital converters does not work well with current

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12

Taherzadeh-Sani, Mohammad. "Reconfigurable pipelined analog-to-digital converters in low -voltage nanometer CMOS." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114247.

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The growing demand for multi-mode/multi-standard wireless terminals is fuelling interest in analog-to-digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions. Furthermore, for power-efficiency, these ADCs must be power-scalable (i.e., their power scales with their bandwidth and resolution), thereby maintaining a constant figure-of-merit (FOM) over their entire reconfigurability space. Such reconfigurable power-scalable ADCs must be implemented in a standard digital CMOS process, for higher integration of the analog and digital functions in a communicat

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13

Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.

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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.<br>The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.<br>This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadma

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14

Strak, Adam. "Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, Stockholm : Elektronik, dator- och programvarusystem Electronic, Computer, and Software Systems, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4243.

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15

Hou, Xiaobo Rosen Warren A. Daryoush Afshin S. "A leaky waveguide all-optical analog-to-digital converter /." Philadelphia, Pa. : Drexel University, 2004. http://dspace.library.drexel.edu/handle/1860/437.

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16

Wong, Si Seng. "Design of analog-to-digital converters with binary search algorithm and digital calibration techniques." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493310.

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17

Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.

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This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, r

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18

Leong, Choon-Haw. "New architectures for high-order bandpass sigma-delta modulation in digital-to-analog converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0033/MQ50636.pdf.

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19

Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.

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A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivato

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20

Early, Adrian Bruce. "A high-accuracy, DC-calibrated, monolithic, delta-sigma analog-to-digital converter." Diss., The University of Arizona, 1990. http://hdl.handle.net/10150/185072.

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Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, D

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21

Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.

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<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled

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22

Jalali, Farahani Bahar. "Adaptive digital calibration techniques for high speed, high resolution SIGMA DELTA ADCs for broadband wireless applications." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1133192371.

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23

Soell, Sven. "Theory and applications of delta-sigma analogue-to-digital converters without negative feedback." Thesis, Connect to e-thesis, 2008. http://theses.gla.ac.uk/369/.

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Thesis (Ph.D.) - University of Glasgow, 2008.<br>Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.

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24

Puidokas, Vytenis. "Design and Research on Sigma-Delta Digital-to-Analog Converters for Audio Power Amplifiers." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2011. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20111220_133108-90590.

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The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis.<br>Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objekt

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25

Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.

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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The

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26

Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.

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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achiev

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27

Dinc, Huseyin. "A high-speed two-step analog-to-digital converter with an open-loop residue amplifier." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39572.

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It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifi

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28

Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.

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29

Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.

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Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (

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30

Kohnen, William. "A prototype investigation of a multi-GHz multi-channel analog transient recorder /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65462.

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31

Janse, van Rensburg HP. "Development of a digitising workstation for the electronics laboratory utilising the personal computer." Thesis, Cape Technikon, 1994. http://hdl.handle.net/20.500.11838/1081.

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Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1994<br>This thesis describes the design, development and implementation of a digitising workstation for the electronics laboratory that utilises the personal computer.

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32

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

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33

Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analo

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34

Hagerty, David Joseph. "Designing and Simulating a Multistage Sampling Rate Conversion System Using a Set of PC Programs." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4697.

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The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula

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35

Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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36

Volkmann, Mark Hans. "A superconducting software defined radio frontend with application to the Square Kilometre Array." Thesis, Stellenbosch : Stellenbosch University, 2013. http://hdl.handle.net/10019.1/85798.

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Thesis (PhD)-- Stellenbosch University, 2013.<br>ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a better instrument. The largest radio telescope in the world will consist of several arrays, the largest of which, consisting of more than 3000 dishes, will be situated primarily in South Africa. The ambitions of the SKA are grand and their realisation requires technology that does not exist today. Current plans see signals in the band of interest ampli ed, channelised, mixed down and then digitised. An all-digital frontend could simplify receiver str

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37

Li, Bo. "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00782429.

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Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédicti

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38

"Chopper-stabilized high-pass delta-sigma modulators." 2011. http://library.cuhk.edu.hk/record=b5894824.

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Zhao, Yinsheng.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references (leaves 90-93).<br>Abstracts in English and Chinese.<br>ABSTRACT --- p.I<br>摘要 --- p.II<br>CONTENTS --- p.III<br>LIST OF FIGURES --- p.V<br>LIST OF TABLES --- p.VII<br>ACKNOWLEDGEMENT --- p.VIII<br>Chapter CHAPTER 1 --- INTRODUCTION --- p.1<br>Chapter 1.1 --- MOTIVATION --- p.1<br>Chapter 1.2 --- ORGANIZATION OF THE THESIS --- p.5<br>Chapter CHAPTER 2 --- BASIC THEOREMS OF DELTA SIGMA ADC --- p.6<br>Chapter 2.1 --- INTRODUCTION TO SAMPLING TECHNIQUE --- p.6<br>Chapter

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39

Lin, Haiqing. "Multi-bit delta-sigma switched-capacitor DACs employing element-mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33995.

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Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Most delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback, the use of multi-bit quantization would improve a delta-sigma modulator's performance by increasing the modulator's resolution or increasing the modulators's bandwidth, while at the same time whitening the quantization noise and improving modulator stability.

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40

Gao, Xiaoran. "A survey on continuous-time [delta sigma] modulators : theory, designs and implementations /." 2008. http://hdl.handle.net/1957/8386.

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41

Shui, Tao 1969. "Lowpass and bandpass current-mode delta-sigma DACs employing mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33910.

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Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. A recent development in the realm of delta-sigma-based ADC and DAC systems is the use of multilevel (as opposed to binary) quantization. This development owes its existence to th

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42

Dalal, Vineet R. "A switched-current bandpass delta-sigma modulator." Thesis, 1993. http://hdl.handle.net/1957/35637.

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43

Lee, Sang Hyeon. "High efficiency wideband low-power delta-sigma modulators." Thesis, 2012. http://hdl.handle.net/1957/30022.

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Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two arc

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da, Silva Jose Barreiro. "High-performance delta-sigma analog-to-digital converters." Thesis, 2004. http://hdl.handle.net/1957/29846.

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45

Yang, Yaohua 1969. "Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators." Thesis, 1993. http://hdl.handle.net/1957/36354.

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46

Zhang, Bo. "Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs." Thesis, 1996. http://hdl.handle.net/1957/34675.

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Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instr

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47

Guo, Yuhua. "A study of basic building blocks of analog-to-digital delta-sigma modulators." Thesis, 2004. http://hdl.handle.net/1957/30047.

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In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also introduced, which can effectively spread or shape the nonlinearity error of multi-bit DAC in the feedback path, thus improve the SNDR and THD performance of overall delta-sigma modulators. A three-bit quantizer design example is presented, which is embedded in a MASH2-0 structure delta-sigma modulator prototype and has been fabricated in AMI CMOS 1.5μm technology.

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48

Rajaee, Omid. "Design of low OSR, high precision analog-to-digital converters." Thesis, 2010. http://hdl.handle.net/1957/19654.

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Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is

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49

"Design techniques for low voltage wideband delta-sigma modulator." Thesis, 2010. http://library.cuhk.edu.hk/record=b6074846.

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Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced.<br>Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the a

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Yang, Yuqing Ph D. "System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications." 2008. http://hdl.handle.net/2152/18176.

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As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challe

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