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Journal articles on the topic 'Modulators (Electronics) Digital-to-analog converters'

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Published: 4 June 2021

Last updated: 7 February 2022

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GHARBIYA, AHMED, TREVOR C. CALDWELL, and D. A. JOHNS. "HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 297–317. http://dx.doi.org/10.1142/s0129156405003211.

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This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

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Nazarathy, Moshe, and Ioannis Tomkos. "Accurate Power-Efficient Format-Scalable Multi-Parallel Optical Digital-to-Analogue Conversion." Photonics 8, no. 2 (2021): 38. http://dx.doi.org/10.3390/photonics8020038.

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In optical transmitters generating multi-level constellations, optical modulators are preceded by Electronic Digital-to-Analog-Converters (eDAC). It is advantageous to use eDAC-free Optical Analog to Digital Converters (oDAC) to directly convert digital bitstreams into multilevel PAM/QAM optical signals. State-of-the-art oDACs are based on Segmented Mach-Zehnder-Modulators (SEMZM) using multiple modulation segments strung along the MZM waveguides to serially accumulate binary-modulated optical phases. Here we aim to assess performance limits of the Serial oDACs (SEMZM) and introduce an alternative improved Multi-Parallel oDAC (MPoDAC) architecture, in particular based on arraying multiple binary-driven MZMs in parallel: Multi-parallel MZM (MPMZM) oDAC. We develop generic methodologies of oDAC specification and optimization encompassing both SEMZM and MPMZM options in Direct-Detection (DD) and Coherent-Detection (COH) implementations. We quantify and compare intrinsic performance limits of the various serial/parallel DD/COH subclasses for general constellation orders, comparing with the scant prior-work on the multi-parallel option. A key finding: COH-MPMZM is the only class synthesizing ‘perfect’ (equi-spaced max-full-scale) constellations while maximizing energy-efficiency-SEMZM/MPMZM for DD are less accurate when maximal energy-efficiency is required. In particular, we introduce multiple variants of PAM4|8 DD and QAM16|64 COH MPMZMs, working out their accuracy vs. energy-efficiency-and-complexity tradeoffs, establishing their format-reconfigurability (format-flexible switching of constellation order and/or DD/COH).

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Colodro, F., J. M. Martinez-Heredia, J. L. Mora, and A. Torralba. "Open loop sigma-delta modulators for digital-to-analog converters with high speed improving using time interleaving." AEU - International Journal of Electronics and Communications 125 (October 2020): 153394. http://dx.doi.org/10.1016/j.aeue.2020.153394.

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Benvenuti, Lorenzo, Alessandro Catania, Giuseppe Manfredini, Andrea Ria, Massimo Piotto, and Paolo Bruschi. "Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs." Electronics 10, no. 10 (2021): 1156. http://dx.doi.org/10.3390/electronics10101156.

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The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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Shi, Yuan, Huang, et al. "Bias Controller of Mach–Zehnder Modulator for Electro-Optic Analog-to-Digital Converter." Micromachines 10, no. 12 (2019): 800. http://dx.doi.org/10.3390/mi10120800.

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As one of the core devices for an electro-optic analog-to-digital converter (ADC), the Mach–Zehnder (MZ) modulator plays an important role, and the output stability of the MZ modulator has a decisive influence on the conversion accuracy of the ADC. This paper proposed a pilot tone-based method to stabilize the bias point of the modulator. This method could obtain the corresponding control voltage of the MZ modulator by adding a KHz-level dither tone to the bias end of the modulator and calculating the ratio of the first and second harmonic components. The experimental results showed that the output optical power of the modulator was stable at 3.2 dB when the bias point of the modulator was set at the orthogonal point. Moreover, the fluctuation range was not more than 0.15 dB, the first harmonic of the output signal was stable at 50.5 dB, and the fluctuation range was not more than 0.6 dB. The proposed bias controller based on the field programmable gate array (FPGA) and digital signal processing (DSP) can stabilize the modulator bias point at the orthogonal point and with a relatively high locking accuracy.

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Hodge Worsham, A., D. L. Miller, P. D. Dresselhaus, A. H. Miklich, and J. X. Przybysz. "Superconducting modulators for high dynamic range delta-sigma analog-to-digital converters." IEEE Transactions on Appiled Superconductivity 9, no. 2 (1999): 3157–60. http://dx.doi.org/10.1109/77.783699.

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NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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FEELY, ORLA, and LEON O. CHUA. "NONLINEAR DYNAMICS OF A CLASS OF ANALOG-TO-DIGITAL CONVERTERS." International Journal of Bifurcation and Chaos 02, no. 02 (1992): 325–40. http://dx.doi.org/10.1142/s021812749200032x.

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Oversampled sigma-delta modulators are finding widespread use in audio and other signal processing applications, due to their simple structure and robustness to circuit imperfections. Exact analyses of the system are complicated by the presence of a discontinuous nonlinear element—a one-bit quantizer. In this paper, we study the dynamics of the one-dimensional mapping which models the behavior of the single-loop modulator. This mapping has a discontinuity at the origin and constant slope at all other points. With slope one, the dynamics in the region of interest reduce to those of the rotation of the circle. With slope less than one, almost all system inputs give rise to globally asymptotically stable periodic orbits. We emphasize the case with slope greater than one, and explain the structure of the resultant bifurcation diagram. A symbolic dynamics based study allows us to explain the self-similarity of the dynamics and the nature of chaos in the system.

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VERNIK, IGOR V. "ULTRASENSITIVE WIDEBAND INTEGRATED SPECTROMETER FOR CHEMICAL AND BIOLOGICAL AGENT DETECTION." International Journal of High Speed Electronics and Systems 18, no. 01 (2008): 87–98. http://dx.doi.org/10.1142/s0129156408005163.

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A novel concept of a compact mm/submm integrated spectrometers for environmental monitoring for hazardous materials of chemical and biological origin as well as for remote monitoring of the Earth atmosphere is discussed. The agents will be exactly identified by their unique spectral signatures. The assembled on a multi-chip module, cryocooler-mounted Superconducting Integrated SPectromer (SISP) exploits the superior performance of superconducting Josephson junction technology and unique on-chip integration of analog components, analog-to-digital converter, and digital components. Analog components include a superconductor-insulator-superconductor (SIS) mixer with integrated quasioptical antenna, mm-wave local oscillator, and SQUID amplifier for the down-converted (IF) signals. Upon amplification, the IF signal is digitized using a bandpass delta-sigma modulator, followed by real time processing with rapid single flux quantum (RSFQ) circuitry. Experimental results showing both operation of spectrometer components and the way to their successful integration are presented.

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Shoop, Barry L. "Second-order cascaded optical error diffusion modulators for oversampled analog-to-digital converters." Optics Communications 102, no. 1-2 (1993): 125–32. http://dx.doi.org/10.1016/0030-4018(93)90483-l.

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Quintero, Andres, Fernando Cardes, Carlos Perez, Cesare Buffa, Andreas Wiesbauer, and Luis Hernandez. "A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones." Sensors 19, no. 19 (2019): 4126. http://dx.doi.org/10.3390/s19194126.

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Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta ( Σ Δ ) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1 / f and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 μ A at 1.8 V and the effective area is 0.12 mm 2 . This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

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Inamdar, A., S. Rylov, A. Sahu, S. Sarwana, and D. Gupta. "Quarter-Rate Superconducting Modulator for Improved High Resolution Analog-to-Digital Converter." IEEE Transactions on Applied Superconductivity 17, no. 2 (2007): 446–50. http://dx.doi.org/10.1109/tasc.2007.897703.

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Morozov, D. V., M. M. Pilipko, and A. S. Korotkov. "Delta-sigma modulator of the analog-to-digital converter with ternary data encoding." Russian Microelectronics 40, no. 1 (2011): 59–69. http://dx.doi.org/10.1134/s1063739710061034.

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Banteywalu, Solomon, Baseem Khan, Valentijn De Smedt, and Paul Leroux. "A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter." Electronics 8, no. 5 (2019): 513. http://dx.doi.org/10.3390/electronics8050513.

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Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques.

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Lv, Risheng, Weiping Chen, and Xiaowei Liu. "A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes." Micromachines 9, no. 8 (2018): 372. http://dx.doi.org/10.3390/mi9080372.

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This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

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Wei, Cong, Jianhan Wu, Rongshan Wei, and Minghua He. "High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier." Journal of Electrical and Computer Engineering 2021 (April 13, 2021): 1–10. http://dx.doi.org/10.1155/2021/5533745.

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This study presents a high-fidelity and high-efficiency digital class-D audio power amplifier (CDA), which consists of digital and analog modules. To realize a compatible digital input, a fully digital audio digital-to-analog converter (DAC) is implemented on MATLAB and Xilinx System Generator, which consists of a 16x interpolation filter, a fourth-order four-bit quantized delta-sigma (ΔΣ) modulator, and a uniform-sampling pulse width modulator. The CDA utilizes the closed-loop negative feedback and loop-filtering technologies to minimize distortion. The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. The analog module is fabricated in a 0.18 µm BCD technology. The postlayout simulation results show that the CDA delivers an output power of 1 W with 93.3% efficiency to a 4 Ω speaker and achieves 0.0138% of the total harmonic distortion (THD) with a transient noise for a 1 kHz input sinusoidal test tone and 3.6 V supply. The output power reaches up to 2.73 W for 1% THD (with transient noise). The proposed amplifier occupies an active area of 1 mm2.

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Salimi, Atefeh, Rasoul Dehghani, and Abdolreza Nabavi. "A Digital Linear-Switching Hybrid Power Amplifier for Envelope Tracking Hybrid Supply Modulators." Journal of Circuits, Systems and Computers 26, no. 10 (2017): 1750162. http://dx.doi.org/10.1142/s0218126617501626.

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A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45[Formula: see text]nm CMOS technology. The overall power consumption of the digital block is around 76[Formula: see text]mW at 800[Formula: see text]MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32[Formula: see text]dBm output power for a 5[Formula: see text]MHz input signal.

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Spector, Steven, and Cheryl Sorace-Agaskar. "Silicon photonics devices for integrated analog signal processing and sampling." Nanophotonics 3, no. 4-5 (2014): 313–27. http://dx.doi.org/10.1515/nanoph-2013-0036.

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AbstractSilicon photonics offers the possibility of a reduction in size weight and power for many optical systems, and could open up the ability to build optical systems with complexities that would otherwise be impossible to achieve. Silicon photonics is an emerging technology that has already been inserted into commercial communication products. This technology has also been applied to analog signal processing applications. MIT Lincoln Laboratory in collaboration with groups at MIT has developed a toolkit of silicon photonic devices with a focus on the needs of analog systems. This toolkit includes low-loss waveguides, a high-speed modulator, ring resonator based filter bank, and all-silicon photodiodes. The components are integrated together for a hybrid photonic and electronic analog-to-digital converter. The development and performance of these devices will be discussed. Additionally, the linear performance of these devices, which is important for analog systems, is also investigated.

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Furuta, F., K. Saitoh, A. Yoshida, and H. Suzuki. "Characterization of sigma–delta modulator with LR-type integrator for superconducting analog-to-digital converter." Physica C: Superconductivity and its Applications 463-465 (October 2007): 1092–95. http://dx.doi.org/10.1016/j.physc.2007.01.062.

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Furuta, F., K. Saitoh, A. Yoshida, and H. Suzuki. "Experimental Evaluation of Signal-to-Noise Ratio of Sigma-Delta Modulator for Superconducting Analog-to-Digital Converter." IEEE Transactions on Applied Superconductivity 17, no. 2 (2007): 438–41. http://dx.doi.org/10.1109/tasc.2007.898239.

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Nahar, Ali Kareem, and Hussain K. Khleaf. "Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping." Bulletin of Electrical Engineering and Informatics 10, no. 4 (2021): 1952–59. http://dx.doi.org/10.11591/eei.v10i4.2934.

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This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.

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Murthy Dumpala, Ramana, and . "Technique to Improve SNR for Sigma Delta Adcs for Audio Signals." International Journal of Engineering & Technology 7, no. 3.6 (2018): 91. http://dx.doi.org/10.14419/ijet.v7i3.6.14946.

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A RISR architecture for Sigma-delta analog to digital converters with modified noise transfer function to obtain a better performance in terms of SNR is proposed. Cascading of two modified second order modulators are done to achieve 4th order modulator. Behavioral simulations are done to study the performance of feed-forward and the modified cascaded architecture. They are designed to operate at 1.28MHz clock frequency for audio applications (OSR of 32). It is noted that SNR of 115dB is achieved by cascading of two Modified second order RISR architectures which is 8dB more than the normal RISR architecture.

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Postek, M. T., and A. E. Vladar. "The bright future of digital imaging in scanning electron microscopy." Proceedings, annual meeting, Electron Microscopy Society of America 51 (August 1, 1993): 768–69. http://dx.doi.org/10.1017/s0424820100149672.

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One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 × 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 × 4096 resolution or greater. The two major categories of SEM systems to which digital technology have been applied are:In the analog SEM system the scan generator is normally operated in an analog manner and the image is displayed in an analog or "slow scan" mode.

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Watson, Jeff, and Maithil Pachchigar. "A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000053–57. http://dx.doi.org/10.4071/hitec-ta26.

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A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

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Wei, Rongshan, Weiwen Lin, Xiaoxia Xiao, Qunchao Chen, and Fanyang Li. "A Large Measurable Range Capacitance-to-Digital Converter for Smart Humidity Sensors." Micromachines 10, no. 9 (2019): 561. http://dx.doi.org/10.3390/mi10090561.

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This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.

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Gao, Zhenyi, Bin Zhou, Xiang Li, Lei Yang, Qi Wei, and Rong Zhang. "A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control." Sensors 21, no. 2 (2021): 431. http://dx.doi.org/10.3390/s21020431.

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Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.

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Høvin, M., T. S. Lande, A. Olsen та C. Toumazou. "Novel second-order Δ-Σ modulator/frequency-to-digital converter". Electronics Letters 31, № 2 (1995): 81–82. http://dx.doi.org/10.1049/el:19950093.

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Karthaus, Udo, Stephan Ahles, Ahmed Elmaghraby, and Horst Wagner. "A 2-bit, 3.1 GS/s, band-pass DSM receiver for active antenna systems." International Journal of Microwave and Wireless Technologies 5, no. 3 (2013): 329–34. http://dx.doi.org/10.1017/s1759078713000305.

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This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are −6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is −62.6 and −52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier.

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Postek, M. T., and A. E. Vladar. "The Bright Future of Digital Imaging in Scanning Electron Microscopy." Microscopy Today 2, no. 4 (1994): 19–20. http://dx.doi.org/10.1017/s1551929500065573.

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One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 X 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 X 4096 resolution or greater.

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Magrath, A. J., and M. B. Sandler. "Resolution enhancement and dither of sigma-delta modulator digital-to-analogue converters." Electronics Letters 31, no. 18 (1995): 1540–42. http://dx.doi.org/10.1049/el:19951063.

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Javahernia, Sahel, Esmaeil Najafi Aghdam, and Pooya Torkzadeh. "An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications." Journal of Circuits, Systems and Computers 29, no. 04 (2019): 2050056. http://dx.doi.org/10.1142/s0218126620500565.

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In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

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Lamo, Paula, Ángel de Castro, Christian Brañas, and Francisco J. Azcondo. "Emulator of a Boost Converter for Educational Purposes." Electronics 9, no. 11 (2020): 1883. http://dx.doi.org/10.3390/electronics9111883.

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Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a digital pulse-width modulator (DPWM) and a current mode controller, implemented in field-programmable gate array (FPGA) devices. To this end, the different parts of the project are developed and evaluated, maximizing the use of FPGA resources in the design of the HIL and DPWM blocks, and applying design techniques that minimize the use of the digital resources used in the design of the controller. Students are equipped with a new individualized educational experience, allowing them to test their technical competence and knowledge in an environment close to the reality of the industry.

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Kuo, C. H., S. L. Chen, and S. I. Liu. "Magnetic-to-Digital Converters Using Single-Amplifier-Based Second-Order Delta–Sigma Modulators." IEEE Sensors Journal 4, no. 2 (2004): 226–31. http://dx.doi.org/10.1109/jsen.2004.823685.

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Ramirez Bohorquez, Jose Luis, and Fabiano Fruett. "PWM output CMOS Stress Sensor based in PiezoFET current mirrors." Journal of Integrated Circuits and Systems 14, no. 2 (2019): 1–10. http://dx.doi.org/10.29292/jics.v14i2.75.

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This work shows the design and characterization of a stress sensor based on piezoFET current mirrors with a Pulse Width Modulated output, a compact device designed to be integrated in any CMOS process which is suitable to estimate the stress state over the silicon surface. The multi-terminal device integrates the piezo-MOSFETs with different alignments within current mirrors with the bias circuits to extract differential currents, which are related to the different stress components at the surface of the device. The analog current outputs are converter into single-bit digital signal using a Pulse Width modulator. In the absence of stress, the duty cycle of the output is 50%, but if stress is applied, the mismatches in the currents generate a shift in the duty cycle proportional to the stress. Since there are piezoFET aligned in different directions, it is possible to add the currents to isolate effect of the different stress components. The piezoFET current mirrors and the PWM stress sensor were characterized using a four-point bending test; a controlled uniaxial stress in a range [5MPa, 70MPa] was applied aligned to the main crystallographic directions of the device surface, while both the currents at the piezoFET mirrors and the digital output are observed. The analog outputs show a linear behaviour with stress and fit the equations from the piezoresistive effect while the duty cycle of the digital output varies also linearly around the 50%.

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Li, Di, Chunlong Fei, Qidong Zhang, Yani Li, and Yintang Yang. "A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs." Journal of Circuits, Systems and Computers 29, no. 07 (2019): 2050108. http://dx.doi.org/10.1142/s021812662050108x.

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A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

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An, Shengbiao, Shuang Xia, Yue Ma, et al. "A Low Power Sigma-Delta Modulator with Hybrid Architecture." Sensors 20, no. 18 (2020): 5309. http://dx.doi.org/10.3390/s20185309.

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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H Hasan, Mohammad, Amin Abbasalipour, Hamed Nikfarjam, et al. "Exploiting Pull-In/Pull-Out Hysteresis in Electrostatic MEMS Sensor Networks to Realize a Novel Sensing Continuous-Time Recurrent Neural Network." Micromachines 12, no. 3 (2021): 268. http://dx.doi.org/10.3390/mi12030268.

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The goal of this paper is to provide a novel computing approach that can be used to reduce the power consumption, size, and cost of wearable electronics. To achieve this goal, the use of microelectromechanical systems (MEMS) sensors for simultaneous sensing and computing is introduced. Specifically, by enabling sensing and computing locally at the MEMS sensor node and utilizing the usually unwanted pull in/out hysteresis, we may eliminate the need for cloud computing and reduce the use of analog-to-digital converters, sampling circuits, and digital processors. As a proof of concept, we show that a simulation model of a network of three commercially available MEMS accelerometers can classify a train of square and triangular acceleration signals inherently using pull-in and release hysteresis. Furthermore, we develop and fabricate a network with finger arrays of parallel plate actuators to facilitate coupling between MEMS devices in the network using actuating assemblies and biasing assemblies, thus bypassing the previously reported coupling challenge in MEMS neural networks.

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Gusenitsa, Yaroslav N., Aleksandr L. Snegirev, and Sergey A. Pokotilo. "Study of the characteristics of a radio photon device for determining the phase difference of a radar signals." Izmeritel`naya Tekhnika, no. 2 (2021): 38–42. http://dx.doi.org/10.32446/0368-1025it.2021-2-38-42.

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The paper considers the problem of accurate calculation of the phase of the radar signal in relation to the receiving phased antenna arrays. Methods for determining the phase difference based on a comparison of the received signal with the local oscillator signal are listed, as well as a method based on the use of a radio-photon analog-to-digital converter for the output signal of the receiving phased antenna array. Their disadvantages are indicated. A method and a radio photon device are proposed that are devoid of these disadvantages. The method allows you to calculate the phase difference of the radar signal at the output of the electro-optical modulator and the output signal of the photodetector, taking into account the known values of the amplitudes and phase difference of the microwave signals at the input of the receiving elements of the phased antenna array. The radio-photon device allows you to implement this method and, unlike the known analogues, is based on the use of two parallel-connected electro-optical modulators constructed according to the scheme of the Mach-Zehnder interferometer. It is shown that the proposed radio photon device provides a higher accuracy of determining the phase of the radar signal in comparison with existing analogues. At the end of the work, an analysis of the results of experimental studies using the proposed method and a radio photon device is presented. According to the results of the experiment, it was found that the phase and phase differences vary linearly, and their maximum reaches π. In addition, the square of the amplitude of the optical signal at the input of the photon-electronic unit is proportional to the phase difference and inversely proportional to the ratio of the amplitudes of the output signals of the adjacent receiving elements of the phased antenna arrays.

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Kalafat Kizilkaya, Isil, Mohammed Al-Janabi та Izzet Kale. "Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Î£âˆ’Î” modulators". ACTA IMEKO 4, № 1 (2015): 68. http://dx.doi.org/10.21014/acta_imeko.v4i1.165.

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Multiresolution analog-to-digital converters (MRADC) are usually used in Time Domain ElectroMagnetic Interference (TDEMI) measuring systems for very fast signal sampling with a sufficient dynamic range. The properties of the spectrum measured by the TDEMI system influenced by imperfections in the MRADC are analyzed in this paper. Errors are caused by imperfect matching of the offset and gain and phase of the circuits used in parallel input channels typical for the MRADC. For deep analyses of MRADC behavior, a precise mathematical model has been created using the concept of additive error pulses. Furthermore, a dedicated process of the identification of discrepancy parameters from experimental data is proposed. Identified parameters enter the expressions of the model and enable side to side comparison of experimental and theoretical results.Novel, multi-path, time-interleaved digital sigma-delta modulators that can operate at any arbitrary frequency from DC to Nyquist are designed, analysed and synthesized in this study. Dual- and quadruple-path fourth-order Butterworth, Chebyshev, Inverse Chebyshev and Elliptical based digital sigma-delta modulators, which offer designers the flexibility of specifying the centre-frequency, pass-band/stop-band attenuation as well as the signal bandwidth are presented. These topologies are compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity to non-idealities. Detailed simulations performed at the behavioural-level in MATLAB are compared with the experimental results of the FPGA implementation of the designed modulators. The signal-to-noise ratios between the simulated and empirical results are shown to be different by not more than 3-5 dBs. Furthermore, this paper presents the mathematical modelling and evaluation of the tones caused by the finite wordlengths of these digital multi-path sigma-delta modulators when excited by sinusoidal input signals.

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H Hasan, Mohammad, Ali Al-Ramini, Eihab Abdel-Rahman, Roozbeh Jafari, and Fadi Alsaleem. "Colocalized Sensing and Intelligent Computing in Micro-Sensors." Sensors 20, no. 21 (2020): 6346. http://dx.doi.org/10.3390/s20216346.

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This work presents an approach to delay-based reservoir computing (RC) at the sensor level without input modulation. It employs a time-multiplexed bias to maintain transience while utilizing either an electrical signal or an environmental signal (such as acceleration) as an unmodulated input signal. The proposed approach enables RC carried out by sufficiently nonlinear sensory elements, as we demonstrate using a single electrostatically actuated microelectromechanical system (MEMS) device. The MEMS sensor can perform colocalized sensing and computing with fewer electronics than traditional RC elements at the RC input (such as analog-to-digital and digital-to-analog converters). The performance of the MEMS RC is evaluated experimentally using a simple classification task, in which the MEMS device differentiates between the profiles of two signal waveforms. The signal waveforms are chosen to be either electrical waveforms or acceleration waveforms. The classification accuracy of the presented MEMS RC scheme is found to be over 99%. Furthermore, the scheme is found to enable flexible virtual node probing rates, allowing for up to 4× slower probing rates, which relaxes the requirements on the system for reservoir signal sampling. Finally, our experiments show a noise-resistance capability for our MEMS RC scheme.

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Maezawa, Koichi, Tatsuo Ito, and Masayuki Mori. "Delta-sigma modulation microphone sensors employing a resonant tunneling diode with a suspended microstrip resonator." Sensor Review 40, no. 5 (2020): 535–42. http://dx.doi.org/10.1108/sr-03-2020-0044.

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Purpose This paper aims to propose and demonstrate novel microphone sensors based on the frequency delta-sigma modulation (FDSM) technique, which replaces the conventional delta-sigma modulator in the delta-sigma analog-to digital converters. A key of the FDSM technology is to use a voltage-controlled oscillator (VCO) for converting an input analog signal to a 1-bit pulse-density modulated digital signal. High-performance sensors can be realized if the VCO is replaced by an oscillator whose oscillation frequency depends on an external physical parameter. Design/methodology/approach Microphone sensors are proposed based on FDSM that uses a suspended microstrip disk resonator, where the backside ground plane is replaced by a thin metal diaphragm. A resonant tunneling diode (RTD) oscillator is also used, as the performance of these sensors significantly depends on the oscillation frequency. To demonstrate the basic operation of the proposal, prototype devices were fabricated with an InGaAs/AlAs RTD. Findings A satisfactory noise shaping property, which is a significant nature of delta-sigma modulation, was demonstrated over three decades for the prototype device. A sound-sensing peak was also clearly observed when applying 1 kHz sound from a speaker. Practical implications High-performance ultrasonic microphone sensors can be realized if the sensors are fabricated by using a thin InP substrate with high-frequency oscillator design. Originality/value In this study, the authors proposed and experimentally demonstrated novel microphone sensors, which are promising as future ultrasonic sensors that have high dynamic range with wide bandwidth.

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Haentjens, B., G. Desruelles, G. Chrétien, et al. "Packaging Tradeoff for SIP Integration Targeting High Speed PAM-4 Applications." International Symposium on Microelectronics 2015, no. 1 (2015): 000730–34. http://dx.doi.org/10.4071/isom-poster3.

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High speed transmission systems using optical fiber are now focusing on 4-level PAM (Pulse Amplitude Modulation) format. This is requesting ultra-wideband electronic system in package, with a high phase linearity behavior in order to drive the electro-optical modulators. Moreover, new power DAC (Digital to Analog Converter) dies, are now available to generate up to 56 GBd, 4-level PAM signals, and providing 4Vpp of differential output amplitude swing. High frequency studies have been pursued to provide system integration in a BGA (Ball Grid Array) package. The BGA package transitions optimization and the configuration of multi-lines carriers, becomes a key step in the design flow. In this paper, some steps of the design, manufacturing process of the SIP (System In Package) and its demonstration board are proposed. The choices of the package, the thermal management, the clock management function are studied according to the final environmental constraint of the SIP. The data lines phase skew are analyzed with the support of EM (Electro Magnetic) simulations to better understand the potential impact on the output eye. Finally, the BGA package transition, simulated and measured results are compared, from DC up to 40 GHz and the measured SIP output, 4 levels, 56GBps eye diagram is presented.

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Lahouli, Rihab, Manel Ben-Romdhane, Chiheb Rebai, and Dominique Dallet. "Mixed baseband architecture based on FBD ΣΔ–based ADC for multistandard receivers." ACTA IMEKO 4, no. 3 (2015): 14. http://dx.doi.org/10.21014/acta_imeko.v4i3.258.

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<p>This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4<sup>th</sup> order single-bit Sigma-Delta modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.</p>

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Narasimman, Neelakantan, Dipankar Nag, Kevin T. C. Chai та Tony Tae-Hyoung Kim. "A Capacitance to Digital Converter Using Continuous Time ΔΣ Modulator for Microphone-Based Auscultation". IEEE Sensors Journal 21, № 12 (2021): 13373–83. http://dx.doi.org/10.1109/jsen.2021.3067804.

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Qian, Ying Qi, Chang Chun Zhang, Zhong Chao Liu та ін. "A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology". Applied Mechanics and Materials 519-520 (лютий 2014): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1085.

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Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

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Hassan, Ahmad, Mohamed Ali, Aref Trigui, Yvon Savaria, and Mohamad Sawan. "A GaN-Based Wireless Monitoring System for High-Temperature Applications." Sensors 19, no. 8 (2019): 1785. http://dx.doi.org/10.3390/s19081785.

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A fully-integrated data transmission system based on gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices is proposed. This system targets high-temperature (HT) applications, especially those involving pressure and temperature sensors for aerospace in which the environmental temperature exceeds 350 °C. The presented system includes a front-end amplifying the sensed signal (gain of 50 V/V), followed by a novel analog-to-digital converter driving a modulator exploiting the load-shift keying technique. An oscillation frequency of 1.5 MHz is used to ensure a robust wireless transmission through metallic-based barriers. To retrieve the data, a new demodulator architecture based on digital circuits is proposed. A 1 V amplitude difference can be detected between a high-amplitude (data-on) and a low-amplitude (data-off) of the received modulated signal. Two high-voltage supply levels (+14 V and −14 V) are required to operate the circuits. The layout of the proposed system was completed in a chip occupying 10.8 mm2. The HT characterization and modeling of integrated GaN devices and passive components are performed to ensure the reliability of simulation results. The performance of the various proposed building blocks, as well as the whole system, have been validated by simulation over the projected wide operating temperature range (25–350 °C).

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Primiani, Rurik A., Kenneth H. Young, André Young, et al. "SWARM: A 32 GHz Correlator and VLBI Beamformer for the Submillimeter Array." Journal of Astronomical Instrumentation 05, no. 04 (2016): 1641006. http://dx.doi.org/10.1142/s2251171716410063.

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A 32[Formula: see text]GHz bandwidth VLBI capable correlator and phased array has been designed and deployed a at the Smithsonian Astrophysical Observatory’s Submillimeter Array (SMA). The SMA Wideband Astronomical ROACH2 Machine (SWARM) integrates two instruments: a correlator with 140[Formula: see text]kHz spectral resolution across its full 32[Formula: see text]GHz band, used for connected interferometric observations, and a phased array summer used when the SMA participates as a station in the Event Horizon Telescope (EHT) very long baseline interferometry (VLBI) array. For each SWARM quadrant, Reconfigurable Open Architecture Computing Hardware (ROACH2) units shared under open-source from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) are equipped with a pair of ultra-fast analog-to-digital converters (ADCs), a field programmable gate array (FPGA) processor, and eight 10 Gigabit Ethernet (GbE) ports. A VLBI data recorder interface designated the SWARM digital back end, or SDBE, is implemented with a ninth ROACH2 per quadrant, feeding four Mark6 VLBI recorders with an aggregate recording rate of 64 Gbps. This paper describes the design and implementation of SWARM, as well as its deployment at SMA with reference to verification and science data.

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Ahmad, Shakeel, та Jerzy Dąbrowski. "One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC Test". Journal of Circuits, Systems and Computers 29, № 15 (2020): 2050245. http://dx.doi.org/10.1142/s021812662050245x.

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This paper presents an application of the [Formula: see text] modulation technique to the on-chip dynamic test for analog-to-digital converters (ADCs). The required stimulus such as a single- or two-tone signal is encoded into one-bit [Formula: see text] sequence, which is applied to an ADC under test through a driving buffer and a simple low-pass reconstruction filter. By a systematic approach, we select the order and type of a [Formula: see text] modulator and develop a frequency plan suitable for the spectral measurement. In this way, we achieve a high dynamic range suitable for spectral harmonic and intermodulation distortion tests for ADCs. For high frequency measurements (up to the Nyquist frequency), we propose a novel low-pass/band-pass modulation scheme that allows to avoid harmful effects of the low-frequency quantization noise. Also we address the distortion components which originate from the buffer imperfections for a nonreturn-to-zero waveform representing the encoded stimulus. We show that the low-frequency distortion components can be cancelled by using a simple iterative predistortion technique supported by measurements with a DC-calibrated ADC. By correlation between low- and high-frequency components also the high frequency distortions can be largely reduced. The presented techniques are illustrated by simulation results of an ADC under test.

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Rothberg, Jonathan M., Tyler S. Ralston, Alex G. Rothberg, et al. "Ultrasound-on-chip platform for medical imaging, analysis, and collective intelligence." Proceedings of the National Academy of Sciences 118, no. 27 (2021): e2019339118. http://dx.doi.org/10.1073/pnas.2019339118.

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Over the past half-century, ultrasound imaging has become a key technology for assessing an ever-widening range of medical conditions at all stages of life. Despite ultrasound’s proven value, expensive systems that require domain expertise in image acquisition and interpretation have limited its broad adoption. The proliferation of portable and low-cost ultrasound imaging can improve global health and also enable broad clinical and academic studies with great impact on the fields of medicine. Here, we describe the design of a complete ultrasound-on-chip, the first to be cleared by the Food and Drug Administration for 13 indications, comprising a two-dimensional array of silicon-based microelectromechanical systems (MEMS) ultrasonic sensors directly integrated into complementary metal–oxide–semiconductor-based control and processing electronics to enable an inexpensive whole-body imaging probe. The fabrication and design of the transducer array with on-chip analog and digital circuits, having an operating power consumption of 3 W or less, are described, in which approximately 9,000 seven-level feedback-based pulsers are individually addressable to each MEMS element and more than 11,000 amplifiers, more than 1,100 analog-to-digital converters, and more than 1 trillion operations per second are implemented. We quantify the measured performance and the ability to image areas of the body that traditionally takes three separate probes. Additionally, two applications of this platform are described—augmented reality assistance that guides the user in the acquisition of diagnostic-quality images of the heart and algorithms that automate the measurement of cardiac ejection fraction, an indicator of heart health.

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