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Dissertations / Theses on the topic 'Monopulse'
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Young, Larry Alan. "High resolution monopulse tracking." Master's thesis, University of Central Florida, 1988. http://digital.library.ucf.edu/cdm/ref/collection/RTD/id/73935.
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University of Central Florida College of Engineering Thesis<br>High Resolution Radar techniques are applied to the problem of resolving a multiple target array and locating its geometric center without the usual biasing toward the brightest targets. Monopulse radar techniques are combined with high resolution stepped frequency pulse train signal processing in an amplitude tracking radar. A single pulse monopulse system's aimpoint is biased toward the brightest point targets in an array. However, by using a stepped frequency pulse monopulse radar, the cross range distance to each individual scatterer may be found. Unlike the single pulse monopulse system, the aimpoint is independent of the reflectivity of the targets. The geometric center of a multiple scatterer array is found by averaging the cross range components along both axes. For the stepped frequency high resolution monopulse system, the center of each uniquely separated pair of point targets is calculated by examining the cross-correlation function of the sum and difference channels. The autocorrelation of the sum channel is used to normalize the cross-correlation data thereby eliminating the effects of the different targets radar cross sections (RCS). The zero separation term of the error function (DC term) remains biased toward the bigger scatterer, even after normalization. The nonzero terms (AC terms) are the cross range distances from the antenna's boresight to each scatterer and are independent of their RCS. By simply dropping ones together, the aimpoint becomes the unbiased geometric center of the array. The special cases of one, two and three resolvable point scatterers are examined in detail. Analysis of a nondiscrete complex scattering array is not presented, since the requirement of separation pair uniqueness cannot be assumed. The monopulse tracking simulation work was done on an IMB AT using Microsoft Fortran-77.<br>M.S.<br>Masters<br>Engineering<br>Engineering<br>105 p.<br>v, 105 leaves, bound : ill. ; 28 cm.
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Seliktar, Yaron. "Space-time adaptive monopulse processing." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13075.
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Sahin, Mehmet Alper. "Performance Optimization Of Monopulse Tracking Radar." Master's thesis, METU, 2004. http://etd.lib.metu.edu.tr/upload/2/12605364/index.pdf.
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An analysis and simulation tool is developed for optimizing system parameters of the monopulse target tracking radar and observing effects of the system parameters on the performance of the system over different scenarios.
A monopulse tracking radar is modeled for measuring the performance of the radar with given parameters, during the thesis studies. The radar model simulates the operation of a Class IA type monopulse automatic tracking radar, which uses a planar phased array. The interacting multiple model (IMM) estimator with the Probabilistic Data Association (PDA) technique is used as the tracking filter. In addition to modeling of the tracking radar model, an optimization tool is developed to optimize system parameters of this tracking radar model. The optimization tool implements a Genetic Algorithm (GA) belonging to a GA Toolbox distributed by
Department of Automatic Control and System Engineering at University of Sheffield.
The thesis presents optimization results over some given optimization scenarios and concludes on effect of tracking filter parameters, beamwidth and dwell interval for the confirmed track.
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Glass, John David. "Monopulse processing and tracking of maneuvering targets." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53556.
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As part of the processing of tracking targets, surveillance radars detect the presence of targets and estimate their locations. This dissertation re-examines some of the often ignored practical considerations of radar tracking. With the advent of digital computers, modern radars now use sampled versions of received signals for processing. Sampling rates used in practice result in the bin-straddling phenomenon, which is often treated as an undesired loss in signal power. Here, a signal model that explicitly models the sampling process is used in the derivation of the average loglikelihood ratio test (ALLRT), and its detection performance is shown to defeat the bin-straddling losses seen in traditional radar detectors. In monopulse systems, data samples are taken from the sum and difference channels, by which a target direction-of-arrival (DOA) estimate can be formed. Using the same signal model, we derive new estimators for target range, strength, and DOA and show performance benefits over traditional monopulse techniques that are predominant in practice. Since tracking algorithms require an error variance report on target parameter estimates, we propose using the generalized Cramer-Rao lower bound (GCRLB), which is the CRLB evaluated at estimates rather than true values, as an error variance report. We demonstrate the statistical efficiency and variance consistency of the new estimators. With several parameter estimates collected over time, tracking algorithms are used to compute track state estimates and predict future locations. Using agile- beam surveillance radars with programmable energy waveforms, optimal scheduling of radar resources is a topic of interest. In this dissertation, we focus on the energy management considerations of tracking highly maneuverable aircraft. A comparison between two competing interacting multiple model (IMM) filter configurations is made, and a recently proposed unbiased mixing procedure is extended to the case of three modes. Finally, we introduce the radar management operating curve (RMOC), which shows the fundamental tradeoff in radar time and energy, to aid radar designers in the selection of an overall operating signal-to-noise level.
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Patriksson, Alfred. "Radio signal DOA estimation : Implementing radar signal direction estimation on an FPGA." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-157144.
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This master’s thesis covers the design and implementation of a monopulse directionof arrival (DOA) estimation algorithm on an FPGA. The goal is to implement a complete system that is capable of estimating the bearing of an incident signal. In order to determine the estimate quality both a theoretical and practical noise analysis of the signal chain is performed. Special focus is placed on the statistical properties of the transformation from I/Q-demodulated signals with correlated noise to a polar representation. The pros and cons for three different methods of calculating received signal phasors are also covered.The system is limited to two receiving channels which constrains this report to a 2D analysis. In addition the used hardware is limited to C-band signals. We show that an FPGA implementation of monopulse techniques is definitely viable and that an SNR higher than ten dB allows for a gaussian approximation of the polar representationof an I/Q signal.
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Champion, James. "A 3-CHANNEL MONOPULSE TRACKING RECEIVER SYSTEM USING COMMERCIAL OFF-THE-SHELF EQUIPMENT." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607375.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California<br>Three-channel monopulse tracking receiver systems are commonly used for high
performance tracking of satellites, missiles, or aircraft to maximize the reception of data.
Typically, the receiver in such systems are custom designed for their end purpose. This
results in a high cost to cover the development, service, and support of a highly
specialized piece of equipment.
This paper covers the requirements and performance of a 3-channel monopulse tracking
receiver assembled from commercial-off-the-shelf (COTS) equipment. Such a system
provides an option for designing or upgrading tracking stations with the lower cost, larger
support base, and greater system configuration choices that are available with COTS
equipment.
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Hagos, Mussie Ghebreegziabiher. "S-band monopulse radar receiver design and implementation." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/2876.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.<br>This thesis documents the design and implementation of an S-band receiver for phasecomparison
monopulse radar. The design and evaluation of the various sub-systems involved
in realizing the receiver are discussed in detail. The designed sub-systems are connected
via low loss coaxial cables to form the complete phase-comparison monopulse radar
receiver. The performance of the receiver is evaluated and compared with the theoretical
results, in terms of frequency response, gain and noise figure.
The designed receiver is finally connected to an existing antenna system, and a preliminary
test of the complete radar is performed. The initial results show that the design is successful,
but the boresight-axis of the radar has shifted in angle and requires pre-comparator phase
shifting in order to obtain accurate tracking.
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Rowe, Phillip James 1974. "Characterization of a wideband monopulse piezoelectric direction finder." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/9796.
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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (leaves 76-78).<br>Sound localization has been the subject of much ongoing research in the area of beamformers and microphone arrays. Although these methods have been successful under certain conditions, the signal processing requirements needed for real-time operation are extensive. This thesis describes the construction and test of a piezoelectric monopulse directionfinding sensor used to determine the angular location of a source within the plane of the sensor. The design of the sensor exploits spatially derivative-matched sensing apertures to eliminate angle ambiguities and frequency dependence of the monopulse ratio. The electronics front end and processing are very simple, consisting of averaging the sample-by-sample ratios of the rectified-and-smoothed outputs during their reverberation-free time period. Several experiments are described with different inputs, and the sensor's operation is compared to theoretical and simulated behavior. Although the effects of the hexcell support on the spatial weighting of the sensor are not fully understood, it is shown that the sensor behaves as a dispersionless monopulse sensor for an angular range of ± 40° and a bandwidth of 4 kHz. It is also shown that the sensor does not, in its current form, produce adequate signal levels to be used as a speech localization device.<br>by Phillip James Rowe.<br>M.Eng.
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Kwon, Ki Hoon. "Optimizing ECM techniques against monopulse acquisition and tracking radars." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/26140.
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Bengtsson, Filip, and David Sköld. "Analysis of angular accuracy in the IFF Monopulse receiver." Thesis, Linköpings universitet, Fysik och elektroteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-150140.
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This master thesis investigates how certain components error margin may affect the accuracy of a IFF monopulse receiver. The IFF monopulse receiver measures the angle of arrival of the incident signal by comparing sum and difference signals created in the receiver. The components of interest are phase shifters and attenuators, where both can give individual and different errors depending on the antenna steering angle. The project is conducted at Saab Aeronautics, based on a receiver in development for the Gripen E aircraft. The results of the thesis generated results showing that the angular accuracy decreases with the increase of steering angle. The angular deviation can for some cases be seen as sufficiently small for the receiver to work properly in the ideal case.
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McNamara, Derek Albert. "On the synthesis of optimum monopulse antenna array distributions." Doctoral thesis, University of Cape Town, 1986. http://hdl.handle.net/11427/21867.
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The stringent specifications of modern tracking systems demand antennas of high performance. For this reason arrays are finding increasing application as monopulse antennas. A new exact procedure is introduced for the synthesis of optimum difference distributions for linear arrays of discrete elements, with a maximum sidelobe level specification. The method is based on the Zolotarev polynomial, and is precisely the difference mode equivalent of the Dolph-Chebyshev synthesis for sum patterns. When the interelement spacings are a half-wavelength or larger the element excitations are obtained in a very direct manner from the Chebyshev series expansion of the Zolotarev polynomial. For smaller spacings, a set of recursive equations is derived for finding the array excitation set. Efficient means of performing all the computations associated with the above procedure are given in full. In addition, a set of design tables is presented for a range of Zolotarev arrays of practical utility. A novel technique, directly applicable to arrays of discrete elements, for the synthesis of high directivity difference patterns with arbitrary si delobe envelope tapers is presented. This is done by using the.Zolotarev space factor zeros and correctly relocating these in a well-defined manner to effect the taper. A solution to the direct synthesis of discrete array sum patterns with arbitrary sidelobe envelope tapers is introduced. In this case the synthesis is also done by correct placement of the space factor zeros. The above techniques enable high excitation efficiency, low sidelobe, sum and difference pat terns to be synthesized independently. Contributions to the simultaneous synthesis of sum and difference patterns, subject to specified array feed network complexity constraints, are also given. These utilise information on the excitations and space factor zeros of the independently optimal solutions, along with constrained numerical optimisation. The thesis is based on original research done by the author, except where explicit reference is made to the work of others.
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Dunn, Daniel S., and Eugene P. Augustin. "A Single Channel Monopulse Antenna with Low Effective Sidelobes." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/611932.
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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California<br>This paper describes a CSC² single axis tracking antenna using a single channel monopulse antenna which has improved sidelobe performance over conventional single channel monopulse antennas. Effective sidelobes of the composite pattern, measured at the receiver input, greater than 22 dB have been achieved. This is due to a unique feed design. The composite patterns are the true measure of performance for a single channel monopulse system since this is the input to the tracking receiver. The low effective sidelobes result in a significant reduction of multi-path problems.
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Moraal, Reinart Johan. "Pattern synthesis and design of a microstrip wire grid monopulse antenna." Diss., University of Pretoria, 2017. http://hdl.handle.net/2263/62783.
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The design of a monopulse microstrip wire grid antenna array is presented with simultaneously low side lobe levels in the sum pattern as well as both azimuth difference and elevation difference patterns. Monopulse antennas are a class of antennas used for direction finding in radar systems, and the control of side lobe levels is important to help with clutter rejection. The microstrip wire grid array is ideally suited to monopulse applications, and it has been shown in the literature that side lobes can be lowered by implementing an excitation taper across the aperture. Although it has been demonstrated in the literature that side lobes could be lowered for the sum pattern by applying a Taylor taper to the element excitation, it has not been shown that the antenna can be designed to produce an exact side lobe level. This work develops a synthesis method to design an excitation taper that would produce simultaneously low side lobes for the sum and both difference patterns. The resulting side lobe levels are a compromise between the patterns, since it is not possible to have arbitrarily low side lobe levels in all the antenna patterns without using complex feed structures and incorporating sub-arraying. This is true for monopulse antennas in general. The result of this work shows that it is quite difficult to achieve an exact side lobe requirement with a specific excitation taper, since mutual coupling and the current distribution at the feed affect the current distribution across the entire antenna in different ways depending on the antenna mode, or pattern generated.<br>Dissertation (MEng)--University of Pretoria, 2017.<br>Electrical, Electronic and Computer Engineering<br>MEng<br>Unrestricted
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Yeh, Jia-Hsin. "Effects of towed-decoys against an anti-air missile with a monopulse seeker." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA304221.
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Sheret, Tamara Louise. "Design, analysis and validation of a twist reflector monopulse antenna system with radome." Thesis, Queen Mary, University of London, 2017. http://qmro.qmul.ac.uk/xmlui/handle/123456789/24740.
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This thesis presents a new approach to the hardware test environment for a twist reflector monopulse antenna system with a radome extending current measurement practice. New research is presented on the optimisation of the design of a twist reflector monopulse antenna system with a radome, significantly improving the design and the design process. A unique extension to current measurement practice, for single channel antennas, is presented to determine the best practice method on phase stable measurements of a multi-channel antenna on a moving positioner. A novel axis transform for a 3 axis positioner system located within an anechoic chamber is derived. It allows for true performance measurement of a twist reflector antenna with a radome. This progresses the field of antenna measurement as, uniquely, this axis transform allows the aberration caused by the antenna radome to be measured and included. Design improvements have been made on polarisation selective grids, the matched thickness of the radome and a new software method that removes the need for a comparator and increases the robustness of the antenna system. Polarisation selective grids, constructed from a set of parallel conductors, have a wide range of uses in antenna systems. This thesis shows that the depth of a copper grid line can be reduced to 15 m and still provide better than -25 dB cross-polar isolation. This is contrary to current understanding at 30 times the skin depth. A new combined approach to radome thickness optimisation is presented that reduces the time taken to calculate the optimal thickness by over 3 orders of magnitude and the computer memory by over 2 orders of magnitude without compromising accuracy. The use of a digital comparator is described and leads to a novel method to compensate for a failed feed element, verifified in both simulation and anechoic chamber measurements.
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Van, der Linden C. P. "Design of a TMS320 C25 signal processor for use in a monopulse radar." Master's thesis, University of Cape Town, 1991. http://hdl.handle.net/11427/14362.
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Summary in English.<br>Charts in pocket.<br>Bibliography: leaf 65.<br>The advent of better and faster digital signal processing chips has led to digital implementation of many functions that have previously only been possible using analogue techniques. One such field is monopulse radar where available processing time is limited strictly to the radar pulse repetition frequency. The aim of this thesis is to design a specific signal processor using a Texas Instruments TMS320 C25 processor. This design is intended for monopulse radar systems using low pulse repetition frequencies. Features typical to monopulse radar signal processing, have been described here as system requirements. From this description a system specification, which is in fact the functional design of the processor, has been developed. Prototype circuitry was then designed and built in order to test the feasibility of performing, within the required time, the functions outlined in the system specification. Following on from the results of the tests, design of the hardware commenced. The design was successfully completed and tested. Although the TMS320 C25 was not found to be the ideal processor for this application, it is capable of performing the task within the required time. Careful consideration was given to the software design. A trade off between easily maintainable, high level language software, and high speed assembler had to be made. The final product is written in c but with critical procedures implemented in in-line assembler. This thesis provides insight into the type of hardware and the level of signal processing required for one type of signal processor used in a low PRF monopulse system.
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Yeh, ShihYuan. "Development of a digital tracking array with single-channel RSNS and monopulse digital beamforming." Thesis, Monterey, California. Naval Postgraduate School, 2010. http://hdl.handle.net/10945/4956.
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Approved for public release; distribution is unlimited<br>Unmanned aerial vehicles (UAVs) are widely used in military applications, and one of the most common missions is remote sensing. Remote sensing requires UAVs equipped with different kinds of sensors. Information collected by remote sensors must be transmitted back to a ground control station (GCS) to conduct analysis. The majority of UAVs are controlled directly by GCS personnel using radio frequency (RF), line-of-sight (LOS) links. The ground antenna must acquire and then track the UAV signal. A digital phased array allows signal processing functions to be performed in the antenna processor as well as beamforming and tracking. The development of a digital tracking array with single-channel robust symmetrical number system (RSNS) and monopulse digital beamforming (DBF) to track a UAV's transmitted signal is described in this thesis. The RSNS is used as the direction finding (DF) algorithm and can provide high angle resolution with two closely spaced elements. However, as is typical for an array, the angle accuracy is reduced at the two ends of the field-of-view (FOV). The monopulse DBF is used to precisely track the signals. The monopulse tracking technique provides precise angle accuracy within a FOV of approximately ±45. The tracking system is developed in LabView, and the performance of a six-element prototype array is demonstrated by measurement in an anechoic chamber.
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Oliver, John Marcus. "3D Micromachined Passive Components and Active Circuit Integration for Millimeter-wave Radar Applications." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/77049.
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The development of millimeter-wave (30-300 GHz) sensors and communications systems has a long history of interest, spanning back almost six decades. In particular, mm-wave radars have applications as automotive radars, in remote atmospheric sensing applications, as landing radars for air and spacecraft, and for high precision imaging applications. Mm-wave radar systems have high angular accuracy and range resolution, and, while susceptible to atmospheric attenuation, are less susceptible to optically opaque conditions, such as smoke or dust. This dissertation document will present the initial steps towards a new approach to the creation of a mm-wave radar system at 94 GHz.
Specifically, this dissertation presents the design, fabrication and testing of various components of a highly integrated mm-wave a 94 Ghz monopulse radar transmitter/receiver. Several architectural approaches are considered, including passive and active implementations of RF monopulse comparator networks. These architectures are enabled by a high-performance three-dimensional rectangular coaxial microwave transmission line technology known as PolyStrataTM as well as silicon-based IC technologies. A number of specific components are examined in detail, including: a 2x2 PolyStrata antenna array, a passive monopulse comparator network, a 94 GHz SiGe two-port active comparator MMIC, a 24 GHz RF-CMOS 4-port active monopulse comparator IC, and a series of V- and W-band corporate combining structures for use in transmitter power combining applications.
The 94 GHz cavity-backed antennas based on a rectangular coaxial feeding network have been designed, fabricated, and tested. 13 dB gain for a 2 x 2 array, as well as antenna patterns are reported. In an effort to facilitate high-accuracy measurement of the antenna array, an E-probe transition to waveguide and PolyStrata diode detectors were also designed and fabricated. AW-band rectangular coaxial passive monopulse comparator with integrated antenna array and diode detectors have also been presented. Measured monopulse nulls of 31.4 dB in the ΔAZ plane have been demonstrated.
94-GHz SiGe active monopulse comparator IC and 24 GHz RF-CMOS active monopulse comparator RFIC designs are presented, including detailed simulations of monopulse nulls and performance over frequency. Simulations of the W-band SiGe active monopulse comparator IC indicate potential for wideband operation, with 30 dB monopulse nulls from 75-105 GHz. For the 24-GHz active monopulse comparator IC, simulated monopulse nulls of 71 dB and 68 dB were reported for the azimuthal and elevational sweeps. Measurements of these ICs were unsuccessful due to layout errors and incomplete accounting for parasitics.
Simulated results from a series of rectangular coaxial power corporate power combining structures have been presented, and their relative merits discussed. These designs include 2-1 and 4-1 reactive, Wilkinson, and Gysel combiners at V- and W-band. Measured back-to-back results from Gysel combiners at 60 GHz included insertion loss of 0.13 dB per division for a 2-1 combination, and an insertion loss of 0.3 dB and 0.14 dB for "planar" and "direct" 4-1 combinations, respectively. At 94 GHz, a measured insertion loss of 0.1 dB per division has been presented for a 2-1 Gysel combination, using a back-to-back structure. Preliminary designs for a solid-state power amplifier (SSPA) structure have also been presented. Finally, two conceptual monopulse transceivers will be presented, as a vehicle for integrating the various components demonstrated in this dissertation.<br>Ph. D.
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Khan, Asim Ali. "Performance optimisation of small antenna arrays." Thesis, University of Manchester, 2011. https://www.research.manchester.ac.uk/portal/en/theses/performance-optimisation-of-small-antenna-arrays(759e6929-04ab-408c-aee3-404c72711cdb).html.
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This thesis addresses radiation pattern synthesis problems for small linear periodic phased arrays (with array elements less then 10). Due to the small array size conventional pattern synthesis techniques fail to produce the required results. In the case of practical small arrays, mutual coupling and element pattern asymmetric effect degrade the array radiation performance. The main performance metrics considered in this thesis include side lobe level (SLL), gain, halfpower beamwidth (HPBW) and mainbeam scan direction. The conventional pattern synthesis approaches result in sub optimal gain, SLL and HPBW due to the limited number of elements and the mutual coupling involved. In case of difference pattern synthesis these factors resulted in lower difference pattern slope, degraded SLL and difference peak asymmetry. The sum and difference patterns are used in monopulse arrays and a simplified feed that could produce both patterns with acceptable radiation properties is of interest and has been examined (chapter 5). A conventional technique is applied to small arrays to synthesise a sector beam and there is limited control over the radiation pattern. It is shown that the mutual coupling has significant effect on the array radiation pattern and mitigation is necessary for optimum performance (chapter 6). Furthermore, wideband phased arrays may have a natural limitation of the HPBW in low gain applications and minimisation of the variation becomes important. Also the SLL variations for wideband antenna arrays in the presence of mutual coupling considerably degrade the radiation pattern. The mutual coupling degrades significantly the radiation pattern performance in case of small scanning wideband arrays (chapter 7). It is the primary goal of this thesis to develop an optimisation scheme thatis applied in the above scenarios (chapters 3 & 4). The only degree of freedom assumed is the array excitation. Optimised amplitude and phase for each element in the array are determined by the proposed scheme, concurrently. The deterministic optimisation techniques reported in the literature for the pattern synthesis may involve complicated problem modelling. The heuristic opti-misation techniques generally are computationally expensive. The proposedIntelligent z-space Boundary Condition-Particle Swarm Optimiser (IzBC-PSO)is based on a heuristic algorithm. This scheme can be applied to a wider rangeof problems without significant modifications and requires fewer computationscompared to the competing techniques.In order to verify the performance of IzBC-PSO antenna array measure-ments were performed in the receiving mode only using the online and offlinedigital beamforming setups described in chapter 8. The measurement resultsshow that the proposed scheme may be successfully applied with both onlineand offline digital beamformers for a practical small array (chapter 8).
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Barnard, Daniel David. "Bore sight error analysis in seeker antennas : a fully functional GUI interfaced ray tracing solution." Thesis, Stellenbosch : Stellenbosch University, 2013. http://hdl.handle.net/10019.1/79991.
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Thesis (MScEng)--Stellenbosch University, 2013.<br>ENGLISH ABSTRACT: Airborne seeker antennas are usually enclosed within a dielectric radome for protection against their harsh operational environment. However the presence of a radome can introduce serious degrading effects on the radiation and electrical performance of the enclosed antenna. The degradation effect studied in this report is that of Bore Sight Error (BSE). BSE is a squint in the pointing accuracy of the antenna due to the enclosing radome. A ray-tracing approach is presented that is able to analyse the BSE of seeker radomes in general and is especially suited to electrically large radomes where other computational electromagnetic techniques become overly computationally intensive.
The ray-tracing algorithm is wrapped in a GUI which, given the radome, antenna, polarisation and incidence plane parameters will compute the BSE for any set of requested scan angles. Close agreement was obtained with measured BSE performance available in literature. Due to easy setup and fast computation time it is demonstrated that the GUI can be efficiently used for iterative radome design and optimisation.<br>AFRIKAANSE OPSOMMING: Luggedrae soekantennes is normaalweg omhul binne ‘n dielektriese antennekoepel vir beskerming teen ‘n strawwe omgewing. Die teenwoordigheid van ‘n antennakoepel kan egter ernstige nadelige effekte op die straling en elektriese werkverrigting van die omhulde antenne hê. Die nadelige effek wat in hierdie verslag ondersoek word, is dié van die “Bore Sight Error (BSE).” BSE is ‘n afwyking in die akkuraatheid van die antenna se rigtingwysing as gevolg van die antennakoepel. Straal-natrekking wat die BSE van soek-antennekoepels in die algemeen kan analiseer word beskryf. Hierdie tegniek is veral gepas vir elektries groot antennekoepels waar die berekenige vir EM tegnieke te intensief raak.
Die straalnatrekkingsalgoritme word omvat in ‘n grafiese gebruikerskoppelvlak. Gegee die parameters van die antennekoepel, antenne, polarisasie en invallende vlak, sal die BSE vir enige stel skandeerhoeke bereken word. Goeie ooreenstemming was verkry, vergeleke met gemete BSE vanuit die literatuur. Die eenvoudige opstel van die koppelvlak en vinnige berekeningstyd wys daarop dat die koppelvlak doeltreffend gebruik kan word vir iteratiewe antennekoepel ontwerp en optimering.
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Fourtinon, Luc. "3D conformal antennas for radar applications." Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2017. http://www.theses.fr/2017IMTA0060/document.
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Embarqué sous le radôme du missile, les autodirecteurs existants utilisent une rotation mécanique du plan d’antenne pour balayer le faisceau en direction d’une cible. Les recherches actuelles examinent le remplacement des composantes mécaniques de rotation de l’antenne par un nouveau réseau d’antennes 3D conformes à balayage électronique. Les antennes 3D conformes pourraient offrir des avantages significatifs, tels qu’un balayage plus rapide et une meilleure couverture angulaire mais qui pourraient aussi offrir de nouveaux challenges résultant d’un diagramme de rayonnement plus complexes en 3D qu’en 2D. Le nouvel autodirecteur s’affranchit du système mécanique de rotation ce qui libère de l’espace pour le design d’une nouvelle antenne 3D conforme. Pour tirer le meilleur parti de cet espace, différentes formes de réseaux sont étudiées, ainsi l’impact de la position, de l’orientation et de la conformation des éléments est établi sur les performances de l’antenne, en termes de directivité, ellipticité et de polarisation. Pour faciliter cette étude de réseaux 3D conformes, un programme Matlab a été développé, il permet de générer rapidement le diagramme de rayonnement en polarisation d’un réseau donné dans toutes les directions. L’une des tâches de l’autodirecteur consiste à estimer la position d’une cible donnée afin de corriger la trajectoire du missile. Ainsi, l’impact de la forme du réseau sur l’erreur entre la direction d’arrivée mesurée de l’écho de la cible et sa vraie valeur est analysé. La borne inférieure de Cramer-Rao est utilisée pour calculer l’erreur minimum théorique. Ce modèle suppose que chaque élément est alimenté séparément et permet ainsi d’évaluer le potentiel des réseaux 3D conformes actifs.Finalement, l’estimateur du monopulse en phase est étudié pour des réseaux 3D conformes dont les quadrants n’auraient pas les mêmes caractéristiques. Un nouvel estimateur, plus adapté à des quadrants non identiques, est aussi proposé<br>Embedded below the radome of a missile, existing RF-seekers use a mechanical rotating antenna to steer the radiating beam in the direction of a target. Latest research is looking at replacing the mechanical antenna components of the RF-seeker with a novel 3D conformal antenna array that can steer the beam electronically. 3D antennas may offer significant advantages, such as faster beam steering and better coverage but, at the same time, introduce new challenges resulting from a much more complex radiation pattern than that of 2D antennas. Thanks to the mechanical system removal, the new RF-seeker has a wider available space for the design of a new 3D conformal antenna. To take best benefits of this space, different array shapes are studied, hence the impact of the position, orientation and conformation of the elements is assessed on the antenna performance in terms of directivity, ellipticity and polarisation. To facilitate this study of 3D conformal arrays, a Matlab program has been developed to compute the polarisation pattern of a given array in all directions. One of the task of the RF-seeker consists in estimating the position of a given target to correct the missile trajectory accordingly. Thus, the impact of the array shape on the error between the measured direction of arrival of the target echo and its true value is addressed. The Cramer-Rao lower bound is used to evaluate the theoretical minimum error. The model assumes that each element receives independently and allows therefore to analyse the potential of active 3D conformal arrays. Finally, the phase monopulse estimator is studied for 3Dconformal arrays whose quadrants do not have the same characteristics. A new estimator more adapted to non-identical quadrants is also proposed
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Melle, Christophe, David Chaimbault, Fabien Peleau, and Alain Karas. "A Tri-Band L, S, C Prime Focus Feed: Concept, Design and Performance." International Foundation for Telemetering, 2013. http://hdl.handle.net/10150/579680.
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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV<br>The flight test mission services need higher data rates due to increased system complexity and the need for more accurate, higher rate, and better data acquisition. The existing L or S band frequency spectrum allocation was a limiting factor to meet this increased data rate requirement. The World Radio-communication Conference (WRC 2007) attributed new additional frequency spectrum allocations in the C band for Aeronautical Mobile Telemetry (AMT). The international flight test community has taken this opportunity to immediately take advantage of the new C-band range 5091-5250MHz. This paper presents the multi-band feed product designed by the RF & Antenna Laboratory of ZODIAC DATA SYSTEMS company. This feed is foreseen to be used in prime focus configuration on any diameter parabola dish providing telemetry and tracking channels in three L, S, and C bands. Here, are described the concept and the technology achieved taking into consideration the performance and industrial constraints. Moreover, this contribution focuses on the electromagnetic simulations of radiating elements, the feed network and RF system integration. This paper is structured as follows: firstly, the objectives and the motivation for developing a prime focus feed which works in L, S, C bands are presented. In particular, the market constraints and approach to find the best solution satisfying the feed RF requirements, and mechanical constraints, such as weight, size and cost, are discussed. The second section describes the 5 step development cycle: principle and technology, design of the telemetry channels and tracking function, cohabitation of the different radiating elements, and problems of the channels isolations. The third section discusses the performance achieved using electromagnetic simulations. The fourth section talks about the integration of RF system feed. The paper concludes by discussing future work using the same concept that is applied to other telecommunication or telemetry frequency bands.
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Turkcu, Ozlem. "Development Of An Electronic Attack (ea) System In Multi&." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12609045/index.pdf.
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In this study, an expert system based EA and tracking system is developed
and the performances of these systems are optimized.
Tracking system consists of a monopulse tracking radar and a Multiple
Hypothesis Tracking (MHT) algorithm. MHT is modelled as a
measurement&<br>#8208<br>oriented approach, which is capable of initiating tracks. As
each measurement is received, probabilities are calculated for the
hypotheses and target states are estimated using a Kalman filter.
Range Gate Pull-Off (RGPO) is selected as an EA technique to be developed
because it is accepted to be the primary deception technique employed
against tracking radar. Two modes of RGPO technique<br>linear and
parabolic, according to time delay controller are modelled.
Genetic Algorithm (GA) Toolbox of MATLAB is used for the optimization
of these systems over some predetermined scenarios. It is observed that the
performance of the tracking radar system is improved significantly and
successful tracking is achieved over all given scenarios, even for closely
spaced targets. RGPO models are developed against this improved tracking
performance and deception of tracking radar is succeeded for all given
target models.
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Bárta, Jakub. "Implementace tvarování anténních příjmových svazků radaru v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400718.
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At the begining of this thesis radar theory and classification of radar systems is explained. Next part introduces antenna arrays with it’s parameters and possibilities. Main part contains design of digital beamformer on FPGA Cyclone V and it’s validation.
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Noyer, Jean-Charles. "Traitement non-linéaire du signal radar par filtrage particulaire." Phd thesis, Université Paul Sabatier - Toulouse III, 1996. http://tel.archives-ouvertes.fr/tel-00144042.
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On présente dans ce mémoire, une approche globale du probème de poursuite radar de cibles manoeuvrantes à faible rapport signal/bruit, par filtrage non-linéaire particulaire. Le filtrage particulaire, dont les bases ont été jetées dès 1989, permet d'aborder tous les cas où les non-linéarités présentes posent des difficultés de résolution aux techniques de filtrage dynamique. Il consiste à construire une approximation-mesure de la probabilité conditionnelle de la variable d'état à estimer par particules aléatoires, dont la dynamique est régie par le flot stochastique du système, et qui sont pondérées, via la règle de Bayes, par les mesures jusqu'à l'instant courant. Ce travail présente en premier lieu le traitement direct des mesures radar brutes en sortie d'échantillonneur/convertisseur. On montre notamment que la prise en compte de la dynamique de cible dans l'intégration cohérente des récurrences RADAR, permet d'atteindre les limites théoriques de détection, jusqu'alors inacessibles. Cela conduit notamment à revoir le problème de détection, car l'intégration d'un modèle de dynamique permet de relever le rapport signal/bruit équivalent, et minimise les problèmes de fausse alarme. En second lieu, on détaille le post-traitement des données de position délivrées par un radar de poursuite usuel, en particulier pour le modèle générique de missile à loi de navigation proportionnelle. On présente dans ce cas la résolution du problème de détermination de but visé, qui se pose en terme d'un test d'hypothèses sur le modèle de dynamique de l'assaillant.
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Modaresi, Mahyar. "System and Method for Passive Radiative RFID Tag Positioning in Realtime for both Elevation and Azimuth Directions." Thesis, KTH, Communication Systems, CoS, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-24562.
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<p>In this thesis, design and realization of a system which enables precise positioning of RFID tags in both azimuth and elevation angles is explained. The positioning is based on measuring the phase difference between four Yagi antennas placed in two arrays. One array is placed in the azimuth plane and the other array is perpendicular to the first array in the elevation plane. The phase difference of the signals received from the antennas in the azimuth array is used to find the position of RFID tag in the horizontal direction. For the position in the vertical direction, the phase difference of the signals received from the antennas in the elevation plane is used. After that the position of tag in horizontal and vertical directions is used to control the mouse cursor in the horizontal and vertical directions on the computer screen. In this way by attaching one RFID tag to a plastic rod, a wireless pen is implemented which enables drawing in the air by using a program like Paint in Windows. Simulated results show that the resolution of the tag positioning in the system is in the order of 3mm in a distance equal to 0.5 meter in front of the array with few number of averaging over the received phase data. Using the system in practice reveals that it is easily possible to write and draw with this RFID pen. In addition it is argued how the system is totally immune to any counterfeit attempt for faked drawings by randomly changing the transmitting antenna in the array. This will make the system a novel option for human identity verification.</p><br>QC 20100920
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Bandeira, Gláucia de Lima. "Efeitos da contramedida de despistamento "Cross-Eye" em radares monopulso." Instituto Tecnológico de Aeronáutica, 2004. http://www.bd.bibl.ita.br/tde_busca/arquivo.php?codArquivo=614.
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Mostram-se as principais características do radar monopulso salientando-se como é feita a medida da localização do alvo utilizando-se o "canal diferença" e o "canal soma". Faz-se um levantamento sucinto das contramedidas utilizadas contra os radares monopulso, destacando-se as vantagens e desvantagens das principais técnicas existentes. Apresentam-se os fundamentos da técnica de contramedida eletrônica de despistamento cruzado (Cross-Eye) usada contra radares monopulso. A técnica "Cross-Eye" usa a distorção de onda provocada por dois interferidores (jammers) que se localizam nas pontas das asas do avião, criando um alvo falso mais atrativo que o alvo real para o radar vítima. Foi modelado o sistema de contramedida eletrônica "Cross-Eye", enfatizando-se o campo resultante dos dois jammers e a sua relação com o ângulo de apontamento indicado pelo radar monopulso. Na simulação realizada foi considerada a aeronave EMB-314, num determinado cenário, onde se pode confirmar a eficiência da técnica sob determinadas limitações explicitadas nesse trabalho.
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Hunsinger, Frédéric. "Méthode de validation globale pour les systèmes monopuces." Grenoble INPG, 2006. http://www.theses.fr/2006INPG0017.
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LES TECHNOLOGIES ACTUELLES PERMETTENT L'INTEGRATION DE NOMBREUX COMPOSANTS SUR UNE SEULE PUCE. CES SYSTEMES APPELES SYSTEMES MONOPUCE (SOC) SONT UN ASSEMBLAGE HETEROGENE DE COMPOSANTS LOGICIELS El MATERIELS. LA PRESSION POUR LA QUALITE ET LES DELAIS DE MISE SUR LE MARCHE FONT DE LA VALIDATION DE CES SYSTEMES UN POINT CLE (70% DU TEMPS DE CONCEPTION). LA VERIFICATION DE L'INTEGRATION DES SOCS, REALISEE PAR SIMULATION, CONSISTE A VALIDER LES FONCTIONNALITES DES COMPOSANTS ET LEURS INTERCONNEXIONS DANS LI SYSTEME. ELLE EST COURAMMENT EFFECTUEE PAR L'EXECUTION DE PROGRAMMES LOGICIELS SUR LES PROCESSEURS EMBARQUES. CES PROGRAMMES SONT GENERALEMENT CONÇUS A BAS NIVEAU (ASSEMBLEUR, C) CE QUI REND DIFFICIL LA REALISATION DE SCENARII DE TEST COMPLEXES NECESSITANT DES MECANISMES DE SYNCHRONISATION SOPHISTIQUES. DE PLUS, LEUR UTILISATION N'EST PAS SUFFISANTE POUR EFFECTUER LA VALIDATION COMPLETE D'UN SYSTEME. AINSI, LES CONTRIBUTIONS PERMETTANT D'ACCELERER LA VALIDATION SONT: (1) LA DEFINITION D'UNE METHODOLOGIE DE VALIDATION UTILISANT PLUSIEURS TECHNIQUES DE VERIFICATION ADRESSANT LES PROBLEMES SPECIFIQUES AUX SOCS; (2) LA DEFINITION D'UNE NOUVELLE METHODE DE VERIFICATION DE L'INTEGRATION S'APPUYAN SUR DES PROGRAMMES DE TEST LOGICIEL DE HAUT NIVEAU REPOSANT SUR UN SYSTEME D'EXPLOITATION. CETTE METHODE A ETE VALIDEE SUR UN SYSTEME MONOPUCE INDUSTRIEL DESTINE AUX APPLICATIONS DE TELEVISION NUMERIQUE HAUTE DEFINITION<br>ACTUAL TECHNOLOGIES FACILITATE INTEGRATION OF MANY COMPONENTS ONTO A SINGLE CHIP. THESE SYSTEMS CALLED SYSTEM ON CHIP (SOC) ARE A HETEROGENEOUS ASSEMBL Y OF HARDWARE AND SOFTWARE COMPONENTS. AS QUALITY AND TIME TO MARKET CONSTRAINTS OF SOCS INCREASE, VALIDATION BECOMES THE KEY POINT (70% OF THE OVERALL DESIGN PROCESS). VERIFICATION OF THE INTEGRATION IS DONE THROUGH SIMULATION AND CONSISTS TO CHECK COMPONENT FUNCTIONALITIES AND INTERCONNECTIONS lN THE SYSTEM. IT IS OFTEN ACHIEVED BY EXECUTING SOFTWARE PROGRAMS ON THE EMBEDDED PROCESSORS. PROGRAMS ARE GENERALL Y DESIGNED AT LOW LEVEL (ASSEMBL Y, C) WHICH MAKES DIFFICUL T TO DESIGN COMPLEX TEST SCENARIOS THAT NEED SOPHISTICATED SYNCHRONISATION SCHEMES. FURTHERMORE, THEIR USE DOES NOT ENABLE PERFORMING THE COMPLETE SYSTEM VALIDATION. THE MAIN CONTRIBUTIONS OF THIS WORK FOR ACCELERATING VALIDATION ARE: (1) THE DEFINITION OF A VALIDATION METHODOLOGY USING DIFFERENT VERIFICATION TECHNIQUES TARGETING SPECIFIC SOC ISSUES; (2) THE DEFINITION OF A NEW VERIFICATION METHOD OF THE INTEGRATION BASED ON HIGH LEVEL SOFTWARE TEST PROGRAMS USING AN OPERATING SYSTEM. THIS METHOD WAS VALIDATED ON AN INDUSTRIAL SOC AIMED AT HIGH DEFINITION TELEVISION APPLICATIONS
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Muller, Olivier. "Architectures multiprocesseurs monopuces génériques pour turbo-communications haut-débit." Phd thesis, Université de Bretagne Sud, 2007. http://tel.archives-ouvertes.fr/tel-00545236.
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Les applications dans le domaine des communications numériques deviennent de plus en plus complexes et diversifiées. En témoigne l'apparition des turbo-communications qui représentent la généralisation du principe de processus itératif introduit par les turbocodes. La mise en œuvre de systèmes de turbo-communications, communément appelés turbo- récepteurs, est devenue primordiale pour atteindre les performances aujourd'hui exigées en terme de qualité de transmission. Des architectures matérielles dédiées implantant ces systèmes ont déjà vu le jour dans plusieurs équipes de recherches académiques et industrielles. Cependant, pour des exigences de flexibilité de l'implantation (pour supporter les évolutions d'une norme ou des applications multi-standards), de qualité de transmission et de haut débit de communication, des architectures multiprocesseurs adéquates deviennent incontournables. Le sujet de cette thèse porte sur la mise en œuvre d'une plate-forme architecturale multiprocesseur générique adaptée aux turbo-récepteurs et plus particulièrement aux turbo-décodeurs convolutifs. Ainsi, le sujet gravite autour de deux axes de recherche : un axe algorithmique autour des systèmes de turbo-décodage et un autre autour de la conception numérique ces derniers. Sur l'axe algorithmique, ces travaux présentent une étude approfondie des algorithmes de turbo-décodage autour des techniques de parallélisme. Les fondations de cette étude reposent sur une classification des parallélismes existants qui distingue les parallélismes selon leurs granularités et leurs pouvoirs d'accélération. L'analyse de cette classification a révélé la nécessité d'investiguer les parallélismes de sous-bloc et de décodeur composant pour améliorer l'efficacité de leur mise en œuvre. Les recherches menées mettent en évidence que le parallélisme de sous-bloc s'avère plus efficace avec la technique d'initialisation par passage de message. Nous avons également montré que le parallélisme de décodeur composant, grâce à la technique du décodage combiné ou « shuffled decoding » , améliore l'efficacité des architectures de turbo-décodeur fortement parallèles et que cette dernière peut être optimisée en contraignant la conception de l'entrelaceur du turbocode. Sur l'axe architectural, ces avancées algorithmiques ont été mises à profit dans une plate-forme multiprocesseur qui exploite au mieux les compromis matériel/logiciel (i .e. performance/flexibilité) tant au niveau du calcul qu'au niveau des communications. Au niveau du calcul, un processeur ASIP (Application-Specific Instruction-set Processor) dédié au décodage des codes convolutifs a été proposé et conçu de manière à ne fournir que la flexibilité désirée, tout en conservant des performances élevées grâce à un chemin de données fortement parallélisé. Au niveau des communications, la plate-forme a été dotée de réseaux sur puce dédiés pour assurer la bande passante nécessaire aux échanges itératifs d'information. Cette plate-forme multi-ASIP flexible a été prototypée sur une carte d'émulation intégrant des circuits FPGA. La flexibilité de la plate-forme proposée autorise le support de tous les standards de turbocodes convolutifs actuels et émergeants et peut trouver un intérêt industriel dans les domaines des télécommunications mobiles et satellitaires, de la diffusion de contenu ou de l'Internet haut-débit.
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Muller, Olivier David. "Architectures multiprocesseurs monopuces génériques pour turbo-communications haut-débit." Lorient, 2007. http://www.theses.fr/2007LORIS106.
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Oyamada, Marcio Seiji. "Estimation de performance du logiciel en systèmes multiprocesseur monopuces." Grenoble INPG, 2007. https://tel.archives-ouvertes.fr/tel-00195230.
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Actuellement, la complexité des systèmes embarqués nécessite des nouvelles méthodologies de développement. Des méthodologies au niveau système sont proposées pour traiter la complexité, utilisant comme point de départ des descriptions de plus haut niveau qui au niveau transfert de registre (register transfer level - RTL). Les outils d’estimation de performance sont une importante partie des méthodologies au niveau système, parce qu’ils aident dans les décisions de projet dans les étapes initiales. Cette thèse propose des méthodes d’estimation de performance intégrées dans le flot de conception ROSES. En raison de l’augmentation du nombre des processeurs intégrés dans une puce, on nécessite de plus en plus des outils pour l’estimation de performance du logiciel. Pour guider la sélection du processeur au niveau de la spécification, on propose l’utilisation des réseaux neuronaux pour estimer rapidement la performance du logiciel. Après le raffinage des interfaces matériels et logiciels, on utilise des prototypes virtuels pour analyser la performance de l’architecture au niveau de bus fonctionnel. Le prototype virtuel est généré automatiquement a partir de la description ROSES, en permettent l’analyse de performance intégré des composants logiciel et matériel. La méthodologie proposée dans ce travail a été évalué par une étude de cas d’un encodeur MPEG4<br>Actuellement, la complexité des systèmes embarqués nécessite des nouvelles méthodologies de développement. Des méthodologies au niveau système sont proposées pour traiter la complexité, utilisant comme point de départ des descriptions de plus haut niveau qui au niveau transfert de registre (register transfer level - RTL). Les outils d’estimation de performance sont une importante partie des méthodologies au niveau système, parce qu’ils aident dans les décisions de projet dans les étapes initiales. Cette thèse propose des méthodes d’estimation de performance intégrées dans le flot de conception ROSES. En raison de l’augmentation du nombre des processeurs intégrés dans une puce, on nécessite de plus en plus des outils pour l’estimation de performance du logiciel. Pour guider la sélection du processeur au niveau de la spécification, on propose l’utilisation des réseaux neuronaux pour estimer rapidement la performance du logiciel. Après le raffinage des interfaces matériels et logiciels, on utilise des prototypes virtuels pour analyser la performance de l’architecture au niveau de bus fonctionnel. Le prototype virtuel est généré automatiquement a partir de la description ROSES, en permettent l’analyse de performance intégré des composants logiciel et matériel. La méthodologie proposée dans ce travail a été évalué par une étude de cas d’un encodeur MPEG4
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Petkov, Ivan Doynov. "Conception des systèmes monopuce multiprocesseur : de la simulation vers la réalisation." Université Joseph Fourier (Grenoble), 2006. https://tel.archives-ouvertes.fr/tel-00011618.
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La complexité des systèmes monopuce est devenue telle qu'il est impossible de continuer à les concevoir au niveau RTL, où il faut préciser chaque détail du comportement des composants. Le grand défi en ce moment pour les ingénieurs est de réussir à maîtriser la complexité lors de la conception de ces systèmes et d'arriver à une conception rapide des systèmes monopuce sous de fortes contraintes de qualité et de temps de développement. Pour dépasser ce défi, les nouvelles méthodes de conception sont basées sur des concepts d'abstraction de haut niveau. La problématique de cette thèse est de comprendre les difficultés de la conception des systèmes sur puce commençant à un niveau d'abstraction élevé et d'essayer de trouver des méthodes ou techniques pour faciliter et accélérer leur développement. Nous nous sommes posé comme objectif d'étudier différentes méthodologies de prototypage des systèmes monopuce et les problèmes liés avec les niveaux d'abstraction et les outils de conception. Les contributions apportées par cette thèse, trouvent place dans la conception des systèmes multiprocesseurs hétérogènes à l'étape d'intégration de matériel et de logiciel à partir d'un modèle abstrait et dans le prototypage des applications monopuce multiprocesseur<br>The design of the system on chip at RTL level is no longer practical approach due to the rising complexity of the circuits. It became difficult to specify all details of the behavior of each component and to validate the entire system at RTL level. The challenge in our days for the engineers is to succeed to control the complexity when designing these systems and to speed up the design of the systems under strong quality constraints and time to market pressure. To deal with this challenge, the new methods of design are based on concepts of high-level abstraction of the system components. The goals of this thesis are to understand the difficulties of the systems on chip design starting on a high level of abstraction and to try to find methods or techniques to accelerate their development. We focused our objectives to study different methodologies for prototyping of system on chip and to study the different types of components used at different levels of abstraction and the relations between them during prototyping. The contributions of this thesis, find place in the design of heterogeneous multiprocessors systems on chip at the stage of integration of hardware and software starting from an abstract model to the prototyping of the multiprocessor system on chip
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Bacivarov, Iuliana Beatrice. "Evaluation des performances pour les systèmes embarqués hétérogènes, multiprocesseur monopuces." Grenoble INPG, 2006. https://tel.archives-ouvertes.fr/tel-00086762.
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Les systèmes embarqués multiprocesseur monopuces (Multi-Processor System-on-Chip, MPSoC) visent l'intégration des sous-systèmes variés, matériels et logiciels, sur une seule puce. Ainsi, l'hétérogénéité et les contraintes imposées pour la mise sur le marché rendent l'analyse en vue de l'évaluation des performances et de l'optimisation de ces systèmes très complexes. L'évaluation des performances est une étape clef dans n'importe quel flot de conception. En se basant sur les résultats de l'évaluation des performances, il est possible de prendre des décisions et de réaliser des compromis pour l'optimisation du système global. La littérature prouve qu'une grande partie du temps de conception est passée dans l'évaluation des performances. De plus, les itérations dans le flot de conception deviennent prohibitives pour des systèmes complexes. Par conséquent, la réalisation des MPSoCs à rendement élevé est un défi. La solution est fortement liée à la disponibilité des méthodes rapides et précises pour l'évaluation des performances. Dans cette thèse, le terme « performances » est limité aux performances des temps d'exécution pour la réalisation finale du système. L'aspect temporel est intensivement analysé pour la validation des systèmes temps-réel et l'optimisation des sous-ensembles d'interconnexion. Nous avons également considéré la vitesse de la méthode proposée d'évaluation des performances, car les temps d'évaluation peuvent devenir prohibitifs pour des systèmes MPSoC complexes. Notre principale contribution est de définir une méthodologie globale d'évaluation des performances pour les systèmes MPSoC. Nous avons également orienté notre recherche vers les performances de l'exécution du logiciel. On a considéré l'évaluation des performances pour un modèle de haut niveau d'abstraction, afin d'avoir une vitesse élevée d'évaluation. De plus, on a inclus des annotations des temps d'exécution, afin d'avoir une bonne précision d'évaluation<br>Multi-processor system-on-chip (MPSoC) is a concept that aims at integrating multiple subsystems on a single chip. Systems that put together complex HW and SW subsystems are difficult to analyze and even harder to optimize. Performance evaluation is a key step in any design, allowing for decisions and trade-offs, in view of overall system optimization. The literature shows that a large part of the design time spent in performance evaluation, and iterations become prohibitive in complex designs. Therefore, the challenge of building high-performance MPSoCs is closely related to the availability of fast and accurate performance evaluation methods. In our work, “performance” is restricted to time related performances of the final architecture. The timing aspect is intensively analyzed for the validation of real-time systems and the optimization of interconnect subsystems. We are also concerned with the speed of any proposed performance evaluation method, as evaluation times may become prohibitive for complex MPSoC designs. Our main objective is to define a global performance evaluation methodology for MPSoC. We also orient our research towards software performance modeling, maintaining a high level of abstraction, in order to have a high evaluation speed, and including timing annotations, in order to have good evaluation
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Pieralisi, Lorenzo. "Modélisation de réseau de communication flexible pour les systèmes monopuces." Grenoble INPG, 2006. https://tel.archives-ouvertes.fr/tel-00164027.
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Les systèmes monopuce deviennent de plus en plus complexes, intégrant composants à la fois logiciels et matériels dans le but de procurer una capacité de calcul croissante aux applications embarquées. L'interconnexion des composants devient un élément crucial de la conception ; le concept de réseau sur puce s'impose comme élément de communication pour les architectures d'interconnexion des systèmes de la prochaine génération. Les principales contributions de cette thèse sont représentées par : (1) le développement d'un simulateur de réseaux sur puce complet, (2) l'intégration de plusieurs environnements de simulation hétérogènes et (3) une connaissance complète des concepts sous-jacents aux réseaux sur puce qui a apporté une contribution importante au développement de STNoC, la nouvelle technologie d'interconnexion développée au sein de STMicroelectronics. L'environnement de modélisation réalisé a été utilisé pour l'étude de deux systèmes monopuce réels développés par STMicroelectronics orientés vers la télévision numérique à très haute définition (HDTV)<br>The Multi-Processors Systems on a chip (MPSoC) era is bringing about many new challenges for systems design in terms of computation and communication subsystems complexity. Interconnection systems became a pivotal component of the overall design, providing designers with advanced communication features such as split transactions, atomic operations and security adds-on. Momentum is building behind Networks on-chip (NoC) as future on-chip interconnection technology. Networks on-chip role is about to take over shared busses whose scalability properties are already a major bottleneck for system design. Modeling of on-chip network is an exacting work ; networks models must be fast, accurate and they have to sport standard interfaces. The main contributions of this work to networks on-chip design and implementation are : (1) the development of a brand new, full-fledged network on-chip simulator based on OCCN, an open-source framework for NoC modeling developed within sourceforge available at http://occn. Sourceforge. Net, (2) the successful integration of heterogeneous simulation environments in extremely complex platforms used to benchmark real STMicroelectronics SoCs and (3) thorough understanding and contribution to the design of STNoC, the new interconnection technology developed within AST Grenoble lab of STMicroelectronics for future generation systems. The modeling environment has been used to benchmark two STMicroelectronics systems on-chip for High Definition digital Television (HDTV)
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Piel, Géraldine. "Contribution à la mise en œuvre d’une plate-forme de simulation d’un système radar : application à un radar automobile d’aide à la conduite." Brest, 2007. http://www.theses.fr/2007BRES2050.
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Compte tenu du développement de la circulation routière et de la nécessité d'une sécurité accrue, les systèmes pour véhicules intelligents se sont considérablement développés ces dernières années. Ces systèmes détectent l'environnement de conduite pour assister le conducteur en vue d'un fonctionnement optimal du véhicule. L'accent est mis sur l'aspect tactique de la conduite (moteur) par opposition à l'aspect stratégique (choix d'itinéraire). Un élément essentiel de ce développement est le radar ACC d'aide à la conduite qui a été développé dans la bande 76-77GHz. Afin de se placer parmi les leaders mondiaux des concepteurs radars ACC, Autocruise (société implantée en Bretagne sur le Technopôle Brest Iroise) doit développer de nouveaux concepts radars. Face à ce système complexe, il est difficilement envisageable de proposer de nouvelles solutions sans avoir recours à un outil de simulation qui permette de prendre en compte le système dans sa globalité. Cet outil passe par la mise en oeuvre d'une plate-forme de simulation, efficace et fiable, pour laquelle on modélise précisément les sous-ensembles analogiques et le traitement du signal associé. Seule une maîtrise forte de cette démarche de modélisation pourra permettre à terme une meilleure maîtrise des coûts voire de l'évolution des fonctionnalités du radar développé. Il faut donc imaginer utiliser conjointement l'ensemble des outils de simulation à disposition : simulations circuit, électromagnétique 2,5D et 3D, système pour pouvoir rendre compte du fonctionnement global du radar. Une première plate-forme de ce type a été développée lors de cette thèse, selon cette démarche de modélisation et de simulation globale<br>Driving assistance systems have become more and more present over the past few years with the steady increase in traffic and the need for better road safety. These systems are designed to detect movement in the surrounding road environment in order to assist drivers as much as possible and help them make the best use of their vehicles. They focus on tactics (steering wheel, brakes, acceleration, etc. ) rather than strategy (choice of routes, etc. ). One of the main elements of this development is the 76-77 GHz ACC radar sensor. Autocruise, a firm located in Brittany, France (and more specifically on the industrial site of Technopôle Brest Iroise), develops new radar concepts with the aim of becoming one of the world leaders in the field of ACC designers. Suggesting new solutions is proving difficult without using a simulation tool which would help us grasp all aspects of this complex system. Such a tool involves implementing an efficient and reliable simulatior platform where analogue subsets and their associated signal processing have been modelled. Better control c costs (and possibly better evolution of radar functionalities) can only be achieved in the long term through mastering this modelling. This is why the available simulation tools are used jointly one with another: circuit simulations, electromagnetic simulations, 2. 5D and 3D and system simulations that give an overview of the operating ACC radar. This thesis presents a platform of this kind for the first time following the abovementioned concept of global simulation and modellinq
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Baghdadi, Amer. "Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des application spécifiques." Grenoble INPG, 2002. http://www.theses.fr/2002INPG0028.
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Sasongko, Arif. "Prototypage basé sur une plateforme reconfigurable pour la vérification des systèmes monopuces." Université Joseph Fourier (Grenoble), 2004. http://www.theses.fr/2004GRE10161.
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La tendance dans la conception des systèmes monopuces est à l'augmentation de la complexité et de l'hétérogénéité de tels systèmes, appelés systèmes monopuces. Ces systèmes sont sur un marché concurrentiel, et l'arrivée rapide du produit sur le marché est très importante. Ceci nous entraîne vers les deux problèmes traités dans ce travail de thèse : s'assurer que le système est correct avant sa fabrication et accélérer la conception. Ce prototypage permet de vérifier rigoureusement les systèmes grâce à une vitesse élevée, et de tester le système dans son environnement d'utilisation. Il accélère aussi la conception en permettent le développement de certaines couches logicielles avant que le système soit fini. Pour obtenir rapidement un prototype à partir d'une description RTL d'une application, nous proposons un flot de prototypage basé sur une plateforme reconfigurable. Ce flot est composé de quatre étapes : allocation, configuration de la plateforme, adaptation de l'application, et génération du code. Dans l'allocation, les concepteurs associent chaque partie de l'architecture à un nœud de prototypage de la plateforme. Ces associations indiquent sur quelles parties de la plateforme reconfigurable sont réalisées les parties de l'architecture de l'application. La configuration est la réorganisation de la plateforme reconfigurable. L'adaptation consiste à modifier l'application pour satisfaire aux caractéristiques de la plateforme reconfigurable. Enfin, la génération du code est un processus standard tel que la compilation et l'édition de lien des logiciels, la synthèse logique, le placement sur FPGA, et le routage. Ce flot a été validé en réalisant le prototypage des applications VDSL et DivX. La plateforme utilisée est une plateforme ARM Integrator avec une carte mère, quatre modules processeurs ARM, et d'un module FPGA communiquant à travers un bus AMBA AHB. Une expérience de co-émulation a également été réalisée pour explorer les difficultés et les avantages de cette technique. L'avantage principal est qu'on peut profiter de l'observabilité de la simulation et de la vitesse de l'émulation. Ce travail de thèse montre que l'on peut obtenir rapidement un prototype en utilisant le flot propose sur une plateforme reconfigurable et aussi faciliter le développement des parties logicielles pour accélérer la conception. La configurabilité de plateforme de prototypage et l'intégration du flot de prototypage sur un flot de conception des systèmes restent des problématiques à approfondir<br>The technology facilitates integration of many components onto a single chip to achieve performances and requirements needed by the application. The complexity and the heterogeneity of this system, called system-on-chip (SoC), tend to increase. The market of SoC is very competitive, so early appearance on the market is very important. Furthermore, the cost chip fabrication is very high, therefore, detecting a bug after fabrication can cause unacceptable overhead. These facts bring us to two problems addressed in this thesis: assuring the correctness of the system and accelerating the design process. After evaluating several verification techniques, we conclude that prototyping based on reconfigurable platform is a solution for the two problems mentioned. This prototyping allows us to verify rigorously the system since the speed which is very high. It allows us also to test the system in his operating environment. Furthermore, prototyping accelerate the design process by allowing development of several software layers before the chip fabrication. To obtain quickly a prototype from RTL description of the application, we propose a prototyping flow based on reconfigurable platform. This flow consists of four steps: assignment, configuration, adaptation, and code generation. In the assignment step, the designer associates each part of the architecture to the prototyping node of the prototyping platform. These associations indicate parts of the prototyping platform which will implement the components of the application. Configuration is reorganization of the reconfigurable platform. Adaptation consists of modify the application to satisfy constraints of the platform. This step is needed when the platform can not be configured to adapt the requirements of the application. Finally, the code generation is standard process such as compilation, logic synthesis, and placement and route. This flow is validated by realizing two prototypes of application: VDSL and DivX encoder. In these experiments, we used ARM Integrator platform. This platform consists of a main board, four processor boards, an FPGA board. These boards communicate each others through bus AMBA-AHB. A co-emulation experiment is also performed using this platform for exploring the difficulties and the advantages of this technique. The main advantage is that we can obtain the observability of simulation while preserving the speed of emulation. This PhD work shows that we can obtain a prototype using the proposed flow on a reconfigurable platform and also facilitate the development the software part to accelerate the design process. The configurability of the platform and the integration of the prototyping flow with design flow of the SoC are left as subjects to be treated
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Meftali, Samy. "Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs monopuce." Université Joseph Fourier (Grenoble), 2002. http://www.theses.fr/2002GRE10106.
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Gharsalli, Ferid. "Conception des interfaces logiciel-matériel pour l'intégration des mémoires globales dans les systèmes monopuces." Grenoble INPG, 2003. http://www.theses.fr/2003INPG0055.
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Grasset, Arnaud. "Synthèse des interfaces de communication dans la conception des systèmes monopuces : de la spécification à la génération automatique." Grenoble INPG, 2006. http://www.theses.fr/2006INPG0004.
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L'intégration dans une seule puce de un ou plusieurs processeurs et de composants matériels spécifiques permet le développement de systèmes complexes appelés systèmes monopuce. L'accroissement de la complexité de ces systèmes fait de la maîtrise de leurs conceptions un défi à relever par les concepteurs. La réutilisation des composants dans ces systèmes est rendue difficile par leur hétérogénéité, notamment en terme de protocole et d'interface physique. Une solution est offerte par l'abstraction des communications entre les composants dans un modèle du système. Un flot de conception doit alors permettre de passer de cette représentation abstraite au circuit final dans lequel les composants du système sont connectés par des interfaces de communication à un réseau de communication. Les contributions apportées par cette thèse à cette méthodologie sont la définition d'un modèle de spécification des interfaces de communication basé sur un graphe de dépendances de services, ainsi qu'une méthodologie pour la génération automatique d'interfaces de communication pour les systèmes monopuces. Cette méthodologie a amené au développement d'un outil de génération automatique de ces interfaces. L'approche proposée a été validée à travers deux expérimentations : une interface en charge de la détection d'erreurs de transmissions et une interface avec un bus AMBA pour la réalisation de primitives MPI<br>Integration in a single chip of one or more processors and specific hardware components allows the development of complex system, called systems-on-chip. With the increasing complexity of these systems, mastering of their designs is a challenge to take up by the designers. The re-use of the components in these systems is difficult due to their heterogeneity in terms of protocol and physical interface. A solution is the abstraction of the communications between the components in a system model. A design flow leads from this abstract representation to the final circuit where the components of the system are connected by network interfaces to a communication network. The contributions of this thesis are the definition of a specification model of the network interfaces based on a service dependency graph, as well as a methodology for the automatic generation of network interfaces for systems-on-chip. This methodology has driven to the development of an automatic generation tool of these interfaces. Two experiments allowed testing the approach with: an interface in charge of the error detection of transmissions and an interface with an AMBA bus for the realization of MPI primitives
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Le, Moigne Rocco. "Modélisation et simulation basée sur systemC des systèmes monopuces au niveau transactionnel pour l'évaluation de performances." Nantes, 2005. http://www.theses.fr/2005NANT2040.
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L'évolution rapide des technologies microélectroniques a entraîné l'apparition d'une nouvelle génération de composants sur le marché : les systèmes monopuces. La conception de ces nouveaux composants est complexe. De plus, il faut en permanence augmenter la productivité en conception des systèmes en vue d'accélérer la conception et la mise sur le marché d'un produit. Ces contraintes conduisent les concepteurs à étudier très tôt les performances des systèmes par modélisation et simulation. Ainsi, l'objectif global de cette thèse est de proposer aux concepteurs de systèmes un ensemble de modèles de haut niveau associé à un outil informatique leur permettant de réaliser la co-simulation de systèmes matériels/logiciels très tôt dans le cycle de conception. L'ensemble des modèles développés ont été intégrés dans la bibliothèque de simulation SystemC de CoFluent Studio™, produit commercial de la société CoFluent Design. Ce travail a été réalisé dans le cadre du projet MEDEA+ A502 MESA<br>The fast evolution of microelectronic technologies and their ever-improving integration capacities made possible the appearance of a new generation of components on the market: the “System-on-Chip”. The complexity involved when designing these new components and the permanent need to increase the productivity of the system design process in order to reduce the time-to-market leads designers to raise the level of abstraction of their simulation models. Thus, our goal is to provide a set of high-level models and software tools enabling designers to conduct very early in the design process the HW/SW co-simulation of systems. All models developed in this thesis are integrated to the SystemC simulation library of CoFluent Design's CoFluent Studio™ software environment. This work was done in the context of the MEDEA+ A502 MESA project
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Bayer, Hendrik [Verfasser], Matthias [Akademischer Betreuer] Hein, Matthias [Gutachter] Geissler, and Enrico [Gutachter] Reiche. "Nachführbare Antennen für die mobile Satellitenkommunikation auf Basis des Multimode-Monopuls-Prinzips / Hendrik Bayer ; Gutachter: Matthias Geissler, Enrico Reiche ; Betreuer: Matthias Hein." Ilmenau : TU Ilmenau, 2017. http://d-nb.info/1178142590/34.
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Elouardi, Abdelhafid. "Evaluation des rétines électroniques pour une définition architecturale d'un système monopuce (SoC) dédié à la vision embarquée." Paris 11, 2005. http://www.theses.fr/2005PA112055.
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Pour définir une architecture d'un système monpuce dédié à la vision embarquée, le travail de thèse s'est appuyé sur quatre modèles de systèmes de vision différents deux modèles utilisant des rétines qui peuvent assurer certains prétraitements d'images de bas niveau grâce aux opérateurs intégrés dans le même circuit du capteur imageur et deux autres modèles utilisant des capteurs CMOS/APS, des circuits reprogrammables types FPGA et un microporocesseur spécifique. Pour ces modules, une grande partie des traitements est réalisée sur le microprocesseur. Cet ensemble représente alors une plate-forme expérimentale pour l'instrumentation et l'évaluation de procédures de contrôle et de traitement des opérateurs rétiniens. La mise en œuvre de ces familles d'architectures nous a permis d'acquérir un niveau d'expertise dans le domaine de l'évaluation et l'instrumentation des systèmes de vision. Au travers de cette thèse, nous avons évalué plus profondément le système à base de la rétine PARIS1. L'évaluation a pris en compte les aspects suivants la programmabilité, l'évaluation de la puissance de calcul, l'énergie consommée et les problèmes d'embarquabilité. Cette étude a permisde définir une approche A3 (Adéquation, Algorithme, Architecture) pour un système de vision monopuce (System on Chip), doté des caractéristiques d'un système de vision intelligent et reconfigurable. Elle a eu aussi pour objectif de définir un compromis et des critères de sélections architecturales des opérateurs à intégrer sur le capteur en fonction des différents algorithmes à implanter et en prenant en considération les besoins de l'application envisagée : vision pour l'automobile<br>One of the solutions to resolve the computational complexity of image processing is to perform some low-level computations on the sensor focal plane. This work is built to get a general conclusion on the aptitude of retinas, as smart sensors, to become potential candidate for a system on chip reaching an algorithm/architecture adequacy. The study showed why retinas are advantageous, what elementary functions and/or operators should be added on chip and how to integrate image-processing algorithms (i. E. How to implement the smart sensor). The thesis includes recommendations on system-level architectures and discusses the limitations of the implementation of smart retinas which are categorized by the nature of image processing algorithms. To sustain the study, we have proposed a system-level architecture and a design methodology to integrate image processing within a CMOS retina on a single chip. This architecture model highlights a compromise between versatility, parallelism, processing speed and resolution. Our solution aims to take also into account the algorithms response times while reducing energy consumption to increase the system performances for embedding reasons. We have done a comparison relating four different architectures dedicated for a vision system on chip. Two models implement APS imagers and a microprocessor. A third model involves the same processor with a CMOS retina that implements hardware operators and analog microprocessors. The fourth model integrates a second CMOS retina and an embedded computer. The comparison is related to image processing speed, processing reliability, programmability, precision, subsequent stages of computations and power
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Samyn, Mickaël. "Une simulation fonctionnelle d'un système monopuce dédié au traitement du signal intensif : une approche dirigée par les modèles." Lille 1, 2005. https://ori-nuxeo.univ-lille1.fr/nuxeo/site/esupversions/9eec6f23-301f-4b30-b5b0-73be4f4ad924.
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Ces quelques dernières années, le monde de la conception des systèmes monopuces a subi un très grand bouleversement. D'une part, la puissance des nouvelles applications fait que les nouveaux systèmes doivent incorporer de nombreuses ressources hétérogènes. D'autre part, les nouvelles technologies permettent d'incorporer de plus en plus de composants sur une même surface de silicium. Les méthodes de conception actuelles, basées sur l'expérience des concepteurs pour choisir les différentes architectures, ne permettent plus de suivre l'évolution des technologies, d'autant plus que la durée de vie des systèmes est de plus en plus courte, alors que le temps de mise sur le marché et le coût de conception ne font qu'augmenter. L'approche adoptée dans cette thèse s'inscrit dans un projet global de co-modélisation et co-conception appelé Gaspard. Elle vise à remédier, même partiellement à ces nouvelles exigences. La méthodologie est basée sur les principes de l'architecture dirigée sur les modèles (MDA), et plus particulièrement la partie traitant de la simulation et de l'analyse de performances à un haut niveau d'abstraction. Dans cette thèse, un métamodèle, permettant la modélisation des systèmes, est décrit. Ensuite, une méthodologie de génération de code, utilisant des moteurs de transformations, est utilisée afin de générer le code nécessaire à la simulation du système modélisé. Enfin, une présentation des différents critères retenus pour l'estimation du système est faite.
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Jin, Ling. "Contribution à l’étude de modules radio ultra faible consommation pour réseaux de capteurs en gamme millimétrique." Thesis, Lille 1, 2010. http://www.theses.fr/2010LIL10019/document.
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L’objectif de ces travaux était d’étudier la faisabilité d’un module radio ultra large bande en gamme millimétrique destiné à des applications de réseaux de capteurs ultra faible consommation pour des applications domotiques, industrielles ou environnementales. Aujourd'hui, l'usage du canal 60 GHz radio est attrayante pour les applications de réseaux de capteurs car elle bénéficie d'une ressource spectrale large (7GHz entre 57GHz et 64GHz), d’une miniaturisation des modules radio, de l'interférence limitée avec les autres systèmes de communication. Après avoir comparé plusieurs technologies de couche physique nous avons opté pour un module radio en technique impulsionnelle ultra large bande transposée en gamme millimétrique autour de 60GHz, qui présente une faible consommation d'énergie, une faible complexité de l'architecture radio, une faible sensibilité à la non-linéarité de l'émetteur, une robustesse aux effets de propagation multiple et une résolution temporelle élevée pour des applications de localisation. Nous avons ensuite montré que pour des réseaux de moyenne densité et à faible débit numérique les approches S-MAC et Zigbee sont prometteuses demandant à être encore améliorées dans la mesure où il n’existe pas à ce jour de normes établies pour les liaisons radio entre nœuds de réseau de capteurs. De plus, afin de ne pas complexifier l’architecture globale du module radio et de diminuer la consommation nous avons choisi une architecture ULB transposée en gamme millimétrique avec une modulation de type OOK et une solution de démodulation basée sur la détection non cohérente de l'énergie Pour valider le principe, nous avons conçu deux circuits utilisant la technologie AsGa 0.1um pHEMT de chez OMMIC. L’un est un émetteur qui fonctionne à 30GHz et l’autre fonctionne à 60GHz. Dans la dernière partie, nous présentons la conception de l’émetteur du nœud de capteur en technologie CMOS 65nm SOI composé d’un oscillateur à 30 GHz contrôlé par un générateur d’impulsion sub nanoseconde, d’un doubleur de fréquence et d’un amplificateur dont les alimentations sont déclenchées par un autre générateur d’impulsion. La synchronisation, la détermination du seuil et la démodulation des données sont implémentées sous un FPGA afin de les valider et de déterminer la consommation d’énergie<br>He objective of this work was to study an ultra wideband (UWB) millimeter-wave module with low power consumption for wireless sensor networks (WSNs). WSNs provide distributed information collection and transmission which are useful for many industrial or environmental applications. Nowadays the use of 60GHz radio channel is attractive for WSNs applications since it benefits of a wide spectral resource (7 GHz allocated between 57GHz and 64GHz), a possibility for the miniaturization of the radio modules, limited interference with other communicating systems, as well as access to worldwide allocated non regulatory frequency bands. After comparing several physical layer technologies we chosed an impulse radio millimeter-wave UWB architecture transposed to 60GHz, the advantages of which are low power consumption, low complexity architecture, low sensitivity to the nonlinearity of the transmitter, robustness to multiple propagation effects and high time resolution for localization applications. We then showed that the approaches (S-MAC and Zigbee) are promising for the MAC layer of the WSNs,but need to be further improved since currently there are no established standards. In order to simplify the overall architecture of the radio module and reduce the power consumption, we have chosen an UWB millimeter-wave architecture using OOK modulation and noncoherent demodulation based on the energy detection. To validate the principle, we have designed two circuits using 0.1um GaAs pHEMT from the OMMIC. The first one is a 30 GHz transmitter and the second one is at 60GHz. In the end a new simple 60 GHz UWB transmitter using 65nm CMOS SOI technology was presented. This transmitter is composed of a negative differential resistance (NDR) oscillator driven by an UWB pulse generator in conjunction with a frequency doubler and a medium power amplifier (MPA), the supply of which is triggered by another UWB pulse generator. The synchronization, the determination of threshold and the demodulation of data are implemented on an FPGA to validate and determine the power consumption
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Youssef, Mohamed Wassim. "Étude des interfaces logicielles/matérielles dans le cadre des systèmes multiprocesseurs monopuces et des modèles de programmation parallèle de haut niveau." Université Joseph Fourier (Grenoble), 2006. http://www.theses.fr/2006GRE10030.
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Today's systems-on-chip are multiprocessor. They are characterized by an increasing complexity and a reduced time to market. To tackle this complexity, the use of high level programming models seems to be a promising approach. In this work, we propose an MPSoC design flow, based on the use of high level parallel programming models API to design embedded software. An automated refinement of these API on target architecture is used. For that purpose, (1) MPSoC hardware/software interfaces were studied; then (2) parallel programming models and their classification in terms of provided abstraction were presented. The proposed flow has been used in two design experiments: (1) an MPEG video encoder, namely OpenDivX, using the MPI parallel programming model and targeting the ARM Integrator prototyping platform, (2) a software defined radio using the CORBA parallel programming model and targeting specific hardware architecture<br>Les systèmes mono-puce sont composés d'une partie logicielle et d'une partie matérielle. L'exécution de la partie logicielle sur les ressources de la partie matérielle est assuré a travers l'utilisation d'une interface logicielle/matérielle. Cette interface a une structure complexe, sa conception nécessite des compétences issues des domaines du logiciel et du matériel. Pour maîtriser cette complexité, des approches de conception de haut niveau sont requises. Dans cette optique, un flot de conception des systèmes MPSoC est proposé. Il est basé sur l'utilisation des API des modèles de programmation parallèle en vue de l'abstraction des interfaces logicielles/matérielles lors de la conception de la partie logicielle, puis de leur génération automatique en raffinant l'API utilisée sur l'architecture cible. Pour arriver à ce but, (1) une étude de l'architecture des interfaces logicielles/matérielles a été réalisé. Puis, (2) une étude des modèles de programmation parallèle et une classification en fonction de leur niveau d'abstraction a été effectué. Ensuite, le flot proposé a été utilisé pour la conception de deux applications : (1) un encodeur vidéo OpenDivX en utilisant le modèle de programmation parallèle MPI et la plateforme ARM IntegratorAP comme architecture matérielle cible, (2) une radio définie par logiciel en utilisant le modèle de programmation CORBA et une architecture matérielle spécifique comme architecture cible
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Guillaume, Philippe. "Contribution aux aspects dorsaux de la synthèse de systèmes monopuces : optimisation de code pour processeurs embarqués, analyse de la consommation dans un environnement de synthèse comportementale /." Grenoble : Institut national polytechnique de Grenoble, 1999. http://catalogue.bnf.fr/ark:/12148/cb370486838.
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Damez, Lionel. "Approche multi-processeurs homogènes sur System-on-Chip pour le traitement d'image." Phd thesis, Université Blaise Pascal - Clermont-Ferrand II, 2009. http://tel.archives-ouvertes.fr/tel-00724443.
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La conception de prototypes de systèmes de vision en temps réel embarqué est sujet à de multiples contraintes sévères et fortement contradictoires. Dans le cas de capteurs dits "intelligents", il est nécessaire de fournir une puissance de traitement suffisante pour exécuter les algorithmes à la cadence des capteurs d'images avec un dispositif de taille minimale et consommant peu d'énergie. La conception d'un système monopuce (ou SoC) et l'implantation d'algorithmes de plus en plus complexes pose problème si on veut l'associer avec une approche de prototypage rapide d'applications scientifiques. Afin de réduire de manière significative le temps et les différents coûts de conception, le procédé de conception est fortement automatisé. La conception matérielle est basée sur la dérivation d'un modèle d'architecture multiprocesseur générique de manière à répondre aux besoins de capacité de traitement et de communication spécifiques à l'application visée. Les principales étapes manuelles se réduisent au choix et au paramétrage des différents composants matériels synthétisables disponibles. La conception logicielle consiste en la parallélisation des algorithmes, qui est facilitée par l'homogénéité et la régularité de l'architecture de traitement parallèle et la possibilité d'employer des outils d'aide à la parallélisation. Avec l'approche de conception sont présentés les premiers éléments constitutifs qui permettent de la mettre en oeuvre.Ceux ci portent essentiellement sur les aspects de conception matérielle. L'approche proposée est illustrée par l'implantation d'un traitement de stabilisation temps réel vidéo sur technologie SoPC
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LIN, ZHAO-HUI, and 林昭輝. "MONOPULSE IMAGING TECHNIQUE." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/37735803879775422475.
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WANG, TIAN-LIN, and 王天霖. "Sub-6GHz Monopulse Antenna Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/k793bh.
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碩士<br>國立臺北科技大學<br>電子工程系<br>107<br>In this paper, we propose a low-cost monopulse antenna. The monopulse antenna can use provided single or multiple radiation beams with high radiation gain. It is widely used in tracking, communication, and measurement systems. This paper is mainly divided into two parts. The first part is monopulse comparators design, Monopulse comparator made with 90-degree hybrid couplers. By adjusting the phase of the feed current along the array the sum pattern and difference pattern can be obtained thereby provided single radiation beam, double radiation beams as well as multiple radiation beams. The second part is the Circular polarization antenna-array design, this antenna array was formed by2 X 2 elements, the layout of 2 X 2 feed networks is uses the sequential phase feed structure, thus increasing the bandwidth of the antenna. Finally, the monopulse antenna of a 4×4 antenna array architecture is formed. It provides a sum beam gain of 9.9 dBi, the azimuth difference beam and elevation difference beam gain of approximately 7.1 dBi, and bidifference beam gain of approximately 3.1 dBi.