Relevant bibliographies by topics / Monotonic switching

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Academic literature on the topic 'Monotonic switching'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "Monotonic switching"

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Wang, Hao, Lungui Zhong, and Guocheng Zhang. "Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 10 (May 24, 2018): 1850161. http://dx.doi.org/10.1142/s021812661850161x.

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A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.
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Song, Hyeonho, and Minjae Lee. "Asymmetric monotonic switching scheme for energy-efficient SAR ADCs." IEICE Electronics Express 11, no. 12 (2014): 20140345. http://dx.doi.org/10.1587/elex.11.20140345.

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Zhu, Zhangming, Yu Xiao, and Xiaoli Song. "V CM ‐based monotonic capacitor switching scheme for SAR ADC." Electronics Letters 49, no. 5 (February 2013): 327–29. http://dx.doi.org/10.1049/el.2012.3332.

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Chen, Yushi, Yiqi Zhuang, and Hualian Tang. "An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC." Journal of Circuits, Systems and Computers 29, no. 06 (August 2, 2019): 2050086. http://dx.doi.org/10.1142/s0218126620500863.

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An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.
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Chang, Ke, Pei Liu, Lei Dong, and Guohe Zhang. "A two-step asymmetric alternate monotonic switching scheme for SAR ADCs." Analog Integrated Circuits and Signal Processing 102, no. 3 (March 2020): 625–35. http://dx.doi.org/10.1007/s10470-020-01615-y.

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Моргунов, Р. Б., А. И. Безверхний, О. С. Дмитриев, and M. В. Бахметьев. "Условия возникновения спонтанной осциллирующей магнитной релаксации в синтетических ферримагнетиках Pt/Co/Ir/Co/Pt." Физика твердого тела 62, no. 3 (2020): 407. http://dx.doi.org/10.21883/ftt.2020.03.49005.583.

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We had established that the non-monotonic magnetic relaxation appeared, when two or three magnetic fields, switching between stable magnetization states, coincide with each other, in Pt/Co/Ir/Co/Pt synthetic ferrimagnets with perpendicular magnetic anisotropy. Switching fields between stable magnetization states depend on sum of exchange interlayer energy, Zeeman energy and magnetization reversal energy barrier of each layer. This total energy depends on layers thickness and temperature. We had shown that with choose of temperature and free layer thickness we can achieve double or triple points on energy states diagram, which is reason of nonmonotonic magnetization relaxation.
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HSU, CHENG-HSIUNG, CHUN-HSIEN LI, and SUH-YUH YANG. "DIVERSITY OF TRAVELING WAVE SOLUTIONS IN DELAYED CELLULAR NEURAL NETWORKS." International Journal of Bifurcation and Chaos 18, no. 12 (December 2008): 3515–50. http://dx.doi.org/10.1142/s0218127408022561.

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This work investigates the diversity of traveling wave solutions for a class of delayed cellular neural networks on the one-dimensional integer lattice ℤ1. The dynamics of a given cell is characterized by instantaneous self-feedback and neighborhood interaction with distributed delay due to, for example, finite switching speed and finite velocity of signal transmission. Applying the monotone iteration scheme, we can deduce the existence of monotonic traveling wave solutions provided the templates satisfy the so-called quasi-monotonicity condition. We then consider two special cases of the delayed cellular neural network in which each cell interacts only with either the nearest m left neighbors or the nearest m right neighbors. For the former case, we can directly figure out the analytic solution in an explicit form by the method of step with the help of the characteristic function and then prove that, in addition to the existence of monotonic traveling wave solutions, for certain templates there exist nonmonotonic traveling wave solutions such as camel-like waves with many critical points. For the latter case, employing the comparison arguments repeatedly, we can clarify the deformation of traveling wave solutions with respect to the wave speed. More specifically, we can describe the transition of profiles from monotonicity, damped oscillation, periodicity, unboundedness and back to monotonicity as the wave speed is varied. Some numerical results are also given to demonstrate the theoretical analysis.
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Bonança, Marcus V. S. "Non-Monotonic Behavior of the Thermodynamic Work as a Function of Switching Time." Brazilian Journal of Physics 46, no. 3 (October 7, 2015): 248–53. http://dx.doi.org/10.1007/s13538-015-0370-7.

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Verma, Deeksha, Khuram Shehzad, Danial Khan, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, and Kang-Yoon Lee. "A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application." Electronics 9, no. 7 (July 6, 2020): 1100. http://dx.doi.org/10.3390/electronics9071100.

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A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.
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Dyda, Alexander A., Nguyen Van Thanh Van Thanh, and Ksenya N. Chumakova. "Vessel heading control systems with switchable regulators." Russian Journal of Water Transport, no. 67 (June 15, 2021): 169–77. http://dx.doi.org/10.37890/jwt.vi67.188.

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The purpose of this work is to study the possibilities of improving the quality of the processes of controlling the movement of the vessel along the course by combining individual standard controllers. Of the known scientific directions devoted to the problem being solved, the closest is the theory of systems with variable structure, in which, due to switching, a unique useful property is achieved, which are not possessed by individual switched structures. The article is devoted to the approach to the construction of the ship course control system, which is based on the principle of switching regulators during the transient process. This makes it possible to improve the quality of control processes in the system by using the features of individual regulators, in particular, the application of the switching principle made it possible to significantly increase the speed of the system in comparison with systems without switching and ensure the desired monotonic nature of the control process. The proposed approach is illustrated based on switchable P-controllers. The results of modeling the developed ship course control system are presented and discussed.
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Dissertations / Theses on the topic "Monotonic switching"

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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Potechin, Aaron H. "Analyzing monotone space complexity via the switching network model." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99066.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Mathematics, 2015.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 177-179).
Space complexity is the study of how much space/memory it takes to solve problems. Unfortunately, proving general lower bounds on space complexity is notoriously hard. Thus, we instead consider the restricted case of monotone algorithms, which only make deductions based on what is in the input and not what is missing. In this thesis, we develop techniques for analyzing monotone space complexity via a model called the monotone switching network model. Using these techniques, we prove tight bounds on the minimal size of monotone switching networks solving the directed connectivity, generation, and k-clique problems. These results separate monotone analgoues of L and NL and provide an alternative proof of the separation of the monotone NC hierarchy first proved by Raz and McKenzie. We then further develop these techniques for the directed connectivity problem in order to analyze the monotone space complexity of solving directed connectivity on particular input graphs.
by Aaron H. Potechin.
Ph. D.
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Bénézet, Cyril. "Study of numerical methods for partial hedging and switching problems with costs uncertainty." Thesis, Université de Paris (2019-....), 2019. http://www.theses.fr/2019UNIP7079.

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Nous apportons dans cette thèse quelques contributions à l’étude théorique et numérique de certains problèmes de contrôle stochastique, ainsi que leurs applications aux mathématiques financières et à la gestion des risques financiers. Ces applications portent sur des problématiques de valorisation et de couverture faibles de produits financiers, ainsi que sur des problématiques réglementaires. Nous proposons des méthodes numériques afin de calculer efficacement ces quantités pour lesquelles il n’existe pas de formule explicite. Enfin, nous étudions les équations différentielles stochastiques rétrogrades liées à de nouveaux problèmes de switching, avec incertitude sur les coûts
In this thesis, we give some contributions to the theoretical and numerical study to some stochastic optimal control problems, and their applications to financial mathematics and risk management. These applications are related to weak pricing and hedging of financial products and to regulation issues. We develop numerical methods in order to compute efficiently these quantities, when no closed formulae are available. We also study backward stochastic differential equations linked to some new switching problems, with costs uncertainty
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Su, Shiou-Wei, and 蘇修緯. "A 10-bit Successive Approximation Register ADCWith Monotonic Capacitor Switching Procedure." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/95871280610812041429.

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Tseng, Shih-Ying, and 曾世穎. "A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/29325643947363123037.

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碩士
國立中興大學
電機工程學系所
102
This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency of the analog-to-digital converter. In addition, the design can effectively enhance the sampling frequency by reduce the delay time of the critical path in digital control logic circuit. With TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process, the sampling frequencies are, respectively, 66M Sample / s and 166M Sample / s. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.556 mm2 with sarf2_12_decouple chip (10 bits) .The supply voltage is 1.2V, the sampling frequency is 66MS / s, input sine wave frequency is 10MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 6.86. Input sine wave frequency is 100kHz, the measured differential nonlinearity ranged between -1LSB~5.25LSB, integral nonlinearity ranged between -5.20LSB~3.16LSB, the total power consumption is 4.78mW ,FOM is 0.624pJ / Conversion-step. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.520 mm2 with sarf2_31_decouple chip (8 bits) .The supply voltage is 1.2V & 1.4V, the sampling frequency is 166MS / s, input sine wave frequency is 20MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 5.67. Input sine wave frequency is 200kHz, the measured differential nonlinearity ranged between -1LSB~2.07LSB, integral nonlinearity ranged between -0.76LSB~3.76LSB, the total power consumption is 11.58mW ,FOM is 3.3pJ / Conversion-step.
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Tung, Wei, and 童偉. "A DIGITALLY CALIBRATED 11-BIT 10-MS/s SAR ADC WITH MONOTONIC SWITCHING SPLIT CAPACITOR ARRAY." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/89282578310273443460.

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碩士
大同大學
電機工程學系(所)
104
In this thesis, a digitally calibrated 11 bit 10MS/s asynchronous differential SAR ADC is presented. A monotonic capacitor switching procedure is used in the design, such that the input pair of the comparator converges to the ground. In this structure, the differential inputs are sample to the input pair of the comparator, where the MSB can be determined without using MSB capacitor. In order to further reduce the area, this design uses split capacitor structure, which affects the linearity of the system. A digital calibration method is proposed to minimize the effects including capacitor mismatch and the bridge parasitic capacitor. The SAR ADC is implemented with a 0.18um CMOS technology. At a 1.8-V supply and 10 MS/s, the ADC achieves an SNDR of 65.2 dB and consumes 0.62 mW, resulting in a figure of merit (FOM) of 21 fJ/conversion-step. The ADC core occupies an active area of 350m  350m.
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Conference papers on the topic "Monotonic switching"

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Osipov, Dmitry, and Steffen Paul. "Two-step monotonic switching scheme for low-power SAR ADCs." In 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, 2017. http://dx.doi.org/10.1109/newcas.2017.8010141.

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Hong, Xiang, Chenchen Yang, and Xiaojie Zhang. "An energy-efficient SAR ADC with a partial-monotonic capacitor switching technique." In 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). IEEE, 2017. http://dx.doi.org/10.1109/iaeac.2017.8054377.

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Li, Lun, Dongsheng Liu, Weila Lei, Yu Hu, Xuecheng Zou, and Dawei Li. "A low power charge-redistribution SAR ADC with a monotonic switching procedure." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021548.

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Burcea, Florin, Husni Habal, and Helmut Graeb. "A novel analytical model for the static behavior of a monotonic-switching charge-scaling ADC." In 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2016. http://dx.doi.org/10.1109/prime.2016.7519453.

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Xie, Yun, Jiwei Wen, Li Peng, and Howard Wang. "Robust H∞ control of average dwell time switching systems via non-monotonic lyapunov function approach." In 2017 3rd IEEE International Conference on Control Science and Systems Engineering (ICCSSE). IEEE, 2017. http://dx.doi.org/10.1109/ccsse.2017.8087886.

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Eddine, Ouerfelli Houssem, Ben Attia Selma, and Salhi Salah. "Monotonic convergence switching iterative learning tracking control for a class of continuous time switched systems." In 2017 American Control Conference (ACC). IEEE, 2017. http://dx.doi.org/10.23919/acc.2017.7963652.

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Mishra, Kirti D., and K. Srinivasan. "Iterative Learning Control for Hybrid Systems." In ASME 2020 Dynamic Systems and Control Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/dscc2020-3191.

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Abstract Iterative learning control (ILC) has been growing in applicability, along with growth in theory for classes of linear and nonlinear systems, and this study extends the theory of ILC to hybrid systems. A lifted form representation of hybrid systems with input-output dependent switching rules is developed, and the proposed lifted form representation is modeled as a switched system with arbitrary/unconstrained switching rules in the trial domain for control design. The causality of hybrid systems in the time domain results in the (lower) triangular structure of switched systems in the trial domain, the triangular structure enabling systematic and efficient control design. A unique aspect of the control design method developed for ILC of hybrid systems in this study is that a solution to the required set of linear matrix inequalities (LMIs) is guaranteed to exist under mild assumptions, which is in contrast to many other studies proposing LMI based solutions in controls literature. The proposed method is validated numerically for a motion control application, and robust and monotonic convergence of the tracking error to zero is demonstrated.
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Filmus, Yuval, Toniann Pitassi, Robert Robere, and Stephen A. Cook. "Average Case Lower Bounds for Monotone Switching Networks." In 2013 IEEE 54th Annual Symposium on Foundations of Computer Science (FOCS). IEEE, 2013. http://dx.doi.org/10.1109/focs.2013.70.

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Potechin, Aaron. "Bounds on Monotone Switching Networks for Directed Connectivity." In 2010 IEEE 51st Annual Symposium on Foundations of Computer Science (FOCS). IEEE, 2010. http://dx.doi.org/10.1109/focs.2010.58.

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Chan, Siu Man, and Aaron Potechin. "Tight bounds for monotone switching networks via fourier analysis." In the 44th symposium. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2213977.2214024.

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