Relevant bibliographies by topics / MOS Transistor Circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'MOS Transistor Circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "MOS Transistor Circuits"

1

Vandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

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A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast duri
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Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.

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This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has
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Mishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.

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In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better
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Thakral, Bindu, Arti Vaish, and Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode." International Journal of Engineering & Technology 7, no. 2.11 (2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of th
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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to fi
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Widemann, C., S. Stegemann, W. John, and W. Mathis. "Analytic investigations on the susceptibility of nonlinear analog circuits to substrate noise." Advances in Radio Science 11 (July 4, 2013): 171–75. http://dx.doi.org/10.5194/ars-11-171-2013.

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Abstract. This work deals with the conducted susceptibility of nonlinear analog circuits with respect to substrate noise. The substrate coupling mechanism is modeled by a passive three-terminal network that is obtained by means of the finite element method with a subsequently performed model order reduction. Applying this substrate model to the bulk terminal of MOS transistors in integrated analog circuits, it is possible to examine the influence of substrate noise on the circuit's functionality. By means of a block-oriented approach, analytic expressions for the output behavior of the circuit
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Yang, D., J. Hu, and X. Xiang. "Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 286–97. http://dx.doi.org/10.2174/1874129001408010286.

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Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC
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Castagnola, Juan L., Fortunato C. Dualibe, Agustín M. Laprovitta, and Hugo García-Vázquez. "A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio." Electronics 9, no. 5 (2020): 785. http://dx.doi.org/10.3390/electronics9050785.

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This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. I
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Wang, Yao, Haibo Wang, and Guangjun Wen. "A Low-Power Edge Detection Technique for Sensor Wake-Up Applications." Journal of Circuits, Systems and Computers 24, no. 10 (2015): 1550157. http://dx.doi.org/10.1142/s0218126615501571.

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A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuit
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Gan, Kwang Jow, Zheng Jie Jiang, Cher Shiung Tsai, et al. "Design of NDR-Based Oscillators Suitable for the Nano-Based BiCMOS Technique." Applied Mechanics and Materials 328 (June 2013): 669–73. http://dx.doi.org/10.4028/www.scientific.net/amm.328.669.

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We present three oscillator designs using the negative-differential-resistance (NDR) circuit which is composed of several Si-based metal-oxide-semiconductor field-effect transistor (MOS) devices and one SiGe-based heterojunction bipolar transistor (HBT) devices. These oscillator circuits are composed of the NDR circuit, resistor, inductor, and capacitor. The oscillation frequencies are about several GHz based on the HSPICE simulation results. The circuits are designed using a standard 0.18 μm BiCMOS technique. Because our circuits are mainly made of a BiCMOS-NDR circuit that is different from
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Dissertations / Theses on the topic "MOS Transistor Circuits"

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Fuchs, Franz Xaver. "Clock-feedthrough compensation in MOS sample-and-hold circuits." Thesis, University of Plymouth, 2001. http://hdl.handle.net/10026.1/2354.

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All MOS sample-and-hold circuits suffer to a greater or lesser extent from clock-feedthrough (CLFT), also called charge-injection. During the transition from sample to hold mode, charge is transferred from an MOS transistor switch onto the hold capacitor, thus the name charge-injection. This error can lead to considerable voltage change across the capacitor, and predicting the extent of the induced error potentials is important to circuit designers. Previous studies have shown a considerable dependency of CLFT on signal voltage, circuit impedances, clock amplitude and clock fall-time. The focu
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Rabah, Kefa V. O. "A study of switching of MOS-bipolar power transistor hybrids." Thesis, Lancaster University, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314432.

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Diouf, Cheikh. "Caractérisation électrique des transistors d’architecture innovante pour les longueurs de grilles décananométriques." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT082/document.

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La taille du transistor MOS ne cesse de diminuer pour des questions de performance et de rentabilité de fabrication. Les procédés de fabrication évoluent, l'architecture se complexifie et les méthodologies d'extraction de paramètres électriques doivent être adaptées. C'est ainsi que dans un premier temps, les effets d'un recuit haute pression sous atmosphère hydrogène (HPH2) ou deutérium (HPD2) sur le transistor MOS sont étudiés en détail dans cette thèse. La comparaison des performances apportées en termes de transport électronique et de dégradations engendrées en fiabilité a permis de montre
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Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183139647.

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Couto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.

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Orientador: Carlos Alberto dos Reis Filho<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação<br>Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005<br>Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e util
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Heddebaut, Bruno. "Étude phénoménologique et modélisation du comportement de fonctions logiques élémentaires TTL et CMOS soumises à des perturbations induites par couplages électromagnétiques." Lille 1, 1992. http://www.theses.fr/1992LIL10087.

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L'usage intensif de fonctions microprogrammées ou plus généralement de logiques bas niveau expose les équipements électroniques à certaines défaillances en présence de champs électromagnétiques hautes fréquences. Ces derniers produisent des mécanismes d'inductions dont les agents sont les lignes de transmissions et les pistes imprimées qui communiquent avec les ports d'accès à un composant intégré dont le fonctionnement peut être troublé. Notre thèse consiste à comprendre et à modéliser ces phénomènes de façon à comparer la sensibilité de différentes variantes de technologie disponible sur le
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Gneiting, Thomas. "An investigation into the implementation of advanced high performance integrated circuits in deep submicron process generations." Thesis, Brunel University, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387530.

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Bezza, Anas. "Caractérisation et modélisation du phénomène de claquage dans les oxydes de grille à forte permittivité, en vue d’améliorer la durée de vie des circuits issus des technologies 28nm et au-delà." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT097.

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.Aujourd’hui, la course à la miniaturisation a engendré de nouveaux défis dans l’industrie microélectronique. En plus de la forte concurrence que subissent les fabricants de composants, de nouvelles contraintes liées à la fiabilité des dispositifs se sont imposées. En effet, le passage d’une technologie « tout silicium » relativement simple à une technologie high-k/grille métal plus complexe, a entrainé une forte réduction des marges de fiabilité des oxydes de grille. A ce titre, Il est devenu nécessaire d’investiguer de nouvelles approches pouvant offrir davantage de gain en durée de vie pour
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Kiefer, Jean-Georges. "Contribution à l'étude des effets de la réduction des dimensions du transistor MOS : application à la conception des circuits intégrés analogiques CMOS." Grenoble 1, 1986. http://www.theses.fr/1986GRE10105.

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Ce memoire traite des effets de petites dimensions du transistor metal-oxyde-semiconducteur (mos). Les principales methodes de maigrissement sont analysees et les grandes lignes de l'evolution des technologies mos sont esquissees. Un modele courant-tension du transistor, qui prend en compte ces effets physiques et qui se prete bien a une extraction de parametres rapide et facile, est adopte. Cette derniere etude est concretisee par la mise au point et la programmation d'un banc de caracterisation en continu. Une structure d'amplificateur operationnel est etudiee et realisee dans une technologi
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Cajueiro, João Paulo Cerquinho. "Fonte de tensão de referencia ajustavel implementada com transistores MOS." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260509.

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Orientador: Carlos Alberto dos Reis Filho<br>Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação<br>Made available in DSpace on 2018-08-05T12:05:57Z (GMT). No. of bitstreams: 1 Cajueiro_JoaoPauloCerquinho_D.pdf: 1564955 bytes, checksum: 6ff645ea51f6ee2dcb9e7ab8db6363aa (MD5) Previous issue date: 2005<br>Resumo: Uma nova técnica de compensação de temperatura para implementar tensões de referência em circuitos CMOS é descrita, desde o seu fundamento teórico até a comprovação experimental feita com amostras de circuitos integrados protótipos qu
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Books on the topic "MOS Transistor Circuits"

1

C, Sansen Willy M., and Maes H. E, eds. Matching properties of deep sub-micron MOS transistors. Springer, 2005.

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Bipolar and MOS analog integrated circuit design. Wiley-Interscience, 2003.

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Bipolar/BiCMOS Circuits and Technology Meeting (1995 Minneapolis, Minn.). Proceedings of the 1995 Bipolar/BiCMOS Circuits and Technology Meeting. IEEE Service Center, 1995.

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Bipolar/BiCMOS Circuits and Technology Meeting (2000 Minneapolis, Minn.). Proceedings of the 2000 Bipolar/BiCMOS Circuits and Technology Meeting: September 24-26, 2000. IEEE, 2000.

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Enz, Christian C., and Eric A. Vittoz. Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design. Wiley & Sons, Incorporated, John, 2006.

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Ouslis, Chris *. An investigation of computer-aided MOS transistor modelling for analogue circuit simulation. 1988.

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H, Hart P. A., ed. Bipolar and bipolar-MOS integration. Elsevier, 1994.

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Huang, Feng-Jung. Schottky clamped MOS transistors for wireless CMOS radio frequency switch applications. 2001.

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Haartman, Martin v., and Mikael Östling. Low-Frequency Noise in Advanced MOS Devices (Analog Circuits and Signal Processing). Springer, 2007.

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Palumbo, Gaetano, and Massimo Alioto. Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Springer, 2005.

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Book chapters on the topic "MOS Transistor Circuits"

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Kolawole, Michael Olorunfunmi. "MOS Field-Effect Transistor (MOSFET) Circuits." In Electronics. CRC Press, 2020. http://dx.doi.org/10.1201/9781003052913-5.

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Papananos, Yannis E. "The MOS Transistor at High Frequencies." In Radio-Frequency Microelectronic Circuits for Telecommunication Applications. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3017-3_2.

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Leblebici, Yusuf, and Sung-Mo Kang. "Transistor-Level Simulation for Circuit Reliability." In Hot-Carrier Reliability of MOS VLSI Circuits. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3250-7_5.

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Conn, Andrew R., Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, and Chandu Visweswariah. "Optimization of Custom MOS Circuits by Transistor Sizing." In The Best of ICCAD. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0292-0_28.

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Enz, Christian C., François Krummenacher, and Eric A. Vittoz. "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications." In Low-Voltage Low-Power Analog Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2283-6_7.

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Bhowmik, Sonali, and Surajit Bari. "Design of Row Decoder Circuit for Semiconductor Memory at Low Power and Small Delay Using MOS Transistor at Nano Dimension Channel Length." In Computational Advancement in Communication Circuits and Systems. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_43.

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Pal, Ajit. "MOS Transistors." In Low-Power VLSI Circuits and Systems. Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-1937-8_3.

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Bindal, Ahmet. "MOS Transistors and CMOS Circuits." In Electronics for Embedded Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-39439-8_3.

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Leblebici, Yusuf, and Sung-Mo Kang. "Oxide Degradation Mechanisms in MOS Transistors." In Hot-Carrier Reliability of MOS VLSI Circuits. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3250-7_2.

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Enz, Christian, and Yuhua Cheng. "MOS Transistor Modeling Issues for RF Circuit Design." In Analog Circuit Design. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3047-0_9.

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Conference papers on the topic "MOS Transistor Circuits"

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Reddy, M. K., S. M. Reddy, and P. Agrawal. "Transistor Level Test Generation for MOS Circuits." In 22nd ACM/IEEE Design Automation Conference. IEEE, 1985. http://dx.doi.org/10.1109/dac.1985.1586046.

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Reddy, Madhukar K., Sudhakar M. Reddy, and Prathima Agrawal. "Transistor level test generation for MOS circuits." In the 22nd ACM/IEEE conference. ACM Press, 1985. http://dx.doi.org/10.1145/317825.318007.

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Kuzmicz, Wieslaw. "MOS transistor as a current-controlled device." In 2016 MIXDES - 23rd International Conference "Mixed Design of Integrated Circuits and Systems". IEEE, 2016. http://dx.doi.org/10.1109/mixdes.2016.7529736.

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Mohamed, Heba N., and Soliman A. Mahmoud. "Modeling photovoltaic modules using N-channel MOS transistor." In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2013. http://dx.doi.org/10.1109/icecs.2013.6815521.

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Schaefer, T. J. "A Transistor-Level Logic-with-Timing Simulator for MOS Circuits." In 22nd ACM/IEEE Design Automation Conference. IEEE, 1985. http://dx.doi.org/10.1109/dac.1985.1586031.

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Schaefer, Thomas J. "A transistor-level logic-with-timing simulator for MOS circuits." In the 22nd ACM/IEEE conference. ACM Press, 1985. http://dx.doi.org/10.1145/317825.317982.

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Fouda, Mohammed E., A. AboBakr, A. S. Elwakil, A. G. Radwan, and A. M. Eltawil. "Simple MOS Transistor-Based Realization of Fractional-Order Capacitors." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702341.

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Fujimura, Toru, and Shigetoshi Nakatake. "Transistor-level programmable MOS analog IC with body biasing." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541377.

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Dimitrov, Dimitar P. "Deep-Submicron MOS Transistor Matching: A Case Study." In 2008 11th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008). IEEE, 2008. http://dx.doi.org/10.1109/ddecs.2008.4538744.

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Chang, Kun-Zen, Jinnu-Fu Liou, Mei-Li Chiou, and S. W. Chang. "High-voltage structure of MOS transistor for LCD driver circuits application." In International Symposium on Optoelectronics in Computers, Communications, and Control, edited by Shu-Hsia Chen and Shin-Tson Wu. SPIE, 1992. http://dx.doi.org/10.1117/12.131312.

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