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Journal articles on the topic 'MOS Transistor Circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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1

Vandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

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A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast duri

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2

Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.

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This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has

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3

Mishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.

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In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better

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4

Thakral, Bindu, Arti Vaish, and Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode." International Journal of Engineering & Technology 7, no. 2.11 (2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of th

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to fi

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6

Widemann, C., S. Stegemann, W. John, and W. Mathis. "Analytic investigations on the susceptibility of nonlinear analog circuits to substrate noise." Advances in Radio Science 11 (July 4, 2013): 171–75. http://dx.doi.org/10.5194/ars-11-171-2013.

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Abstract. This work deals with the conducted susceptibility of nonlinear analog circuits with respect to substrate noise. The substrate coupling mechanism is modeled by a passive three-terminal network that is obtained by means of the finite element method with a subsequently performed model order reduction. Applying this substrate model to the bulk terminal of MOS transistors in integrated analog circuits, it is possible to examine the influence of substrate noise on the circuit's functionality. By means of a block-oriented approach, analytic expressions for the output behavior of the circuit

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7

Yang, D., J. Hu, and X. Xiang. "Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 286–97. http://dx.doi.org/10.2174/1874129001408010286.

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Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC

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8

Castagnola, Juan L., Fortunato C. Dualibe, Agustín M. Laprovitta, and Hugo García-Vázquez. "A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio." Electronics 9, no. 5 (2020): 785. http://dx.doi.org/10.3390/electronics9050785.

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This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. I

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9

Wang, Yao, Haibo Wang, and Guangjun Wen. "A Low-Power Edge Detection Technique for Sensor Wake-Up Applications." Journal of Circuits, Systems and Computers 24, no. 10 (2015): 1550157. http://dx.doi.org/10.1142/s0218126615501571.

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A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuit

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10

Gan, Kwang Jow, Zheng Jie Jiang, Cher Shiung Tsai, et al. "Design of NDR-Based Oscillators Suitable for the Nano-Based BiCMOS Technique." Applied Mechanics and Materials 328 (June 2013): 669–73. http://dx.doi.org/10.4028/www.scientific.net/amm.328.669.

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We present three oscillator designs using the negative-differential-resistance (NDR) circuit which is composed of several Si-based metal-oxide-semiconductor field-effect transistor (MOS) devices and one SiGe-based heterojunction bipolar transistor (HBT) devices. These oscillator circuits are composed of the NDR circuit, resistor, inductor, and capacitor. The oscillation frequencies are about several GHz based on the HSPICE simulation results. The circuits are designed using a standard 0.18 μm BiCMOS technique. Because our circuits are mainly made of a BiCMOS-NDR circuit that is different from

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11

Altet, Josep, Enrique Barajas, Diego Mateo, et al. "BPF-Based Thermal Sensor Circuit for On-Chip Testing of RF Circuits." Sensors 21, no. 3 (2021): 805. http://dx.doi.org/10.3390/s21030805.

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A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metal-oxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissip

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12

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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13

POPA, COSMIN. "LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 519–34. http://dx.doi.org/10.1142/s0218126609005253.

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Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak i

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14

Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is expl

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15

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad ar

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16

Pantel, R., E. Sondergard, D. Delille, and L. F. Tz Kwakman. "Quantitative Thickness Measurements of Thin Oxides Using Low Energy Loss Filtered TEM Imaging." Microscopy and Microanalysis 7, S2 (2001): 560–61. http://dx.doi.org/10.1017/s1431927600028877.

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A technique for very thin silicon oxide measurements using energy filtered TEM (EFTEM) is presented and applied for BiCMOS technology optimization.In advanced VLSI circuits, thin silicon oxide layers are used as critical part of active devices such as MOS or bipolar transistors (BiCMOS). Today the 2 nm thick gate oxides of the 0.12 urn generation MOS transistors can be controlled using high resolution TEM (HRTEM). However, for the next generations these measurements will become difficult or will necessitate Cs corrected microscopes'. For the NPN bipolar transistor very thin oxides (less than 0

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17

Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Bootstrapped Switches." Electronics 10, no. 14 (2021): 1661. http://dx.doi.org/10.3390/electronics10141661.

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the c

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18

Kumar, Manish, Md Anwar Hussain, and Sajal K. Paul. "Effective Circuit Design Methodologies for Standby Leakage Power Reduction." Advanced Science, Engineering and Medicine 12, no. 2 (2020): 168–72. http://dx.doi.org/10.1166/asem.2020.2484.

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This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software

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19

Elwakil, A. S. "Motivating Two-Port Network Analysis through Elementary and Advanced Examples." International Journal of Electrical Engineering & Education 47, no. 4 (2010): 404–15. http://dx.doi.org/10.7227/ijeee.47.4.5.

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We seek to motivate the use of two-port network circuit analysis techniques by proposing two examples: one is elementary, the other is advanced. In particular, we start by deriving the transmission matrices for small-signal equivalent models of the BJT and MOS transistors. We then proceed to the first example where we explain the function of a Gyrator in a very clear way aided by Spice simulations. In the second more advanced example, we show how to systematically analyse the classical Cascode amplifier in a general way that is independent of whether it is realized using a BJT or a MOS transis

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20

NIU, Dan, Kazutoshi SAKO, Guangming HU, and Yasuaki INOUE. "A Globally Convergent Nonlinear Homotopy Method for MOS Transistor Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A, no. 12 (2012): 2251–60. http://dx.doi.org/10.1587/transfun.e95.a.2251.

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21

Rantala, A., S. Franssila, K. Kaski, J. Lampinen, M. Aberg, and P. Kuivalainen. "Improved neuron MOS-transistor structures for integrated neural network circuits." IEE Proceedings - Circuits, Devices and Systems 148, no. 1 (2001): 25. http://dx.doi.org/10.1049/ip-cds:20010055.

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22

Hu, Jian Ping, and Yu Zhang. "Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction." Advanced Materials Research 159 (December 2010): 180–85. http://dx.doi.org/10.4028/www.scientific.net/amr.159.180.

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Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopte

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23

Niu, Dan, Xiao Jun Wang, Xing Peng Zhou, Guo Rui He, and Zhou Rong Huang. "An Effective Implementation of the Nonlinear Homotopy Method for MOS Transistor Circuits." Applied Mechanics and Materials 619 (August 2014): 166–72. http://dx.doi.org/10.4028/www.scientific.net/amm.619.166.

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Recently, an efficient homotopy method termed the nonlinear homotopy method (NLH) has been proposed for finding DC operating points of MOS transistor circuits. This method is not only efficient but also globally convergent. However, the programming of sophisticated homotopy methods is often difficult for non-experts or beginners. In this paper, an effective method for implementing the MOS NLH method on SPICE is proposed. By this method, we can implement the MOS NLH method from a good initial solution with various efficient techniques and without programming.

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24

Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies." Crystals 11, no. 9 (2021): 1150. http://dx.doi.org/10.3390/cryst11091150.

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All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic in

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25

Dagenais, M. R., S. Gaiotti, and N. C. Rumin. "Transistor-level estimation of worst-case delays in MOS VLSI circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 3 (1992): 384–95. http://dx.doi.org/10.1109/43.124425.

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26

Schwabe, Ulrich, and Erwin Jacobs. "4459741 Method for producing VLSI complementary MOS field effect transistor circuits." Vacuum 35, no. 1 (1985): 55. http://dx.doi.org/10.1016/0042-207x(85)90079-x.

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27

Sayed, Shimaa Ibrahim, Mostafa Mamdouh Abutaleb, and Zaki Bassuoni Nossair. "Optimization of CNFET Parameters for High Performance Digital Circuits." Advances in Materials Science and Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/6303725.

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The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current d

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28

Dokic, Branko, Tatjana Pesic-Brdjanin, and Rados Dabic. "Analytic models of CMOS logic in various regimes." Serbian Journal of Electrical Engineering 11, no. 2 (2014): 269–90. http://dx.doi.org/10.2298/sjee140106022d.

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In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuit

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29

CHENG, KUO-HSING, SHUN-WEN CHENG, and WEN-SHIUAN LEE. "64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 13–27. http://dx.doi.org/10.1142/s0218126606002915.

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This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC

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30

Caisso, J. P., E. Cerny, and N. C. Rumin. "A recursive technique for computing delays in series-parallel MOS transistor circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 5 (1991): 589–95. http://dx.doi.org/10.1109/43.79496.

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31

Nagulapalli, R., K. Hayatleh, S. Barker, A. A. Tammam, P. Georgiou, and F. J. Lidgey. "A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950120. http://dx.doi.org/10.1142/s0218126619501202.

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This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works w

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32

Andrejevic, Miona, and Vanco Litovski. "Electronic circuits modeling using artificial neural networks." Journal of Automatic Control 13, no. 1 (2003): 31–37. http://dx.doi.org/10.2298/jac0301031a.

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In this paper artificial neural networks (ANN) are applied to modeling of electronic circuits. ANNs are used for application of the black-box modeling concept in the time domain. Modeling process is described, so the topology of the ANN, the testing signal used for excitation, together with the complexity of ANN are considered. The procedure is first exemplified in modeling of resistive circuits. MOS transistor, as a four-terminal device, is modeled. Then nonlinear negative resistive characteristic is modeled in order to be used as a piece-wise linear resistor in Chua's circuit. Examples of mo

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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-

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35

NIU, Dan, Xiao WU, Zhou JIN, and Yasuaki INOUE. "An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96.A, no. 9 (2013): 1848–56. http://dx.doi.org/10.1587/transfun.e96.a.1848.

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Jain, Amit, Basanta Singh Nameriakpam, and Subir Kumar Sarkar. "A new compact analytical model of single electron transistor for hybrid SET–MOS circuits." Solid-State Electronics 104 (February 2015): 90–95. http://dx.doi.org/10.1016/j.sse.2014.11.019.

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Yao, C. T., and H. C. Lin. "Comments on "Small geometry MOS transistor capacitance measurement method using simple on-chip circuits"." IEEE Electron Device Letters 6, no. 1 (1985): 63. http://dx.doi.org/10.1109/edl.1985.26042.

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Schwabe, Ulrich, Erwin Jacobs, and Adolf Scheibe. "4459740 Method for manufacturing VLSI complementary MOS field effect transistor circuits in silicon gate technology." Vacuum 35, no. 1 (1985): 55. http://dx.doi.org/10.1016/0042-207x(85)90078-8.

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39

Yoshida, Shinya, Hiroshi Miyaguchi, and Tsutomu Nakamura. "Prototyping of an All-pMOS-Based Cross-Coupled Voltage Multiplier in Single-Well CMOS Technology for Energy Harvesting Utilizing a Gastric Acid Battery." Electronics 8, no. 7 (2019): 804. http://dx.doi.org/10.3390/electronics8070804.

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A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount of energy. In this study, we have proposed an all-p-channel metal-oxide semiconductor (pMOS)-based cross-coupled voltage multiplier (CCVM) utilizing single-well CMOS technology to achieve a voltage boosting higher than from a conventional complementary MOS (CMOS) CCVM. We prototyped a custom integrated circuit (IC) implemented with the above CCVMs and a ri

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Jacquemod, G., Y. Charlon, Z. Wei, Y. Leduc, and P. Lorenzini. "Application de la technologie FDSOI pour la conception de nouvelles topologies de circuits analogiques et mixtes." J3eA 18 (2019): 1021. http://dx.doi.org/10.1051/j3ea/20191021.

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Pour poursuivre la loi de Moore avec des noeuds technologiques de 22 nm et en deçà, les transistors MOS bulk ont été remplacés par des transistors FinFET ou UTBB-FDSOI. Ces derniers disposent d’une grille arrière permettant de réaliser de nouvelles topologies de circuits analogiques et mixtes, offrant des performances jamais atteintes et réduisant certaines limitations, comme par exemple celles liées à la réduction de la longueur du canal. Partant de la caractéristique de la tension de seuil d’un transistor UTBB-FDSOI en fonction de la polarisation de la grille arrière, nous proposons aux élèv

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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in th

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Khateb, Fabian, Tomasz Kulej, Harikrishna Veldandi, and Winai Jaikla. "Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits." AEU - International Journal of Electronics and Communications 100 (February 2019): 32–38. http://dx.doi.org/10.1016/j.aeue.2018.12.023.

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Khursheed, Afreen, and Kavita Khare. "Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects." Circuit World 46, no. 2 (2020): 71–83. http://dx.doi.org/10.1108/cw-06-2019-0060.

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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with

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Orisian, J. E., H. Iwai, J. T. Walker, and R. W. Dutton. "A reply to "Comments on 'small geometry MOS Transistor capacitance measurement method using simple on-chip circuits'"." IEEE Electron Device Letters 6, no. 1 (1985): 64–67. http://dx.doi.org/10.1109/edl.1985.26043.

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Chih-Tang, Sah, and Jie Binbin. "The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)." Journal of Semiconductors 30, no. 2 (2009): 021001. http://dx.doi.org/10.1088/1674-4926/30/2/021001.

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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applicat

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HASSAN, TAREK M., та SOLIMAN A. MAHMOUD. "FULLY PROGRAMMABLE UNIVERSAL FILTER WITH INDEPENDENT GAIN-ω0-Q CONTROL BASED ON NEW DIGITALLY PROGRAMMABLE CMOS CCII". Journal of Circuits, Systems and Computers 18, № 05 (2009): 875–97. http://dx.doi.org/10.1142/s0218126609005411.

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A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 μA standby current. The digital programmability of the current conveyor, based on transisto

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Chéron, Jérôme, Michel Campovecchio, Denis Barataud, et al. "Electrical modeling of packaged GaN HEMT dedicated to internal power matching in S-band." International Journal of Microwave and Wireless Technologies 4, no. 5 (2012): 495–503. http://dx.doi.org/10.1017/s1759078712000530.

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The electrical modeling of power packages is a major issue for designers of high-efficiency hybrid power amplifiers. This paper reports the synthesis and the modeling of a packaged Gallium nitride (GaN) High electron mobility transistor (HEMT) associating a nonlinear model of the GaN HEMT die with an equivalent circuit model of the package. The extraction procedure is based on multi-bias S-parameter measurements of both packaged and unpackaged (on-wafer) configurations. Two different designs of 20 W packaged GaN HEMTs illustrate the modeling approach that is validated by time-domain load-pull

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Bult, K., and H. Wallinga. "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation." IEEE Journal of Solid-State Circuits 22, no. 3 (1987): 357–65. http://dx.doi.org/10.1109/jssc.1987.1052733.

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Girardi, Alessandro, and Sergio Bampi. "Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics." Journal of Integrated Circuits and Systems 2, no. 1 (2007): 22–28. http://dx.doi.org/10.29292/jics.v2i1.232.

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This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The

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