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Relevant bibliographies by topics / MOSFET Devices; Gate dielectrics; Threshold Voltage

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Academic literature on the topic 'MOSFET Devices; Gate dielectrics; Threshold Voltage'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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Journal articles on the topic "MOSFET Devices; Gate dielectrics; Threshold Voltage"

1

Tappin, Peter, Rajat Mahapatra, Nicolas G. Wright, Praneet Bhatnagar, and Alton B. Horsfall. "Simulation Study of High-k Materials for SiC Trench MOSFETs." Materials Science Forum 556-557 (September 2007): 839–42. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.839.

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This report investigates the advantages of high-k materials as gate dielectrics for high power SiC trench MOSFET devices, by means of TCAD simulation. The study makes a comparison between the breakdown characteristics of gate dielectrics comprising SiO2, HfO2 and TiO2. I-V and Transfer functions show forward characteristics with on-state resistivity of 8.27 m*⋅cm2, 8.65 m*⋅cm2, 15.8 m*⋅cm2 for the respective devices, at a gate voltage of 20 V. The threshold voltage is 10 V for all devices. The blocking voltage for the HfO2 and TiO2 is increased from 1800 V (for the SiO2 device) to 2200 V. With a peak electric field of 12 MV/cm through the oxide of the SiO2 device is reduced to 3.2 MV/cm for the HfO2 and 2.3 MV/cm for the TiO2 devices.

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Liu, Ao, Song Bai, Run Hua Huang, Tong Tong Yang, and Hao Liu. "Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement." Materials Science Forum 954 (May 2019): 133–38. http://dx.doi.org/10.4028/www.scientific.net/msf.954.133.

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The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

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Jaafar, Hind, Abdellah Aouaj, A. Bouziane, and Benjamin Iñiguez. "Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (2020): 52. http://dx.doi.org/10.11591/ijres.v9.i1.pp52-60.

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An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.

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Idris, Muhammad I., Ming Hung Weng, H. K. Chan, et al. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

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Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

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Sinha, Sanjeet Kumar, and Saurabh Chaudhury. "Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime." Journal of Nano Research 36 (November 2015): 64–75. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.64.

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In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

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Krishnaswami, Sumi, Sei Hyung Ryu, Bradley Heath, et al. "A Study on the Reliability and Stability of High Voltage 4H-SiC MOSFET Devices." Materials Science Forum 527-529 (October 2006): 1313–16. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1313.

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Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.

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Kumar, Arun, P. S. T. N. Srinivas, Shiv Bhushan, Sarvesh Dubey, Yatendra Kumar Singh, and Pramod Kumar Tiwari. "Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1555–64. http://dx.doi.org/10.1166/jno.2019.2658.

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In this paper, an analytical threshold voltage model of double gate-all-around metal-oxide-semiconductorfield-effect-transistors (DGAA MOSFETs) including the fringing field effects is developed. The total fringing capacitance arising due to induced fringing fields in the device is divided into inner, outer and bottom fringing capacitance. A simple expression for each fringe capacitance is developed individually. The 3-D Poisson's equation has been solved in the channel region using the parabolic potential approximation method to develop the surface potential expressions. The effects of fringing capacitances of inner and outer gates which causes charge induction in the source/drain regions have been incorporated within the developed surface potential expressions. The change in potential due to these induced charges of source/drain region along the channel is formulated and added with the developed surface potential expression at both surfaces. The obtained modified surface potential equations have been utilized to derive the expression of the threshold voltage of the device. The performance of the proposed model has been compared with the previously developed model of DGAA MOSFET structure without High-k dielectrics. The effects of variation of device parameters on the threshold voltage have been also analyzed. The accuracy of the proposed model has been verified by numerical simulation results obtained by a device simulator VTCAD from Cogenda Int.

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John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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Farzana, Esmat, Shuvro Chowdhury, Rizvi Ahmed та M. Ziaur Rahman Khan. "Performance Analysis of Nanoscale Double Gate MOSFETs with High-κ Gate Stack". Applied Mechanics and Materials 110-116 (жовтень 2011): 1892–99. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.1892.

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The performance and characteristics of Double Gate MOSFET with high dielectric constant (high-κ) gate stack have been analyzed and compared with those of conventional pure SiO2gate MOSFET. Quantum Ballistic Transport Model has been used to demonstrate the performance of the device in terms of threshold voltage, drain current in both low and high drain voltage regions and subthreshold swing. The effect of temperature on the threshold voltage and subthreshold characteristics has also been observed. This work reveals that improved performance of this structure can be achieved by scaling the gate length and illustrates its superiority over SiO2gate MOSFETs in achieving long-term ITRS goals.

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Nawaz, Muhammad. "On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs." Active and Passive Electronic Components 2015 (2015): 1–12. http://dx.doi.org/10.1155/2015/651527.

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This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2as a gate dielectric for 4H-SiC MOSFETs, high-kgate dielectric such as HfO2reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-kgate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2(k=3.9) to HfO2(k=25). This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2as gate dielectric than high-kdielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

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Dissertations / Theses on the topic "MOSFET Devices; Gate dielectrics; Threshold Voltage"

1

Seshadri, Sriram Mannargudi. "INVESTIGATION OF HIGH-k GATE DIELECTRICS AND METALS FOR MOSFET DEVICES." Master's thesis, University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3331.

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Progress in advanced microlithography and deposition techniques have made feasible high- k dielectric materials for MOS transistors. The continued scaling of CMOS devices is pushing the Si-SiO2 to its limit to consider high-k gate dielectrics. The demand for faster, low power, smaller, less expensive devices with good functionality and higher performance increases the demand for high-k dielectric based MOS devices. This thesis gives an in-depth study of threshold voltages of PMOS and NMOS transistors using various high-k dielectric materials like Tantalum pent oxide (Ta2O5), Hafnium oxide (HfO2), Zirconium oxide (ZrO2) and Aluminum oxide (Al2O3) gate oxides. Higher dielectric constant may lead to high oxide capacitance (Cox), which affects the threshold voltage (VT) of the device. The working potential of MOS devices can be increased by high dielectric gate oxide and work function of gate metal which may also influence the threshold voltage (VT). High dielectric materials have low gate leakage current, high breakdown voltage and are thermally stable on Silicon Substrate (Si). Different kinds of deposition techniques for different gate oxides, gate metals and stability over silicon substrates are analyzed theoretically. The impact of the properties of gate oxides such as oxide thickness, interface trap charges, doping concentration on threshold voltage were simulated, plotted and studied. This study involved comparisons of oxides-oxides, metals-metals, and metals-oxides. Gate metals and alloys with work function of less than 5eV would be suitable candidates for aluminum oxide, hafnium oxide etc. based MOSFETs.<br>M.S.E.E.<br>Department of Electrical and Computer Engineering<br>Engineering and Computer Science<br>Electrical Engineering

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Book chapters on the topic "MOSFET Devices; Gate dielectrics; Threshold Voltage"

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Yu, HongYu. "Metal Gate Electrode and High-Dielectrics for Sub-32nm Bulk CMOS Technology: Integrating Lanthanum Oxide Capping Layer for Low Threshold-Voltage Devices Application." In Solid State Circuits Technologies. InTech, 2010. http://dx.doi.org/10.5772/6879.

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Conference papers on the topic "MOSFET Devices; Gate dielectrics; Threshold Voltage"

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Wirths, Stephan, Yulieth Arango, Andrei Mihaila, et al. "Vertical Power SiC MOSFETs with High-k Gate Dielectrics and Superior Threshold Voltage Stability." In 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2020. http://dx.doi.org/10.1109/ispsd46842.2020.9170122.

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2

Lamba, V. K., Derick Engles, and S. S. Malik. "Modeling and Designing a Device Using MuGFETs." In ASME 2008 3rd Energy Nanotechnology International Conference collocated with the Heat Transfer, Fluids Engineering, and Energy Sustainability Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/enic2008-53015.

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This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

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Ji, F., J. P. Xu, J. J. Chen, H. X. Xu, C. X. Li, and P. T. Lai. "A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric." In 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009). IEEE, 2009. http://dx.doi.org/10.1109/edssc.2009.5394286.

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Sharma, Dheeraj, and Santosh Vishvakarma. "Analysis of crossover point and threshold voltage for triple gate MOSFET." In 2013 Spanish Conference on Electron Devices (CDE). IEEE, 2013. http://dx.doi.org/10.1109/cde.2013.6481352.

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Koh, R. "Simulation on the Threshold Voltage Adjustment of Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFET." In 1999 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1999. http://dx.doi.org/10.7567/ssdm.1999.b-8-3.

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Liu, C. T., and W. H. Lee. "Fabrications of Low threshold Voltage Organic Thin Film Transistor by Using Inkjet-Printed Hybrid Gate dielectrics." In 2012 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2012. http://dx.doi.org/10.7567/ssdm.2012.m-1-3.

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Dey Malakar, Tiya, Partha Bhattacharyya, and Subir Kumar Sarkar. "Quantum analytical modelling of threshold voltage for linearly graded alloy material gate recessed S/D SOI MOSFET." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8074056.

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Vishvakarma, S. K., B. Raj, R. Singh, C. R. Panda, A. K. Saxena, and S. Dasgupta. "Analytical modeling of threshold voltage for Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra Thin Body (UTB)." In 2007 International Workshop on Physics of Semiconductor Devices. IEEE, 2007. http://dx.doi.org/10.1109/iwpsd.2007.4472499.

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Lim, G. H., X. Zhou, K. Khu, et al. "Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch." In 2007 IEEE Conference on Electron Devices and Solid-State Circuits. IEEE, 2007. http://dx.doi.org/10.1109/edssc.2007.4450310.

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Horiguchi, Seiji, Akira Fujiwara, Hiroshi Inokawa, and Yasuo Takahashi. "Analysis of Back-Gate Voltage Dependence of Threshold Voltage of Thin SOI MOSFET and Its Application to Si Single-Electron Transistor." In 2003 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2003. http://dx.doi.org/10.7567/ssdm.2003.e-6-5.

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