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Prokhorov, Andrey, and Olesya Gerzheva. "Model of MOSFET in Delphi." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14209.
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In modern times the increasing complexity of transistors and their constant decreasingsize require more effective techniques to display and interpret the processes that are inside of devices. In this work, we are modeling a two‐dimensional n‐MOSFET with a long channeland uniformly doped substrate. We assume that this device is a large geometry device so that short‐channel and narrow‐width effects can be neglected. As a result of the thesis, a demonstration program was built. In this executable file, the user can choose parameters of the MOSFET‐model: drain and gate voltage, and different geometrical parameters of the device (junction depth and effective channel length). In the advanced regime of the program, the user can also specify the model re‐calculation parameter, doping concentration in n+ and bulk regions. The program shows the channel between the source and drain region with surface diagrams of carrier density and potential energy as an output. It is possible to save all calculated results to a file and process it in any other program, for example, plot graphics in Matlab or Matematica. The model can be used in lectures that are related to semiconductor physics in order to explain the basic working mechanisms of MOSFETs as well as for further detailed analysis of the processes in MOSFETs. It is possible to use our modeling techniques to rebuild the model in another computer language, or even to build other models of transistors, performing similar calculations and approximations. It is possible to download the executable file of the model here: http://studentdevelop.com/projects/MOSFET_model.zip
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Budihardjo, Irwan Kukuh. "A charge based power MOSFET model /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/5975.
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SUNDARAM, KARTHIK. "A DYNAMIC MOSFET MODEL IN VHDL-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1154637877.
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NEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
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Bordelon, John H. "A large-signal model for the RF power MOSFET." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15048.
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Menberu, Beniyam. "Analysis of hot-carrier AC lifetime model for MOSFET." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39386.
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Yoon, Kwang Sub. "A precision analog small-signal model for submicron MOSFET devices." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14935.
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Tuladhar, Looja R. "Resonant Power MOSFET Driver for LED Lighting." Youngstown State University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.
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GURUMURTHY, ARAVIND. "COMPARISON OF BEHAVIOR OF MOSFET TRANSISTORS DESCRIBED IN HARDWARE DESCRIPTION LANGUAGES." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141363591.
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Dalin, Johan. "Fabrication and characterisation of a novel MOSFET gas sensor." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1292.
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A novel MOSFET gas sensor for the investigation has been developed. Its configuration resembles a"normally on"n-type thin-film transistor (TFT) with a gas sensitive metal oxide as a channel. The device used in the experiments only differs from common TFTs in the gate configuration. In order to allow gas reactions with the SnO2-surface, the gate is buried under the semiconducting layer. Without any gate voltage, the device works as a conventional metal oxide gas sensor. Applied gate voltages affect the channel carrier concentration and surface potential of the metal oxide, thus causing a change in sensitivity. The results of the gas measurements are in accordance with the electric adsorption effect, which was postulated by Fedor Wolkenstein 1957, and arises the possibility to operate a semiconductor gas sensor at relatively low temperatures and, thereby, be able to integrate CMOS electronics for processing of measurements at the same chip.
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Kaytaz, V. Gunhan. "A new simulation model of coupled electro-thermal performance for MOSFET devices." Ann Arbor, Mich. : Proquest, 2005. http://proquest.umi.com/pqdweb?index=0&did=982819651&SrchMode=1&sid=2&Fmt=2&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1187711746&clientId=57025.
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Silva, Maurício Banaszeski da. "A physics-based statistical random telegraph noise model." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/150171.
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O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito.Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.
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Soukal, Pavel. "Model stárnutí unipolárního tranzistoru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217677.
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According to non-stopable progress in wireless communications, it is desirable to integrate the RF front-end with the baseband building blocks of communication circuits into a one chip in the recent years. The CMOS technology advances, this is the reason why it becomes attractive for system-on-a-chip implementation, but CMOS device is getting shrink, so the channel electric field increasing and the hot carrier (HCI) effect becomes more significant. If the oxide is scaled down to less than 3 nm, then there is the possibility of soft or hard oxide breakdown (S/HBD) often takes place. As a result of the oxide trapping and interface generation is the long term performance drift and related reliability problems in devices and circuits. During the scaling and increasing chip power dissipation operating temperatures for device have also is increasing. Another reliability concern is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias are arising while the operation temperature of devices is increasing. Parameter’s extraction is a very important part of the current electronic components modeling process, as it looking for the value of the unknown parameters in mathematical model, which represents physical behavior of given electronic component. The problem of parameter extraction is that fits electronic components mathematical model to a measured data set is an ill-posed problem and its solution is inherently difficult. This diploma thesis presents the parameter extraction, optimization methodology and verifies it on a case study of a MOSFET mathematical models (LEVEL1, LEVEL2 and LEVEL3) parameter extraction. The presented nonlinear method is based on the method of the least squares, which is solved with the aid of Levenberg- Marquardt’s algorithm.
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Guarnay, Sébastien. "Étude des mécanismes de dégradation de la mobilité sur les architectures FDSOI pour les noeuds technologiques avancés (<20nm)." Thesis, Paris 11, 2015. http://www.theses.fr/2015PA112053/document.
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Pour augmenter les performances des MOSFET, il est indispensable de comprendre les différents phénomènes physiques qui dégradent la mobilité apparente des électrons et trous traversant le canal et qui limitent l’amélioration obtenue par réduction de sa longueur. Pour cela, une étude précise du transport par des simulations Monte-Carlo a été effectuée. Cette méthode de simulation semi-classique permet de résoudre l’équation de transport de Boltzmann en prenant en compte à la fois le régime quasi-balistique, les interactions avec les phonons, les impuretés ionisées, la rugosité de surface, et le confinement quantique, par génération aléatoire des électrons et de leurs interactions, décrites selon les lois de la mécanique quantique.Un modèle simple de mobilité a alors pu être établi et validé par les simulations. Il est basé sur trois paramètres importants : la mobilité à canal long, la résistance d’accès et la résistance balistique. Ce modèle de mobilité s’est avéré compatible avec des résultats expérimentaux, ce qui suggère que la résistance d’accès est déterminante dans la réduction de mobilité apparente.Par ailleurs, la contribution du transport balistique dans la mobilité a été calculée en tenant compte précisément du confinement quantique et des fonctions de distribution des différentes sous-bandes, ce qui a ainsi permis d’améliorer le modèle de mobilité apparente de Shur qui sous-estime (d’environ 50 Ω.µm) la résistance balistique. Cette résistance balistique est inférieure à la résistance d’accès mais elle pourrait avoir une incidence sur les dispositifs ultimesTo improve the MOSFET performances, it is necessary to understand the physical phenomena contributing to the apparent mobility of electrons and holes crossing the channel, and limiting the improvement obtained by reducing the channel length. Therefore, a precise study of transport using Monte Carlo simulations was performed. This semi-classical simulation method allows for solving the Boltzmann transport equation, taking into account the quasi-ballistic regime, phonon and Coulomb scattering, surface roughness, as well as the quantum confinement, by randomly generating electrons and their scattering events described by the laws of quantum mechanics.A simple mobility model has been established and validated by the simulations. It is based upon three important parameters: the long channel mobility, the access resistance, and ballistic resistance. This mobility model proved compatible with experimental results, suggesting that the access resistance is determining in the apparent mobility reduction.By the way, the ballistic transport contribution in the mobility was calculated by taking into account the quantum confinement accurately and the distribution functions of the different subbands, allowing for an improvement of Shur’s apparent mobility model, which underestimates (of about 50 Ω.µm) the ballistic resistance. The latter is lower than the access resistance but it could have an incidence on the ultimate devices.Keywords: MOSFET, FDSOI, mobility degradation, analytical model, contact resistance, ballistic, multi-subband Monte Carlo, simulation
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Ewert, Tony. "Advanced TCAD Simulations and Characterization of Semiconductor Devices." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-6883.
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Pumarica, Julio César Saldaña. "Projeto de modelos neurais pulsados em CMOS." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3142/tde-01032011-115940/.
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O presente trabalho descreve o projeto de modelos neurais pulsados em tecnologia CMOS. Foram projetados dois modelos: um neurônio baseado em condutâncias e um neurônio do tipo integra e dispara. O primeiro gera impulsos elétricos similares aos potenciais de ação gerados pelo neurônio biológico. Mediante simulação, foram observadas as seguintes características: disparo do impulso quando se atinge a tensão de limiar, hiperpolarização após o potencial de ação, retorno passivo à tensão de repouso, presença de período refratário e relação sigmoide entre a frequência de disparo e a intensidade do estímulo. Da mesma maneira, foi reproduzida a curva mínima duração x amplitude de estímulo típico dos neurônios biológicos. O segundo realiza a codificação de uma grandeza analógica na fase relativa dos impulsos elétricos gerados. Os impulsos gerados pelo circuito estão afastados em relação a um sinal periódico, em um intervalo que apresenta uma dependência logarítmica de uma corrente de entrada. John Hopfield propus esse tipo de codificação para explicar o reconhecimento de padrões com independência de escala, realizado pelo cérebro humano. No decorrer da pesquisa, foi necessário desenvolver algumas expressões analíticas para o projeto de circuitos de baixa frequência em CMOS, não encontradas na literatura estudada. As expressões estão baseadas na equação da corrente do transistor MOS proposta no modelo conhecido como Advanced Compact Mosfet (ACM). O projeto, implementação e testes de um transcondutor linearizado, e os resultados das simulações dos modelos neurais projetados, demonstram a validade das expressões desenvolvidas.This work describes the design of pulsed neural models in CMOS technology. Two models were designed: a conductance based neuron and an integrate and fire neuron. The first generates electrical impulses similar to action potentials generated by the biological neuron. Through simulation, the following characteristics were observed: pulse trigger after reaching threshold voltage, hyperpolarization after the action potential, passive return to resting potential, presence of refractory period and sigmoid relationship between the firing rate and the stimulus intensity. Likewise, the curve minimal duration vs stimulus amplitude typical of biological neurons was reproduced. The second one performs the encoding of an analog input in the relative phase of electrical impulses. The impulses generated by the circuit are delayed with respect to a reference periodic signal, in a range that has a logarithmic dependence on an input current. John Hopfield proposed this type of encoding to explain the scale independent pattern recognition performed by the human brain. During the research, it was necessary to develop some analytical expressions for the design of low-frequency circuits in CMOS, not found in the literature studied. The expressions are based on the Advanced Compact MOSFET (ACM) model. The design, implementations and testing of a linearized transconductor, and the simulations results of the neural models designed, demonstrate the validity of the expressions developed.
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Sarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell." Thesis, Indian Institute of Science, 1995. http://hdl.handle.net/2005/124.
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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the
possibility of fabrication of LBTs with a CMOS technology is established.
Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same.
A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
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Persson, Stefan. "Modeling and characterization of novel MOS devices." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3720.
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Challenges with integrating high-κ gate dielectric,retrograde Si1-xGexchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si1-xGex surface-channel and different high-κgate dielectric are examined. Si1-xGex ρMOSFETs with an Al2O3/HfAlOx/Al2O3nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si1-xGexρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si1-xGexρMOSFETs.
Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si1-xGexincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si1-xGex/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi2-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi1-xGex is found to form on selectively grown p-typeSi1-xGexused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi1-xGex/p-type Si1-xGexcontacts is 5´10-8Ωcm2, which satisfies the requirement for the 45-nmtechnology node in 2010.
When the Si1-xGexchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi1-xGexretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.
Key Words:MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.
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Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.
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Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.
The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.
The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.
Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions.
The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.
We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.
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Chevillon, Nicolas. "Etude et modélisation compacte du transistor FinFET ultime." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00750928.
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Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.
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李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.
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Sow, Amadou Tidiane. "Evaluation de la fiabilité d'un générateur à rayons X pour application médicale." Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0120/document.
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Les systèmes d’imagerie médicale, principalement les systèmes à rayons X, sont devenus incontournables dans le diagnostic et le traitement des maladies complexes. Le générateur à rayons X fait partie des sous-systèmes critiques d’un système à rayons X. La technologie des générateurs à rayons X se complexifie et les contraintes vues par les composants augmentent. L’évaluation de la fiabilité du générateur à rayons X est par conséquent nécessaire afin d’optimiser la durée de vie de ce dernier. Dans ces travaux de thèse, une méthodologie d’évaluation de la fiabilité d’un générateur à rayons X est proposée. La méthodologie repose sur l’évaluation de la fiabilité allant du composant au système. Des essais de vieillissement sont d’abord réalisés au niveau des composants critiques du générateur afin d’identifier les mécanismes de défaillance et de construire les courbes de durée de vie permettant d’effectuer une prévision de fiabilité. Les paramètres du recueil de fiabilité FIDES ont aussi été utilisés pour construire les courbes de durée de vie des composants critiques. Une méthode de prévision de la fiabilité basée sur l’hypothèse du dommage cumulé avec la règle de Miner est proposée pour évaluer la durée de vie des composants critiques sous contraintes thermomécaniques. Cette méthode utilise les règles de comptage rainflow pour obtenir une distribution des différences de température vues par les composants critiques. Une association de fiabilité permet enfin d’estimer la durée de vie de chaque sous système du générateur à rayons X à travers ses composants critiquesMedical imaging systems, mainly X-rays imaging systems, have become essential in the diagnosis and treatment of complex diseases. X-rays generator is one of the critical subsystems of a medical system. Its technology became more complex and constraints seen by the components increase. An assessment of X-rays generator reliability is therefore necessary to optimize its lifetime. In this thesis, a reliability assessment method of an X-rays generator is proposed. The methodology is based on the assessment of the reliability from component to system. Aging tests are first performed for X-rays generator critical components in order to identify failure mechanisms and build lifetime curves for performing reliability prediction. FIDES guide parameters were also used to construct critical components lifetime curves. A reliability prediction method based on the assumption of cumulative damage with Miner's rule is proposed to evaluate critical components lifetime under thermomechanical stresses. This method uses rainflow counting rules for the temperature cycles distribution of critical components. A reliability block diagram is finally used to estimate the lifetime of each X-ray generator subsystem through its critical components
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Salameh, Lynne Rafik. "An analysis of posynomial MOSFET models using genetic algorithms and visualization." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/41549.
Full textAbstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 89-90).
Analog designers are interested in optimization tools which automate the process of circuit sizing. Geometric programming, which uses posynomial models of MOSFET parameters, represents one such tool. Genetic algorithms have been used to evolve posynomial models for geometric programs, with a reasonable mean error when modeling MOSFET parameters. By visualizing MOSFET data using two dimensional plots, this thesis investigates the behavior of various MOSFET small and large signal parameters and consequently proposes a lower bound on the maximum error, which a posynomial cannot improve upon. It then investigates various error metrics which can be used to balance the mean and maximum errors generated by posynomial MOSFET models. Finally, the thesis uses empirical data to verify the existence of the lower bound, and compares the maximum error from various parameters modeled by the genetic algorithm and by monomial fitting. It concludes that posynomial MOSFET models suffer from inherent inaccuracies. Additionally, although genetic algorithms improve on the maximum model error, the improvement, in general, does not vastly surpass results obtained through monomial fitting, which is a less computationally intensive method. Genetic algorithms are hence best used when modeling partially convex MOSFET parameters, such as ro.
by Lynn Rafik Salameh.
M.Eng.
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Warnock, Shireen M. "A ballistic transport model for HEMTs and III-V MOSFETs." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85520.
Full textAbstract:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 77-78).
As silicon MOSFETs keep scaling down in size, the continued improvement on their logic performance is threated by their fundamental physical limits. With silicon approaching these limits, MOSFETs designed with III-V semiconductors have emerged as promising candidates to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs allow both faster and more power efficient performance. One of the key challenges, particularly as devices continue to shrink, is to understand the important of non-idealities in FET structures. High-electron mobility transistors, or HEMTs, are III-V Quantum-Well FETs that we can use to explore many issues of relevance to future III-V MOSFETs. HEMTs are worthwhile transistors in their own right, but are also simpler than III-V MOSFETs and therefore allow a more thorough exploration into the basic transport physics of a quantum-well III-V device. We know from HEMT experimental data that electrons travel ballistically at gate lengths of 30- 40 nm, suggesting that a ballistic transport model will only become more accurate as channel lengths are scaled down to 10 nm. We would like to investigate to what extent this is true in III-V MOSFETs, and also to study the impact of short channel effects and other parasitics inherent to a III-V design. To accomplish these goals, we have developed a flexible transistor model in MATLAB based on a ballistic theory of transport. We will first verify the model with HEMT experimental data coming from devices fabricated at MIT, and then focus our attention on peculiarities specific to III-V MOSFETs, namely a buried-channel design and the presence of traps at the oxide-semiconductor interface. We will use the model to extract the trap density as a function of energy, and then make measurements independent of interface trap effects to extract the 2D sheet carrier concentration and mobility, two figures of merit important in characterizing FET devices. The ability to correctly model and predict device behavior will help identify the problems ahead that need improvement in the iterations of future device fabrication.
by Shireen M. Warnock.
M. Eng.
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Ruffilli, Roberta. "Modes de fatigue des métallisations à base d'aluminium dans les composants MOSFET de puissance." Thesis, Toulouse 3, 2017. http://www.theses.fr/2017TOU30256/document.
Full textAbstract:
Cette thèse, effectuée en collaboration entre le CEMES-CNRS, le laboratoire Satie (ENS Cachan) et NXP Semiconductors est motivée par la compréhension des mécanismes de défaillance des dispositifs MOSFET pour les applications dans l'industrie automobile. Un facteur limitant de la fiabilité à long terme des modules de puissance basse tension est le vieillissement électrothermique et/ou thermo-mécanique des parties métalliques de la source: métallisation en aluminium (ou alliage) et fils de connexion. A cause de la différence de coefficient de dilatation thermique entre la métallisation les oxydes et le substrat semi-conducteur, la température atteinte pendant les cycles de fonctionnement (quelques centaines de degrés), induit une déformation plastique inévitable dans le métal, qui est le matériau le plus mou dans l'architecture complexe du MOSFET. Nous avons caractérisé la microstructure métallique avant et après les tests de vieillissement électrothermique accélérés, en utilisant des techniques spécifiques du domaine de la métallurgie physique: microscopie électronique et ionique, cartographie d'orientation de grains et de la composition chimique. Pour la première fois, la métallisation de la source a été caractérisée sous les fils de connexion, qui sont cent fois plus épais que la métallisation. Cet emplacement est critique pour la fiabilité du composant, car le processus de soudure par ultrasons induit une déformation plastique importante qui peut affaiblir la métallisation initiale avant le vieillissement. Ceci est peu étudié dans la littérature en raison de la difficulté à accéder à la métallisation sous les fils sans altérer leur interface, souvent endommagée et fragilisée dans les modules vieillis. Nous avons mis en place des méthodes de préparation d'échantillon, basées sur le polissage ionique, pour étudier cette interface, sans introduire d'artefacts de préparation. Le processus de soudure à froid induit une déformation plastique sévère et non uniforme dans la métallisation sous les fils sans parvenir à recréer un bon contact électrique: de petites cavités et des résidus d'oxyde natif, ont été systématiquement observés à l'interface Al / Al, dans tous les modules analysés, avant et après vieillissement. Le mécanisme principal de défaillance des modules est la génération et la propagation de fissures de fatigue dans l'aluminium, associée à une oxydation locale qui empêche la fermeture de ces fissures. Sous et en dehors des fils de connexion, ces fissures traversent la métallisation perpendiculairement à la surface jusqu'au substrat en silicium en suivant les joints de grains. Cette fissuration est due à la diffusion intergranulaire accélérée des atomes d'aluminium. Dans la zone de soudure, le phénomène de fissuration parallèle à l'interface est favorisé par les imperfections initiales (cavités, oxyde). Les expériences de tomographie ionique ont montré que ces fissures sont confinées à l'interface fil-métal et ne se propagent pas dans le fil malgré sa plus faible résistance mécanique (Al pur, structure à grains plus grands). La propagation de la fissure le long de l'interface Al/Al peut provoquer une diminution du contact entre le fil et la métallisation de la source et éventuellement son décollement. Les fissures dans le métal source peuvent expliquer l'augmentation locale de la résistance et de la température du module qui accélère le processus de vieillissement jusqu'à l'échec. Cette étude a établi de nouvelles techniques dédiées et des méthodes de quantification pour évaluer le vieillissement des parties métalliques des modules MOSFET. La caractérisation complète de l'interface soudée, intrinsèquement défectueuse et la dégradation de la métallisation pendant le vieillissement électrothermique ouvrent la voie à l'amélioration possible les technologies actuelles et au développement potentiel de nouveaux procédésThis thesis, a collaboration between CEMES-CNRS, Satie laboratory (ENS Cachan) and NXP Semiconductors is motivated by the comprehension of the failure mechanisms of low voltage power MOSFET devices produced for ap- plications in the automotive industry. A limiting factor for the long-term reliability of power modules is the electro- thermal and/or thermo-mechanical aging of the metallic parts of the source: Al metallization and bonding wires. At the temperature reached during the on-off operating cycles (few hundred degrees), the difference in the coefficient of thermal expansion between the metallization and the oxide and semicon- ductor parts induces an inevitable plastic deformation in the metal, which is the softest material in the complex MOSFET architecture. We have characterized the metal microstructure before and after accelerated electro-thermal aging tests, by using specific techniques from the field of the physical metallurgy: electron and ion microscopy, grain orientation and chem- ical composition mapping. For the first time the source metallization has been characterized both away and under the bonding connections, which are one hundred times thicker than the metallization layer. The latter is a critical loca- tion for the reliability assessment because the ultrasonic bonding process may weaken the initial metallization microstructure by adding an important plas- tic deformation prior to aging. This is, however, poorly stated in the literature because of the difficulty to access the metallization under the wires without damaging their bonding, which is known to be particularly weak in case of aged modules. In order to investigate the wire-metallization interface, we have set up origi- nal sample preparations, based on ion polishing, that allowed us to disclose the metallization under the bonding wires without introducing preparation artifacts in the microstructure. The bonding process induces a severe and non- uniform plastic deformation in the metallization under the wires without re- creating a good electrical contact: small cavities and native oxide residues, have been systematically observed at the Al/Al interface, in all the analyzed mod- ules, before and after aging. The main mechanism behind the device failure is the generation and propa- gation of fatigue cracks in the aluminum metallization, associated to a local Al oxidation that prevents these crack from closing. Away and under the wire bonds, they run perpendicularly from the surface down to the silicon substrate following the grain boundaries, due to an enhanced intergranular diffusion of aluminum atoms. In the bonding area, the phenomenon of parallel cracking is favored by the initial imperfections in the wire-metallization bonding. Ion to- mography experiments have shown that these cracks are confined to the wire- metal interface and do not propagate in the wire despite its lower strength (pure Al, larger grain structure). Crack propagation along the Al/Al interface can cause a contact reduction between the wire and the source metallization and eventually its failure. Such discontinuities in the metal can explain the lo- cal increase in the device resistance and temperature that accelerates the aging process until failure. This study settled new, dedicated techniques and quantification methods to as- sess the aging of the metal parts of MOSFET devices. The full characterization of the intrinsically defective interface generated by the bonding process and the metallization degradation during electro-thermal aging indicated paths to possible improvements of current technologies and potential developments of new processes
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Cheralathan, Muthupandian. "Compact modeling for multi-gate mosfets using advanced transport models." Doctoral thesis, Universitat Rovira i Virgili, 2013. http://hdl.handle.net/10803/111165.
Full textAbstract:
En aquesta tesi hem desenvolupat models compactes que incorporen un model de
transport hidrodinàmic adaptat a multi-gate (principalment double-gate (DG) and
surrounding-gate (SRG) MOSFETs a partir de models unificats de control de càrrega I
del potencial de superfície, obtinguts de l’equació de Poisson. Tots aquests dispositius
es modelitzen seguint un esquema semblant. El corrent i càrregues totals s’escriuen en
funció de les densitats de càrrega mòbil per unitat d’àrea als extrems drenador i font del
canal. Els efectes de canal curt i quàntics també s’inclouen en el model compacte
desenvolupat. El model desenvolupat mostra un bon acord amb simulacions numèriques
2D i 3D en tots els règims d’operació. El model desenvolupat s’implementa i testeja al
simulador de circuits SMASH per a l’anàlisi dels comportaments DC i transitori de
circuits CMOS.En esta tesis hemos desarrollado modelos compactos que incorporan un modelo de transporte hidrodinámico adaptado a multi-gate (principalmente double-gate (DG) and surrounding-gate (SRG) MOSFETs a partir de modelos unificados de control de carga I del potencial de superficie, obtenidos de la ecuación de Poisson. Todos estos dispositivos se modelizan siguiendo un esquema similar. La corriente y cargas totales escriben en función de las densidades de carga móvil por unidad de área en los extremos drenador y fuente del canal. Los efectos de canal corto y cuánticos también se incluyen en el modelo compacto desarrollado. El modelo desarrollado muestra un buen acuerdo con simulaciones numéricas 2D y 3D en todos los regímenes de operación. El modelo desarrollado se implementa y testea el simulador de circuitos SMASH para el análisis de los comportamientos DC y transitorio de circuitos CMOS.
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Sylin, Ståhlberg Erika, and Madelene Andersson. "Kawamodellen, Model of Human Occupation, Canadian Model of Occupational Performance och Mosey´s modell : - en studie avseende aktivitet, person, omgivning och kultur." Thesis, Örebro University, School of Health and Medical Sciences, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-5279.
Full textAbstract:
Bakgrund: Valet av uppsatsämne berör de ökade kraven på kulturell kompetens som ställs på arbetsterapeuter. Att granska och förstå arbetsterapeutiska teorier är viktigt för att ha förmågan att överföra teorierna i praktiken.
Syfte: Syftet är att beskriva begreppen aktivitet, person, omgivning och kultur i, de arbetsterapeutiska teoretiska modellerna, Kawamodellen, MOHO, CMOP och Mosey´s modell.
Metod: Arbetet är en studie där datainsamling och analys har varit en jämsides process som kontinuerligt har växt fram.
Analysen har genomförts av utvalda begrepp från de olika teorierna och har bestått i en beskrivning av begrepp som sedan har jämförts mellan de olika teorierna.
Huvudresultat: Det huvudsakliga resultatet är att uppfattningen om personens placering i förhållande till omgivningen i de olika modellerna har del i hur aktivitet förklaras.
I Kawamodellen har begreppet person en decentraliserad plats och omfattas av omgivningen. Mänsklig aktivitet bestäms utifrån den sociala situationen och inte utifrån ett centralt placerat jag. Att göra något som har betydelse för kollektivet har högre prioritet än att göra något för sig själv som individ. I övriga modeller är begreppet person ett fristående, centraliserat begrepp med olika grad av närhet till omgivningen.
Slutsats: Slutsatsen är att både skillnader och likheter, avseende aktivitet, finns mellan Kawamodellen och de modeller vi har studerat i den analys vi har genomfört. Centrala begrepp inom arbetsterapi kan tolkas på skilda sätt i olika kulturer. Arbetsterapeuter bör vara medvetna om att kulturella skillnader finns, vara mottagliga för dem och därmed också förberedda på att bemöta dem.
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Chiappori, Guido Jose. "Système de stabilisation de la tension batterie pour la fonction Stop-Start automobile : solution à composants de puissance commandés en linéaire." Thesis, Ecole centrale de Lille, 2015. http://www.theses.fr/2015ECLI0005/document.
Full textAbstract:
Cette thèse présente un nouveau système de stabilisation de la tension batterie spécialement destinés aux véhicules Stop-Start, économique et compact, nommé LVSS (Linear Voltage Stabilization System). Le LVSS se comporte comme une résistance variable et limite le courant à l’aide de transistors MOSFET fonctionnant en mode linéaire. Il permet donc de stabiliser la tension de la batterie pendant le démarrage du moteur à combustion interne (ICE). Un prototype a été conçu et testé sur une voiture. Les résultats ont montré que la tension était stabilisée tout en limitant le courant de démarrage. De plus la solution proposée n’impacte pas sur les performances globales du système Stop-Start et comme les transistors fonctionnent en mode linéaire, cette solution n’émet pas de perturbations CEMThis thesis presents a new Linear Voltage Stabilization System (LVSS) specially designed for µ-hybrid vehicles using the Stop-Start function. The LVSS stabilizes the battery voltage during the start-up of the Internal Combustion Engine (ICE) limiting the start-up current using parallels MOSFETs working in linear mode. A prototype was developed and tested in a car. Results have shown the battery voltage properly stabilized limiting the start-up current. Furthermore the proposed solution does not impact on the overall performance of the Stop-Start. Main advantages are its small volume, low price and the fact that there is no EMC perturbation as transistors work in linear mode
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Benson, James. "A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69885/.
Full textAbstract:
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications. The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum. In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect. As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25μm, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters.
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Boige, François. "Caractérisation et modélisation électrothermique compacte étendue du MOSFET SiC en régime extrême de fonctionnement incluant ses modes de défaillance : application à la conception d'une protection intégrée au plus proche du circuit de commande." Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0084/document.
Full textAbstract:
Le défi de la transition vers une énergie sans carbone passe, aujourd’hui, par un recours systématique à l’énergie électrique avec au centre des échanges l’électronique de puissance. Pour être à la hauteur des enjeux, l'électronique de puissance nécessite des composants de plusen plus performants pour permettre un haut niveau d'intégration, une haute efficacité énergétique et un haut niveau de fiabilité. Aujourd’hui, le transistor de puissance, du type MOSFET, en carbure de silicium (SiC) est une technologie de rupture permettant de répondre aux enjeux d’intégration et d’efficacité par un faible niveau de perte et une vitesse de commutation élevée. Cependant, leur fiabilité non maitrisée et leur faible robustesse aux régimes extrêmes du type court-circuit répétitifs freinent aujourd’hui leur pénétration dans les applications industrielles. Dans cette thèse, une étude poussée du comportement en court-circuit d'un ensemble exhaustif de composants commerciaux, décrivant toutes les variantes structurelles et technologiques en jeu, a été menée sur un banc de test spécifique développé durant la thèse, afin de quantifier leur tenue au courtcircuit. Cette étude a mis en lumière des propriétés à la fois génériques et singulières aux semiconducteurs en SiC déclinés en version MOSFET tel qu’un courant de fuite dynamique de grille et un mode de défaillance par un court-circuit grille-source amenant, dans certaines conditions d'usage et pour certaines structures de MOSFET, à un auto-blocage drain-source. Une recherchesystématique de la compréhension physique des phénomènes observés a été menée par une approche mêlant analyse technologique interne des composants défaillants et modélisation électrothermique fine. Une modélisation électrothermique compacte étendue à la prise en compte des modes de défaillance a été établie et implémentée dans un logiciel de type circuit. Ce modèle a été confronté à de très nombreux résultats expérimentaux sur toutes les séquences temporelles décrivant un cycle de court-circuit jusqu'à la défaillance. Ce modèle offre un support d'analyse intéressant et aussi une aide à la conception des circuits de protection. Ainsi, à titre d'application, un driver doté d'une partie de traitement numérique a été conçu et validé en mode de détection de plusieurs scénarii de court-circuit mais aussi potentiellement pour la détection de la dégradation de la grille du composant de puissance. D’autres travaux plus exploratoires ont aussi été menés en partenariat avec l’Université de Nottingham afin d’étudier l'impact de régimes de court-circuit impulsionnels répétés sur le vieillissement de puces en parallèle présentant des dispersions. La propagation d'un premier mode de défaillance issu d'un composant "faible" a aussi été étudiée. Ce travail ouvre la voie à la conception de convertisseurs intrinsèquement sûrs et disponibles en tirant parti des propriétés atypiques et originales des semi-conducteurs en SiC et du MOSFET en particulierNowaday, the challenge of the transition to carbon-free energy involves a systematic use of electrical energy with power electronics at the heart of the exchanges. To meet the challenges, power electronics requires increasingly high-performance devices to provide a high level of integration, high efficiency and a high level of reliability. Today, the power transistor, of the MOSFET type, made of silicon carbide (SiC) is a breakthrough technology that allows us to meet the challenges of integration and efficiency through their low level of loss and high switching speed. However, their limited reliability and low robustness at extreme operating conditions such as repetitive short-circuits are now hindering their expansion in industrial applications. In this thesis, an in-depth study of the short-circuit behaviour of an exhaustive set of commercial devices, describing all the structural and technological variants involved, was carried out on a specific test bench developed during the thesis, in order to quantify their short-circuit resistance. This study highlighted both generic and singular properties of SiC semiconductors for every Mosfet version such as a dynamic gate leakage current and a failure mode by a short-circuit grid-source leading, under certain conditions of use and for certain Mosfet structures, to a self-blocking drain-source. A systematic research of the physical understanding of the observed mechanisms was carried out by an approach combining an internal technological analysis of the failed devices and a fine electrothermal modelling. A compact electrothermal modeling extended to failure mode consideration has been established and implemented in circuit software. This model was confronted with numerous experimental results describing a short-circuit cycle up to failure. This model offers an interesting analytical support and also helps the design of protection circuits. Thus, as an application, a driver equipped with a digital processing part has been designed and validated in detection mode for several short-circuit scenarios but also potentially for the detection of the degradation of the power component grid. Other more exploratory work has also been carried out in partnership with the University of Nottingham to study the impact of repeated pulse short-circuit regimes on the aging of parallel chips with dispersions. The propagation of a first failure mode from a "weak" device was also studied. This work paves the way for the design of intrinsically safe and available converters by taking advantage of the atypical and original properties of SiC semiconductors and Mosfet in particular
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Moldovan, Oana. "Devenlopment of Compact Small Signal Quasi Static Models for Multiple Gate Mosfets." Doctoral thesis, Universitat Rovira i Virgili, 2008. http://hdl.handle.net/10803/8459.
Full textAbstract:
En esta tesis hemos desarrollado los modelos compactos explícitos de carga y de capacitancia adaptados para los dispositivos dopados y no dopados de canal largo (DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados) de un modelo unificado del control de carga derivado de la ecuación de Poisson. El esquema de modelado es similar en todos estos dispositivos y se adapta a cada geometría. Los modelos de la C.C. y de la carga son completamente compatibles. Las expresiones de la capacitancia se derivan del modelo de la carga. La corriente, la carga total y las capacitancias se escriben en términos de las densidades móviles de la carga en los extremos de fuente y drenador del canal. Las expresiones explícitas e infinitamente continuas se utilizan para las densidades móviles de la carga en la fuente y drenador. Las capacitancias modeladas demuestran el acuerdo excelente con las simulaciones numéricas 2D y 3D (SGT), en todos los regímenes de funcionamiento. Por lo tanto, el modelo es muy prometedor para ser utilizado en simuladores del circuito. Desafortunadamente, no mucho trabajo se ha dedicado a este dominio de modelado. Las cargas analíticas y las capacitancias, asociadas a cada terminal se prefieren en la simulación de circuito. Con respecto al SGT MOSFET, nuestro grupo fue el primero en desarrollar y publicar un modelo de las cargas y de las capacitancias intrínsecas, que es también analítico y explícito. La tesis es organizada como sigue: el capítulo (1) presenta el estado del arte, capítulo (2) el modelado compacto de los cuatro dispositivos: DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados; en el capítulo (3) estudiamos las capacitancias de fricción en MuGFETs. Finalmente el capítulo (4) resuma el trabajo hecho y los futuros objetivos que necesitan ser estudiados. Debido a la limitación de los dispositivos optimizados disponibles para el análisis, la simulación numérica fue utilizada como la herramienta principal del análisis. Sin embargo, cuando estaban disponibles, medidas experimentales fueron utilizadas para validar nuestros resultados. Por ejemplo, en la sección 2A, en el caso de DG MOSFETs altamente dopados podríamos comparar nuestros resultados con datos experimentales de FinFETs modelados como DG MOSFETs. La ventaja principal de este trabajo es el carácter analítico y explícito del modelo de la carga y de la capacitancia que las hace fácil de implementar en simuladores de circuitos. El modelo presenta los resultados casi perfectos para diversos casos del dopaje y para diversas estructuras no clásicas del MOSFET (los DG MOSFETs, los UTB MOSFETs y los SGTs). La variedad de las estructuras del MOSFET en las cuales se ha incluido nuestro esquema de modelado y los resultados obtenidos, demuestran su validez absoluta. En el capítulo 3, investigamos la influencia de los parámetros geométricos en el funcionamiento en RF de los MuGFETs. Demostramos el impacto de parámetros geométricos importantes tales como el grosor de la fuente y del drenador o, el espaciamiento de las fins, la anchura del espaciador, etc. en el componente parásito de la capacitancia de fricción de los transistores de la múltiple-puerta (MuGFET). Los resultados destacan la ventaja de disminuir el espaciamiento entre las fins para MuGFETs y la compensación entre la reducción de las resistencias parásitas de fuente y drenador y el aumento de capacitancias de fricción cuando se introduce la tecnología del crecimiento selectivo epitaxial (SEG). La meta de nuestro estudio y trabajo es el uso de nuestros modelos en simuladores de circuitos. El grupo de profesor Aranda, de la Universidad de Granada ha puesto el modelo actual de SGT en ejecución en el simulador Agilent ADS y buenos resultados fueron obtenidos.
In this thesis we have developed explicit compact charge and capacitance models adapted for doped and undoped long-channel devices (doped Double-Gate (DG) MOSFETs, undoped DG MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and undoped Surrounding Gate Transistor (SGT)) from a unified charge control model derived from Poisson's equation. The modelling scheme is similar in all these devices and is adapted to each geometry. The dc and charge models are fully compatible. The capacitance expressions are derived from the charge model. The current, total charges and capacitances are written in terms of the mobile charge sheet densities at the source and drain ends of the channel. Explicit and infinitely continuous expressions are used for the mobile charge sheet densities at source and drain. As a result, all small signal parameters will have an infinite order of continuity. The modeled capacitances show excellent agreement with the 2D and 3D (SGT) numerical simulations, in all operating regimes. Therefore, the model is very promising for being used in circuit simulators.
Unfortunately, not so much work has been dedicated to this modelling domain. Analytical charges and capacitances, associated with each terminal are preferred in circuit simulation. Regarding the surrounding-gate MOSFET, our group was the first to develop and publish a model of the charges and intrinsic capacitances, which is also analytic and explicit. The thesis is organized as follows: Chapter (1) presents the state of the art, Chapter (2) the compact modeling of the four devices: doped DG MOSFETs, undoped DG MOSFETs, undoped UTB MOSFETs and undoped SGT; in Chapter (3) we study the fringing capacitances in MuGFETs. Finally Chapter (4) summarizes the work done and the future points that need to be studied.
Due to the limitation of available optimized devices for analysis, numerical simulation was used as the main analysis tool. However, when available, measurements were used to validate our results. The experimental part was realised at the Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la Neuve, Belgium.
For example, in section 2A, in the case of highly-doped DG MOSFETs we could compare our results with experimental data from FinFETs modeled as DG MOSFETs. The main advantage of this work is the analytical and explicit character of the charge and capacitance model that makes it easy to implement in circuit simulators. The model presents almost perfect results for different cases of doping (doped/undoped devices) and for different non classical MOSFET structures (DG MOSFET, UTB MOSFETs and SGT). The variety of the MOSFET structures in which our modeling scheme has been included and the obtained results, demonstrate its absolute validity.
In chapter 3, we investigate the influence of geometrical parameters on the RF performance in MuGFETs. We show the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET). Results highlight the advantage of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced.
The goal of our study and work is the usage of our models in circuit simulators. This part, of implementing and testing our models of these multi gate MOSFET devices in circuit simulators has already begun. The group of Professor Aranda, from the University of Granada has implemented the SGT current model in the circuit simulator Agilent ADS and good results were obtained.
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Trapes, Céline. "Etude expérimentale des phénomènes de dégradation sous différents modes d'injection dans les oxydes ultra-minces (<5nm) pour la microélectronique." Aix-Marseille 1, 2004. http://www.theses.fr/2004AIX11003.
Full textAbstract:
La technologie CMOS (Complementary Metal Oxide Semiconductor) qui représente 3/4 de la production de l'industrie de la microélectronique est confrontée à l'enjeu de la miniaturisation et les transistors MOS ont un oxyde de grille qui atteint aujourd'hui quelques nanomètres. A de telles épaisseurs des problèmes de fiabilité et de performance se posent car le courant de fuite de grille prend des proportions considérables alors que la limite du courant acceptable dans les circuits logiques est de 1A/cm2 en mode de fonctionnement nominal. L'objectif de ce travail est d'étudier la fiabilité des oxydes ultra minces d'épaisseur comprise entre 3. 5 et 1. 2 nm sous différents modes d'injection et de caractériser la dégradation de l'oxyde grâce à des mesures électriques de type courant/tension (IV), de capacité (C-V) ou de pompage de charges (CP). Dans les oxydes d'épaisseur supérieure à 5 nm nous pouvons étudier le SILC (Stress Induced Leakage Current) qui correspond à une augmentation du courant.
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Shelley, Valerie Anderson 1957. "Validity of the Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276801.
Full textAbstract:
The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.
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Towie, Ewan Alexander. "Extended models of Coulomb scattering for the Monte Carlo simulation of nanoscale silicon MOSFETs." Thesis, University of Glasgow, 2010. http://theses.gla.ac.uk/1900/.
Full textAbstract:
The International Technology Roadmap for Semiconductors (ITRS) specifies that MOSFET logic devices are to be scaled to sub-10nm dimensions by the year 2020, with 32nm bulk devices ready for production and double-gate FinFET devices demonstrated down to 5nm channel lengths. Future device generations are expected to have lower channel doping in order to reduce variability in devices due to the discrete nature of the channel dopants. Accompanying the reduced channel doping is a corresponding increase in the screening length, which is even now comparable with the channel length. Under such conditions, Coulomb scattering mechanisms become increasingly complex as the scattering potential interacts with a larger proportion of the device. Ionized impurity scattering within the channel is known to be an important Coulombic scattering mechanism within MOSFETs. Those channel impurities located close to the heavily doped source and drain or both, will induce a polarisation charge within the source and drain. These polarisation charge effects are shown in this work to increase the net screening of the channel impurities, due to the inclusion of remote screening effects, and significantly decrease the scattering rate associated with ionized impurity scattering. Remote screening can potentially reduce the control by ionized channel impurities over channel transport properties, leading to an increased sub-threshold current. A potential model has been obtained that is based on an exact solution of Poisson’s equation for an ionized impurity located close to one or both of these highly doped contact regions. The model shows that remote screening effects are evident within a few channel screening lengths of the highly doped contact regions. The resultant scattering model developed from this potential, which is based on the Born approximation, is implemented within a Monte Carlo simulator and is applied to MOSFET device simulation. The newly developed ionized impurity scattering model, which allows for remote screening, is applied in the simulation of two representative MOSFET devices: the first device being a bulk MOSFET device developed for the 32nm technology generation; the second device is an Ultra-Thin-Body Double Gate (UTB DG) MOSFET developed for the forthcoming 22nm technology generation. Thorough investigative simulations show that for both the bulk MOSFET and the UTB DG MOSFET, that remote screening of channel impurities in these devices is not a controlling effect. These results prove that the current model for ionized impurity scattering employed in Monte Carlo simulations is sufficient to model devices scaled to at least the 22nm technology node, predicted to be in production in the year 2012.
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Djomehri, Ihsan Jahed 1976. "Comprehensive inverse modeling for the study of carrier transport models in sub-50nm MOSFETs." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8011.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 123-129).
Direct quantitative 2-D characterization of sub-50 nm MOSFETs continues to be elusive. This research develops a comprehensive indirect inverse modeling technique for extracting 2-D device topology using combined log(I)-V and C-V data. An optimization loop minimizes the error between a broad range of simulated and measured electrical characteristics by adjusting parameterized profiles. The extracted profiles are reliable in that they exhibit decreased RMS error as the doping parameterization becomes increasingly comprehensive of doping features. The inverse modeling methodology pieces together complementary MOSFET data sets such as capacitance of the gate stack, 1-D doping analysis, subthreshold I-V which is a strong function of 2-D doping, and C-V data which is especially sensitive to the source/drain. Combining the data sets enhances the extracted profiles. Such profiles serve as a basis for tuning diffusion coefficients in order to realistically calibrate modern process simulators.
(cont.) The important application of this technique is in the calibration of carrier transport models. With an accurate device topology, the transport model parameters can be adjusted to predict the onstate behavior. Utilizing a mobility model that conforms to the experimental effective field dependence and including a correction for parasitic resistance, the transport model for an advanced NMOS generation at various gate lengths and voltages is calibrated. Employing the Energy Balance model yields an energy relaxation value valid over all devices examined in this work. Furthermore, what has been learned from profile and transport calibration is used in investigating optimal paths for sub-20 nm MOSFET scaling. In a study of candidate architectures such as double-gate, single-gate, and bulk-Si, metrics for the power versus performance trade-off were developed. To conclude, the best trade-off was observed by scaling as a function of gate length with a single near-mid-gap workfunction.
by Ihsan J. Djomehri.
Ph.D.
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LI, JIA-RUI, and 李家瑞. "MOSFET model and optimal parameter extraction." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/97291880015677111862.
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Chen, Yung-Chih, and 陳泳志. "RF Model Establishment of sub-micron MOSFET." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65771245485120985285.
Full textAbstract:
碩士長庚大學
半導體產業研發碩士專班
95
ABSTRACT A high-freqency model for MOSFET by Nanya Technology Corporation is presented which achieves a good agreement with the device DC and microwave performance. This model is based on the BSIM3v3 model by U.C. Berekeley, and extracted extrinsic parameters and lossy substrate parameters. The measured and model-predicted device DC I-V curves, S-parameters, and power performance have been compared. Good correspondences between measurement and simulation DC、microwave and power performance, which confirm the validity of this model. In chapter 4, a low noise amplifier was demonstrated by MOSFET of Nanya Technology Corporation as the core of the design, targeting a center frequency of 5.2 GHz apply to WLAN 802.11a system.
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Sharma, Sameer. "First order quasi static mosfet channel capacitance model." 2008. http://digital.library.okstate.edu/etd/umi-okstate-2669.pdf.
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Liu, Shou-En, and 劉守恩. "Threshold Voltage Model of Asymmetry Double Gate MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23002033707927316207.
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Ting, Chien-yi, and 丁健益. "Comparison between BJT model and MOSFET model with linear circuit elements." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/11935380668995021910.
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碩士國立中央大學
電機工程研究所碩士在職專班
99
In this thesis, to compare the bipolar-junction transistor (BJT) and metal-oxide-semiconductor field-effect transistor (MOSFET) model, we develop nonlinear circuit simulations based on the linear components. The basic linear components include voltage source, resistor, capacitor, and voltage-control current source (VCCS), etc. In the program, we will use explicit representation structure to display the implicit parameters of the nonlinear elements and linear components in the main program. We use the basic linear VCCS with the current and transconductance for Newton-Raphson iteration. The difficulty of MOSFET modeling by linear VCCS will be compared to BJT modeling. We successfully verify the program by the applied circuit of MOSFETs.
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LI, ZHENG-SHENG, and 李正昇. "The hot electron effect model of MOSFET for circuit simulation." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/48339805017585677463.
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Hsu, Hui-chuan, and 徐惠娟. "Analytical drain current model for submicrometer and deep submicrometer MOSFET." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/29603395845045824040.
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Hsieh, Wen Yi, and 謝文義. "A 2-D Analytic Model for Short-Channel SOI MOSFET." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/07709657787547765406.
Full textAbstract:
碩士國立交通大學
電子工程系
89
Recently, the SOI structure has drawn much attention for its advantages over bulk device such as perfect device isolation, elimination of latch-up path and improved radiation hardness. Moreover, a number of companies have announced that they will use the Silicon-on-Insulator (SOI) technology in commercial VLSI production. Therefore, it is expected that the SOI technology will become a mainstream technology. In this thesis, the basic physical characteristics and advantages of SOI MOSFET will be analyzed and discussed. This thesis focuses on the analytic model of the short-channel fully-depleted SOI MOSFET. Therefore, the analytic threshold voltage model and I-V model are derived for short-channel fully-depleted SOI MOSFET. With the help of a 2D numerical simulator (Medici), the accuracy of the analytic models of short-channel fully-depleted SOI MOSFET have been confirmed. Finally, some future researches deserved further efforts are summarized
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Lin, Chia-Long, and 林佳龍. "Implementation and application of a double-gate MOSFET compact model." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/00702736561428286245.
Full textAbstract:
碩士國立宜蘭大學
電子工程學系碩士班
99
Computer-aided design (CAD) is useful for early development of integrate circuits (ICs). SPICE is commonly used in circuit design. In circuit simulation, an analytical and physics-based compact model plays an important role in predicting performance and also issues. Nowadays, there are still no standard multi-gate MOSFETs compact models available in commercial tools. In this paper, we successfully developed a compact model which is focused on undoped symmetric double-gate (DG) MOSFETs using Verilog-A. Starting from Poisson’s equation solved for the undoped channel, surface and center potentials are then calculated by Newton iteration. An analytical drain current expression is derived from Pao-Sah’s double integral method. The model provides flexible parameters and is completely compatible with SPICE-like simulators.
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Tsai, Chung-Hsien, and 蔡鐘賢. "A MOSFET Saturation Current Mismatch Model Based on Backscattering Theory." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/13731700716311499339.
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碩士國立交通大學
電子工程系所
94
This thesis investigates the current mismatch in above-threshold regions and derives a physical mismatch model based on backscattering theory. We have extensively characterized measured MOSFETs in above-threshold regions with different gate widths and lengths to determine the current mismatch. We have observed that the current mismatch decreases with increasing gate voltage. We have also derived a backscattering based mismatch model with three key parameters, drain-induce-barrier-lowering (DIBL), quasi-equilibrium threshold voltage Vtho, and backscattering coefficient rC. We can calculate the current mismatch in above-threshold regions by using the new mismatch model.
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蘇裕勝. "The GIDL model for Ultra-Thin Gate Oxide Low Voltage MOSFET." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/47277744142596178334.
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碩士國立清華大學
電子工程研究所
90
As the channel length and the gate oxide thickness are scaled down, the off-state MOSFETs’ leakage current becomes more severe. The off-state leakage components are the sub-threshold current, surface/bulk thermal generation of carriers in the junction space-charge region, gate direct tunneling current etc. Furthermore, Many researchers have attributed the leakage current to the band-to-band tunneling occurring in the overlay region at negative gate bias and named the phenomenon “gate-induced drain leakage current (GIDL)”.According to the SIA roadmap, CMOS with gate length of 50-70 nm needs an oxide thickness of around 1.5-2.0 nm, which corresponds to 2-3 layers of atoms. With such a thin gate oxide, the gate direct tunneling current and the gate induced drain leakage current would become more apparent at low voltage due to the high electric field at low voltage. The exact oxide thickness and doping profiles in the gate-to-drain overlay region play important roles in the GIDL current. And this leakage current is very sensitive to the oxide thickness, drain concentration, and lateral drain doping gradient. In the gate-to-drain overlay region, since the gate work function and high drain concentration would serve to enhance the field strength. So, recently complete suppression of the GIDL current has been demonstrated for low-concentration LDD devices by suppressing the electric field. At somewhat higher field, the band-to-band tunneling in the gate-overlapped deep-depletion drain region has been proven to be the generation mechanism for Gate-Induced Drain Leakage (GIDL). In this thesis, we investigate GIDL models with n-MOSFETs oxide thickness of 20 Å, 26 Å, and 50 Å, respectively. We show that the published GIDL models are not well fitting to our measured data. Since the surface electric field in the gate-to-drain overlay region play important roles in the GIDL current. In order to observe the surface electric field, we generate tsuprem4 structures whose aspects are similar to the measured samples. Then, devices characteristic are simulated with Medici to observe the surface electric field in the gate-overlapped-drain region. Moreover, we derive a new GIDL model and fitting well with measured data.
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Tang, Chien-Fong, and 唐千峰. "MOSFET Threshold Voltage Mismatch Model and Its Impact on Circuit Yield." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/40913049263705529791.
Full textAbstract:
碩士國立交通大學
電子工程系
88
Nowadays, many of the high-technology electronics industries are developing advanced communication and multimedia products. The requirements of these products, such as internet peripherals, mobile phone, and digital camera, become more and more. And certain circuits in these products act as the bridge between the real world and the digital processing units. The representation circuits like digital to analog converter (DAC) need that devices, such as transistors, resistors, capacitors, are best the same in parameters when they are being designed. However, there are not two things exactly the same. So, the research of the mismatch model becomes more and more important. Once we get the statistical properties of the mismatch, we can use it to compute the yield of some kind of analog/digital circuits such as to see if the design is worth of being implemented. Besides, we can also use it to improve the design rule of circuits in order to make the least effect of mismatch on circuits. This paper contains two major parts. The first part is about the development of mismatch model. Also discussed is the reasonable range of the parameters in the model equation. In the second part, we try to use the standard deviation of the threshold voltage to compute the yield in a precise DAC, and address the theory behind as well as its corection.
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Hsu, Shu-Yen, and 徐書彥. "A Study of MOSFET Model - BSIM4 Modeling Technology and Characterization Measurement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/10688052341979344820.
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碩士逢甲大學
電子工程所
93
This thesis focuses on the parameter extraction and optimization procedure of MOSFET BSIM4 compact model for DC、CV and RF application. The model operation frequency verification had also done under 20GHz or upward. The devices fabricated by 0.18um process technology. BSIM3v3 MOSFET model is the industry standard model which is used under MOSFET circuit extensively. But, the BSIM3v3 model should lump parasitic components and modify the core model equation for precise modeling process under advance fabricated technology. Since the BSIM4 model is the using trend of the circuit designer. So, the first, we would entire study of the BSIM4 core model and lead to a optimization modeling procedure with physical means. Beside, we would emphasis on measurement method for CV and RF. Consider the probes interfere each other on CV and use the De-embedding technology on RF. This is in order to get the precise device characterization. At last, we would take the modeling procedure from verification under 0.18um device.
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Liao, Wen-Tui, and 廖文堆. "The Study of Drain Current Model in Deep Submicron MOSFET''s." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/68332498682964597181.
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碩士國立雲林科技大學
電子與資訊工程研究所碩士班
89
Pocket implantation structure can improve effectively the Vth roll-off, DIBL and punch through, but it will induce IDSAT degradation and hot carriers effect will be series then the reliability of the device will be degraded. Thus, how to tradeoff between the improvement of short-channel immunity and the reliability of the device is very important. In this thesis, we have developed a physics-based model to predict the effect of pocket implant on device characteristics. We have also derived a drain current model for linear and saturated regions. The validity of this model has been confirmed with experimental data of NMOS devices from 0.24um technology. The capability to account for different pocket doping levels is also confirmed by Medici two-dimensional numerical simulation. In this thesis, we also study the relation between pocket dosage and pocket concentration in the physics-based model. We find out that when the pocket dosage increases twofold, the pocket concentration in the physics-based model will increases 1.4 fold. We also find out that when the pocket dosage equals to 1.25×1012cm-2, the Reverse Short Channel Effect and IDSAT degradation are not serious, and short channel immunity is improved.
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HWANG, CHING FONG, and 黃清風. "The High Frequency Model of Power MOSFET - Verification and Parameter Analysis." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/23959029551456306645.
Full textAbstract:
碩士國立清華大學
電機工程研究所
84
High-frequency high-power devices have been valued recently as the demand of communication and power electronics increased. The main streams of material and structure are III-V family (eg GaAs) and MESFET. Many small-signal models and analysis methods have been presented and well-developed. However, as the great process in IC technology, the channel length of a device has been scaled down to submicron range. The frequency of operation of silicon MOSFET is competitive with that of GaAs MESFET. Moreover, the MOS technology has the advantages of low-cost and easy-fabri- cation. In this paper we present a high-frequency model suited for MOSFET and establish procedures for extracting and analyzing parameters which is useful as guidelines of research and for de- signing power MOS devices in the future. In Chapter two, we compare various small-signal models for MOSFET devices which are valid up to different upper frequency limits. We concluded that the Non-Quasi-Static (NQS) model which considers "transmission-line effects" is appropriate for high frequency operations. A simplified high-frequency model based on NQS analysis is presented, which is valid for three- terminal de- vices. In the next chapter, the design of different layouts of power devices is discussed. A mesh- structured transistor with benefits of high-packing density and minimum parasitic capaci- tance is preferable. Besides, we will introduce a method of ex- tracting parameters including intrinsic and extrinsic parts of a transistor without designing dummy devices. The d.c. character- istics and high frequency performances of designed MOSFET samples will be characterized in Chapter four. The method of extracting parameters would be modified to get high degree of precision. Concluding remarks and recommendations are given in the last chapter.