Log in

Relevant bibliographies by topics / MOSFET model / Journal articles

To see the other types of publications on this topic, follow the link: MOSFET model.

Journal articles on the topic 'MOSFET model'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'MOSFET model.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

LIU, WEIDONG, and CHENMING HU. "BSIM3V3 MOSFET MODEL." International Journal of High Speed Electronics and Systems 09, no. 03 (September 1998): 671–701. http://dx.doi.org/10.1142/s0129156498000294.

Full text

Abstract:

The BSIM3v3 compact MOSFET model is reviewed. It is a physics-based model that is accurate, smooth, continuous, scalable, predictive and computationally robust over different regions of operation and a wide geometry range. BSIM3v3 considers all major physical effects in deep submicron MOSFETs, making it a good base for future sub-0.1m device models and for statistical circuit designs. A key feature of the model lies in its thorough, accurate and functional mathematical representation of MOS device physics, which has made BSIM3v3 selected by an international consortium of semiconductor companies as the first industry standard MOSFET model.

APA, Harvard, Vancouver, ISO, and other styles

2

Ejury, Jens. "Advanced Thermal Simulation Model for Power MOSFETs." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000598–603. http://dx.doi.org/10.4071/isom-2013-wa64.

Full text

Abstract:

Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.

APA, Harvard, Vancouver, ISO, and other styles

3

Wu, Li-Feng, Yong Guan, Xiao-Juan Li, and Jie Ma. "Anomaly Detection and Degradation Prediction of MOSFET." Mathematical Problems in Engineering 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/573980.

Full text

Abstract:

The MOSFET is an important power electronic transistor widely used in electrical systems. Its reliability has an effect on the performance of systems. In this paper, the failure models and mechanisms of MOSFETs are briefly analyzed. The on-resistanceRonis the key failure precursor parameter representing the degree of degradation. Based on the experimental data, a nonlinear dual-exponential degradation model for MOSFETs is obtained. Then, we present an approach for MOSFET degradation state prediction using a strong tract filter based on the obtained degradation model. Lastly, the proposed algorithm is shown to perform effectively on experimental data. Thus, it can provide early warning and enhance the reliability of electrical systems.

APA, Harvard, Vancouver, ISO, and other styles

4

Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

Full text

Abstract:

Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

APA, Harvard, Vancouver, ISO, and other styles

5

Petrosyants, Konstantin O., Igor A. Kharitonov, and Lev M. Sambursky. "Hardware-Software Subsystem for MOSFETs Characteristic Measurement and Parameter Extraction with Account for Radiation Effects." Advanced Materials Research 718-720 (July 2013): 750–55. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.750.

Full text

Abstract:

Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel approach is used to account for radiation effects in MOSFET modeling. Particularities of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are emphasized. Application of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.

APA, Harvard, Vancouver, ISO, and other styles

6

Hebali, Mourad, Menaouer Bennaoum, Mohammed Berka, Abdelkader Baghdad Bey, Mohammed Benzohra, Djilali Chalabi, and Abdelkader Saidane. "A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model." Journal of Electrical Engineering 70, no. 2 (April 1, 2019): 145–51. http://dx.doi.org/10.2478/jee-2019-0021.

Full text

Abstract:

Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

APA, Harvard, Vancouver, ISO, and other styles

7

Potbhare, Siddharth, Neil Goldsman, Gary Pennington, Aivars J. Lelis, and J. M. McGarrity. "Time Dependent Trapping and Generation-Recombination of Interface Charges: Modeling and Characterization for 4H-SiC MOSFETs." Materials Science Forum 556-557 (September 2007): 847–50. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.847.

Full text

Abstract:

SiC MOSFETs have very large interface trap densities which degrade device performance. The effect of traps on inversion layer mobility and inversion charge concentration has been studied, and mobility models suitable for inclusion in Drift-Diffusion simulators have been developed for steady state operation of SiC MOSFET devices. Here, we attempt to model the transient behavior of SiC MOSFETs, and at the same time, extract the time constants for the filling and emptying of interface traps. As compared to the inversion layer, interface traps in SiC MOSFETs are slow in reacting to change in gate bias. So, at the positive edge of a gate pulse, we see a large current in the MOSFET, which then decays slowly to the steady state value as the interface traps fill up. We have developed a generation/recombination model for minority carriers in a SiC MOSFET based on the Shockley-Read-Hall recombination model for electrons and holes. In our model, the generation/recombination takes place between minority carriers in the inversion layer, and the traps at the SiC-SiO2 interface. Comparing our simulated current vs. time curves to experiment, we have been able to extract time constants for the filling and emptying of traps at the SiC-SiO2 interface.

APA, Harvard, Vancouver, ISO, and other styles

8

Chaudhry, Amit, and Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures." Serbian Journal of Electrical Engineering 7, no. 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.

Full text

Abstract:

In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

APA, Harvard, Vancouver, ISO, and other styles

9

Manzoor, Sadia, Nissar Mohammad Karim, and Norhayati Soin. "Analyzing p-MOSFET Lifetime by Employing R-D Model & MOS Device Theory." Applied Mechanics and Materials 229-231 (November 2012): 1626–29. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1626.

Full text

Abstract:

For CMOS circuitry the models which are able to determine the reliability of the components and the methods which lead them to the degradation of the reliability issues are very important. Negative bias temperature instability (NBTI) is a critical issue for the p-MOSFETs. It causes, shifting of drive current and threshold voltage of P-MOSFET. Till date many models capable of simulating various features of the NBTI degradation have been proposed by researchers. Reaction Diffusion (R-D) model is notable among them. This paper demonstrates a new approach which analyzes the combination of R-D model and transistor theories. To do so, we analytically correlated R-D model and device theory. The analysis shows the lifetime estimation for p-MOSFET device with respect to drain current.

APA, Harvard, Vancouver, ISO, and other styles

10

zaman, Haider, Xiancheng Zheng, Husan Ali, Shahbaz Khan, and Xiaohua Wu. "Reliability Modeling of SiC-Based Multiphase Synchronous Boost Converter." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950033. http://dx.doi.org/10.1142/s0218126619500336.

Full text

Abstract:

Despite attractive thermal and electrical characteristics, wide band-gap semiconductor devices such as SiC MOSFET have struggled to penetrate in aircraft applications because of reliability issues in earlier releases. The second and third generation SiC MOSFETs have achieved improved reliability using high quality oxides and innovative fabrication process. This paper presents a failure rate model for SiC MOSFET based on the accelerated test data at a given operating condition. The proposed model enables the system level reliability analysis of second generation SiC MOSFET-based converters. The reliability of SiC two-phase synchronous boost converter has been evaluated at two different operating conditions: 10 and 16 A load condition. To predict the life time of the converter even after a chain of component failures, Markov’s reliability model of the converter is developed. The state transition probabilities and mean time to failure (MTTF) of SiC converter are compared against its Si counterpart which shows that second generation SiC MOSFETs are for aircraft applications with high reliability.

APA, Harvard, Vancouver, ISO, and other styles

11

Ahn, Tae Jun, and Yun Seop Yu. "Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs." Micromachines 11, no. 10 (September 24, 2020): 887. http://dx.doi.org/10.3390/mi11100887.

Full text

Abstract:

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

APA, Harvard, Vancouver, ISO, and other styles

12

Shur, M., T. A. Fjeldly, T. Ytterdal, and K. Lee. "Unified MOSFET model." Solid-State Electronics 35, no. 12 (December 1992): 1795–802. http://dx.doi.org/10.1016/0038-1101(92)90263-c.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Lukić, P. M., R. M. Ramović, and Rajko M. Šašić. "Modeling and Investigation of SiGe Based MOSFET Structure Transport Characteristics." Materials Science Forum 555 (September 2007): 101–6. http://dx.doi.org/10.4028/www.scientific.net/msf.555.101.

Full text

Abstract:

The focus of this paper was the investigation and modeling of transport characteristics in a strained SiGe based MOSFET structure, which might be of fundamental importance for the understanding of its operating characteristics. In the investigation, carrier mobility dependence on the lateral and vertical electric field is especially considered. Carrier mobility models for long channel as well as short channel SiGe MOSFETs are also presented. Average effective electric field model is proposed taking into account impact of high electric field effects on the effective channel length. In the final effective carrier mobility model, for the short channel SiGe MOSFETs, serial drain to source resistance is included. At the same time, proposed models are relatively simple. By using the presented model, simulations were performed.

APA, Harvard, Vancouver, ISO, and other styles

14

Hino, Shiro, Naruhisa Miura, Akihiko Furukawa, Shoyu Watanabe, Yukiyasu Nakao, Shuhei Nakata, Masayuki Imaizumi, Hiroaki Sumitani, and Tatsuo Oomori. "SiC-MOSFET Structure Enabling Fast Turn-On and -Off Switching." Materials Science Forum 717-720 (May 2012): 1097–100. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1097.

Full text

Abstract:

High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.

APA, Harvard, Vancouver, ISO, and other styles

15

Müting, Johanna, Bhagyalakshmi Kakarla, and Ulrike Grossner. "Comprehensive and Detailed Study on the Modeling of Commercial SiC Power MOSFET Devices Using TCAD." Materials Science Forum 897 (May 2017): 553–56. http://dx.doi.org/10.4028/www.scientific.net/msf.897.553.

Full text

Abstract:

The main scattering mechanisms reducing the channel mobility and thus the typical performance of a SiC power MOSFET are reviewed. It is demonstrated that the Poisson equation within the drift-diffusion model is able to account for the effects of ionized impurity scattering. Furthermore, a correlation between the size of macro-or nanosteps at the SiC/SiO2 interface and the corresponding fitting parameter within the Lombardi surface roughness model is established. By qualitatively reproducing the typical performance of a commercial SiC power MOSFET a baseline for the TCAD modeling of power MOSFETs is provided.

APA, Harvard, Vancouver, ISO, and other styles

16

Abdelmalek, N., F. Djeffal, M. Meguellati, and T. Bendib. "Numerical Analysis of Nanoscale Junctionless MOSFET Including Effects of Hot-Carrier Induced Interface Charges." Advanced Materials Research 856 (December 2013): 137–41. http://dx.doi.org/10.4028/www.scientific.net/amr.856.137.

Full text

Abstract:

In this work, we aim at highlighting the immunity of the junctionless Gate All Around (JLGAA) MOSFET against the induced interface tarps degradation at nanoscale level. In this context, a numerical investigation has been proposed to study the subthreshold behavior of the (JLGAA) MOSFET for ultra-low power applications. Based on 2-D numerical investigation, a small-signal parameters model for nanoscale JLGAA MOSFETs, including the hot-carrier induced interface charge effects, is developed. The numerical analysis has been used to simulate the transconductance and output-conductance in subthreshold region and to compare the performance of the investigated design and conventional GAA MOSFET, where the hot-carrier effects are included. High reliability, low fabrication cost and integration ability make JLGAA MOSFET promising candidate to improve the device reliability for the ultra-low power applications.

APA, Harvard, Vancouver, ISO, and other styles

17

Jung, Hakkee. "SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1288. http://dx.doi.org/10.11591/ijece.v10i2.pp1288-1295.

Full text

Abstract:

We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.

APA, Harvard, Vancouver, ISO, and other styles

18

van Zeghbroeck, Bart, and Hamid Fardi. "Comparison of 3C-SiC and 4H-SiC Power MOSFETs." Materials Science Forum 924 (June 2018): 774–77. http://dx.doi.org/10.4028/www.scientific.net/msf.924.774.

Full text

Abstract:

A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.

APA, Harvard, Vancouver, ISO, and other styles

19

Lee, Min Su, and Hee Chul Lee. "Aspect Ratio Model for Radiation-Tolerant Dummy Gate-Assisted n-MOSFET Layout." International Scholarly Research Notices 2014 (November 18, 2014): 1–6. http://dx.doi.org/10.1155/2014/145759.

Full text

Abstract:

In order to acquire radiation-tolerant characteristics in integrated circuits, a dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was adopted. The DGA n-MOSFET has a different channel shape compared with the standard n-MOSFET. The standard n-MOSFET has a rectangular channel shape, whereas the DGA n-MOSFET has an extended rectangular shape at the edge of the source and drain, which affects its aspect ratio. In order to increase its practical use, a new aspect ratio model is proposed for the DGA n-MOSFET and this model is evaluated through three-dimensional simulations and measurements of the fabricated devices. The proposed aspect ratio model for the DGA n-MOSFET exhibits good agreement with the simulation and measurement results.

APA, Harvard, Vancouver, ISO, and other styles

20

IÑIGUEZ, BENJAMIN, ROMAIN RITZENTHALER, and FRANÇOIS LIME. "COMPACT MODELING OF DOUBLE AND TRI-GATE MOSFETs." International Journal of High Speed Electronics and Systems 22, no. 01 (November 2013): 1350004. http://dx.doi.org/10.1142/s0129156413500043.

Full text

Abstract:

This chapter presents some insights into the modeling of different Multi-Gate SOI MOSFET structures, and in particular Double-Gate MOSFETs (DG MOSFETs) and Tri-Gate MOSFETs (TGFETs). For long-channel case an electrostatic model can be developed from the solution of the 1D Poisson's equation (in the case of DG MOSFETs) and the 2D Poisson's equation in the section perpendicular to the channel (in the case of TGFETs). Allowing it to be incorporated in quasi-2D compact models. For short-channel devices a model can be derived from a 2D (in the case of DG MOSFETs) or a 3D (in the case of TGFETs) electrostatic analysis. The models were successfully compared with 2D and 3D TCAD simulations and, in some cases, experimental measurements. Short-channel effects, such as subthrehold slope degradation, threshold voltage roll-off and DIBL were accurately reproduced.

APA, Harvard, Vancouver, ISO, and other styles

21

Islam, Md Rabiul, Md Kamrul Hasan, Md Abdul Mannan, M. Tanseer Ali, and Md Rokib Hasan. "Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor." AIUB Journal of Science and Engineering (AJSE) 18, no. 2 (August 31, 2019): 73–80. http://dx.doi.org/10.53799/ajse.v18i2.43.

Full text

Abstract:

We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

APA, Harvard, Vancouver, ISO, and other styles

22

Rao, R. Ramakrishna, Kevin Matocha, and Vinayak Tilak. "Quasi-Charge-Sheet Model for Inversion Layer Mobility in 4H-SiC MOSFETs." Materials Science Forum 615-617 (March 2009): 797–800. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.797.

Full text

Abstract:

The mobility of electrons in the inversion layer of 4H-Silicon Carbide (SiC) MOSFETs is lower than the ideal value due to the various scattering mechanisms that takes place at the surface. These scattering mechanisms are strong function of both the interface-trapped charge density and inversion-layer electron density. In this work, we develop a quasi-charge-sheet model to quantify coulomb scattering due to interface trapped-charge in SiC MOSFET inversion layers and calculate the inversion layer electron mobility.

APA, Harvard, Vancouver, ISO, and other styles

23

Graham, M. G., J. J. Paulos, and D. W. Nychka. "Template-based MOSFET device model." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 8 (1995): 924–33. http://dx.doi.org/10.1109/43.402493.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Suzuki, K. "Short channel epi-MOSFET model." IEEE Transactions on Electron Devices 47, no. 12 (2000): 2372–78. http://dx.doi.org/10.1109/16.887024.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Farzana, Esmat, Shuvro Chowdhury, Rizvi Ahmed, and M. Ziaur Rahman Khan. "Performance Analysis of Nanoscale Double Gate MOSFETs with High-κ Gate Stack." Applied Mechanics and Materials 110-116 (October 2011): 1892–99. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.1892.

Full text

Abstract:

The performance and characteristics of Double Gate MOSFET with high dielectric constant (high-κ) gate stack have been analyzed and compared with those of conventional pure SiO2gate MOSFET. Quantum Ballistic Transport Model has been used to demonstrate the performance of the device in terms of threshold voltage, drain current in both low and high drain voltage regions and subthreshold swing. The effect of temperature on the threshold voltage and subthreshold characteristics has also been observed. This work reveals that improved performance of this structure can be achieved by scaling the gate length and illustrates its superiority over SiO2gate MOSFETs in achieving long-term ITRS goals.

APA, Harvard, Vancouver, ISO, and other styles

26

Singh, Ranbir. "Improvement of Mosfet Characteristics." Active and Passive Electronic Components 14, no. 2 (1990): 53–65. http://dx.doi.org/10.1155/1990/78629.

Full text

Abstract:

By inclusion of a semi-dielectric layer, a novel MOSFET Structure, the T-MOSFET, and its integrated circuit version are presented. Both for the enhancement mode and the depletion mode, equivalent circuit models are developed. Also, the high frequency behaviour is explained by a model and the behaviour of a T-MOSFET under different conditions is given.

APA, Harvard, Vancouver, ISO, and other styles

27

El Abbassi, A., Y. Amhouche, K. Raïs, and R. Rmaily. "A Physical Model for MOSFET Drain Current in Non-ohmic Regime Using Ohmic Regime Operation." Active and Passive Electronic Components 24, no. 1 (2001): 23–29. http://dx.doi.org/10.1155/2001/34065.

Full text

Abstract:

In order to characterise the velocity saturation phenomena in short channel MOSFET's, a simple method is proposed in this work. It is based on the comparison between transistor behaviour in ohmic and saturation regime respectively. Therefore, the MOSFET characteristicId0(Vd). avoiding velocity saturation phenomena, can be obtained from ohmic characteristicId(Vg)and compared with the experimental characteristicId(Vd).

APA, Harvard, Vancouver, ISO, and other styles

28

CHENG, YUHUA. "MOSFET MODELING FOR RF IC DESIGN." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1007–84. http://dx.doi.org/10.1142/s0129156401001052.

Full text

Abstract:

High frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. Modeling of the intrinsic device and the extrinsic components is disussed by accounting for the important physical effects at both DC and HF. Based on the Y-parameter analysis of the equivalent circuit model, procedures of the HF model parameter extraction are also developed. With the discussed approaches, a sub-circuit RF model incorporating the modeling of parasitics is presented. This model is compared with the measured data for both y parameter and fr characteristics. Good model accuracy is achieved against the measurements for a 0.25μm RF CMOS technology. The non-quasi-static (NQS) modeling issue has also been discussed by using the BSIM3v3 based RF model to predict the HF characteristics of devices with serious NQS effects. Further, noise modeling issues are discussed by analyzing the theoretical and experimental results in both the flicker noise and thermal noise modeling. Modeling efforts to in corporate new physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A detailed analysis of the HF noise parameters has been conducted to establish the relationship between the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical calcultion of the noise parameters has also been discussed to understand the noise characteristics with/without some parasitic components such as gate and substrate resistances as well as the influence of the induced gate noise. The HF noise predictivities of several HF noise models are also examined with the measured data. The results show that the BSIM3v3 based RF model can predict the channel thermal noise better than the other models.

APA, Harvard, Vancouver, ISO, and other styles

29

JE, MINKYU, ICKJIN KWON, HYUNGCHEOL SHIN, and KWYRO LEE. "MOSFET MODELING AND PARAMETER EXTRACTION FOR RF IC'S." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 953–1006. http://dx.doi.org/10.1142/s0129156401001040.

Full text

Abstract:

After reviewing the basic concept and general strategies, we have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation is also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal I-V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET is very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach is examined with various examples.

APA, Harvard, Vancouver, ISO, and other styles

30

ABOU-ELNOUR, ALI, OSSAMA ABO-ELNOR, HAMDY ABDELHAMEED, and ADEL EL-HENAWY. "MODELING OF NOISE BEHAVIOR OF GRADED BAND GAP CHANNEL MOSFET AT GHz FREQUENCIES." Fluctuation and Noise Letters 07, no. 04 (December 2007): L507—L517. http://dx.doi.org/10.1142/s0219477507004185.

Full text

Abstract:

A novel graded band gap channel Si - SiGe MOSFET structure has been suggested and its characteristics have been investigated. The investigations indicated that the suggested structure reduces the short-channel effects, increases the cut-off frequency, and hence makes its usage at high frequency and Low noise applications possible. To show the superior performance of the suggested structure at GHz frequencies, and as an example, the noise behavior of the structure is determined. First the device noise model parameters are calculated from D.C. and A.C. characteristics. The extracted noise model parameters are then used to determine the minimum noise figure at GHz frequencies. The effects of the different device parameters on the noise performance are determined. Finally, the results are compared with those of conventional MOSFET structure to show the superior performance of graded band gap Si - SiGe MOSFETs at high frequency ranges.

APA, Harvard, Vancouver, ISO, and other styles

31

Vimala, Palanichamy, and N. R. Nithin Kumar. "Explicit Quantum Drain Current Model for Symmetric Double Gate MOSFETs." Journal of Nano Research 61 (February 2020): 88–96. http://dx.doi.org/10.4028/www.scientific.net/jnanor.61.88.

Full text

Abstract:

In this article, an analytical model for Double gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) is developed including Quantum effects. The Schrodinger–Poisson’s equation is used to develop the analytical Quantum model using Variational method. A mathematical expression for inversion charge density is obtained and the model was developed with quantum effects by means of oxide capacitance for different channel thickness and gate oxide thickness. Based on inversion charge density model the compact model is developed for transfer characteristics, transconductance and C-V curves of DG MOSFETs. The results of the model are compared to the simulated results. The comparison shows the accuracy of the proposed model.

APA, Harvard, Vancouver, ISO, and other styles

32

Xie, Li Jun, Jin Yuan Li, and Kun Shan Yu. "Study on Loss Calculation for Inverter Based on 1200V SiC MOSFET." Applied Mechanics and Materials 672-674 (October 2014): 906–13. http://dx.doi.org/10.4028/www.scientific.net/amm.672-674.906.

Full text

Abstract:

SiC MOSFETs are expected as one of next generation power devices for their superior performances compared with conventional Si power devices and have become one of the new promising substitude to Si devices. The characteristics of 1200V SiC MOSFET are presented first and the power losses analysis model of SiC devices are given. As losses of power devices are essential parameters in converter design, the power dissipation of SiC MOSFET in SPWM inverter are calculated. In this paper, whether a free-wheeling-diode necessary is illustrated from the point of power dissipation and choice is made based on the power loss. According to the analysis result, the inverter without SBD shows less power losses, which can reduce the cost and volume of inverter.

APA, Harvard, Vancouver, ISO, and other styles

33

Fossum, J. G. "A model too hot to handle? [MOSFET model]." IEEE Circuits and Devices Magazine 18, no. 3 (May 2002): 26–31. http://dx.doi.org/10.1109/mcd.2002.1005646.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Merad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.

Full text

Abstract:

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

APA, Harvard, Vancouver, ISO, and other styles

35

Aoki, Hitoshi, and Haruo Kobayashi. "A Typical MOSFET Modeling Procedure for RF Analog Circuit Design." Key Engineering Materials 698 (July 2016): 87–99. http://dx.doi.org/10.4028/www.scientific.net/kem.698.87.

Full text

Abstract:

This paper presents a theoretical yet practical device targeting method to extract typical model parameters of MOSFET devices on wafer for RF analog integrated circuit design. This method employs skewing algorithms with model parameters of existing typical device which are selected by using inter-lot process electrical test parameters. Although this technique can be applied for both n-channel and p-channel MOSFETs, only n-channel devices could be prepared for our experiments in this research. To demonstrate the plausibility of this method, a cascode amplifier is designed to simulate frequency characteristic of S21 with this method.

APA, Harvard, Vancouver, ISO, and other styles

36

MIURA, Mitiko. "Advanced MOSFET Model for Circuit Simulation." IEICE ESS FUNDAMENTALS REVIEW 3, no. 1 (2009): 57–65. http://dx.doi.org/10.1587/essfr.3.1_57.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Kumar, Anil, Navneet Kaushik, Subhasis Haldar, Mridula Gupta, and R. S. Gupta. "Analytical model of 6H-SiC MOSFET." Microelectronic Engineering 65, no. 4 (May 2003): 416–27. http://dx.doi.org/10.1016/s0167-9317(03)00053-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Jang, S.-L., and S.-S. Liu. "An analytical surrounding gate MOSFET model." Solid-State Electronics 42, no. 5 (May 1998): 721–26. http://dx.doi.org/10.1016/s0038-1101(97)00243-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Mitros, J. C. "Empirical model of MOSFET breakdown voltages." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, no. 4 (April 1993): 511–15. http://dx.doi.org/10.1109/43.229734.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Barby, J. A., J. Vlach, and K. Singhal. "Polynomial splines for MOSFET model approximation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 5 (May 1988): 557–66. http://dx.doi.org/10.1109/43.3193.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

BALLAY, N., and B. BAYLAC. "CAD MOSFET MODEL FOR EPROM CELLS." Le Journal de Physique Colloques 49, no. C4 (September 1988): C4–681—C4–685. http://dx.doi.org/10.1051/jphyscol:19884143.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Van der Tol, M. J., and S. G. Chamberlain. "Buried-channel MOSFET model for SPICE." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 8 (1991): 1015–35. http://dx.doi.org/10.1109/43.85739.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Klein, P. "A compact-charge LDD-MOSFET model." IEEE Transactions on Electron Devices 44, no. 9 (1997): 1483–90. http://dx.doi.org/10.1109/16.622605.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Wright, G. T. "A simple and continuous MOSFET model." IEEE Transactions on Electron Devices 32, no. 7 (July 1985): 1259–63. http://dx.doi.org/10.1109/t-ed.1985.22109.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Yuancheng Ren, Ming Xu, Jinghai Zhou, and F. C. Lee. "Analytical loss model of power MOSFET." IEEE Transactions on Power Electronics 21, no. 2 (March 2006): 310–19. http://dx.doi.org/10.1109/tpel.2005.869743.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Rho, K. M., K. Lee, M. Shur, and T. A. Fjeldly. "Unified quasi-static MOSFET capacitance model." IEEE Transactions on Electron Devices 40, no. 1 (1993): 131–36. http://dx.doi.org/10.1109/16.249435.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Zhang, Q. Z., and D. K. Schroder. "A new long-channel MOSFET model." Solid-State Electronics 30, no. 8 (August 1987): 859–64. http://dx.doi.org/10.1016/0038-1101(87)90013-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi, and Sima Dimitrijev. "Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE." Electronics 10, no. 2 (January 9, 2021): 130. http://dx.doi.org/10.3390/electronics10020130.

Full text

Abstract:

The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

APA, Harvard, Vancouver, ISO, and other styles

49

Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi, and Sima Dimitrijev. "Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE." Electronics 10, no. 2 (January 9, 2021): 130. http://dx.doi.org/10.3390/electronics10020130.

Full text

Abstract:

The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

APA, Harvard, Vancouver, ISO, and other styles

50

Marani, Roberto, and Anna Gina Perri. "Variation of I–V characteristics due to process parameters as base for modeling the component variability for LDD MOSFET devices." International Journal of Modeling, Simulation, and Scientific Computing 09, no. 02 (March 20, 2018): 1850015. http://dx.doi.org/10.1142/s1793962318500150.

Full text

Abstract:

In this paper, we present the effect of process parameters variations on [Formula: see text]–[Formula: see text] characteristics of LDD MOSFETs through a simulation study, applying also to any submicron device. In particular, we examine the effect of variation of ionic implantation for different channel doping involved in MOSFET production. At last, we examine a linear [Formula: see text]–[Formula: see text] model to simulate more adequately the effects of variation of the process parameters as correction to the base model.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!