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Journal articles on the topic 'MTCMOS'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

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The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less powe

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2

JIAO, HAILONG, and VOLKAN KURSUN. "NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 125–45. http://dx.doi.org/10.1142/s0218126611007116.

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Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the

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3

Ali, Luqman Sufer, and Asmaa Salim Mayoof. "Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed." Tikrit Journal of Engineering Sciences 23, no. 2 (2016): 96–102. http://dx.doi.org/10.25130/tjes.23.2.11.

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This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipatio

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4

Pattanaik, Manisha, Balwinder Raj, Shashikant Sharma, and Anjan Kumar. "Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders." Advanced Materials Research 548 (July 2012): 885–89. http://dx.doi.org/10.4028/www.scientific.net/amr.548.885.

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In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit wi

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5

C, S. Hemanth Kumar, and S. Kariyappa B. "Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique." Indian Journal of Science and Technology 15, no. 23 (2022): 1143–50. https://doi.org/10.17485/IJST/v15i23.1991.

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Abstract <strong>Objective:</strong> To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. <strong>Methods:</strong> The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). <strong>Findings:</strong> The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MT

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6

Siddaiah, Premananda B., and Vallamkonda Ch Dheeraj. "Performance analysis of low-power multi-threshold CMOS-based 10T SRAM cell." Journal of Electrical Engineering 76, no. 3 (2025): 300–306. https://doi.org/10.2478/jee-2025-0030.

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Abstract Static Random-Access Memory (SRAM) used in cache memories faces significant power challenges due to increased leakage power. To minimize the overall power dissipation of memory units, SRAM cells should be designed to consume less power. The design of a low-power SRAM cell is proposed, utilizing the multi-threshold CMOS (MTCMOS) technique. The work builds upon, identifying a gap in the literature related to efficient power management in SRAM cells. The methodology employed in this work involves integrating the MTCMOS technique into the SRAM cells. Power gating is implemented by adding

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7

Tiwari, Nitendra kumar. "Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations." Journal of Futuristic Sciences and Applications 5, no. 2 (2022): 31–37. http://dx.doi.org/10.51976/jfsa.522205.

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MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

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8

Hailong Jiao and V. Kursun. "Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 8 (2010): 2053–65. http://dx.doi.org/10.1109/tcsi.2010.2041505.

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9

Calhoun, B. H., F. A. Honore, and A. P. Chandrakasan. "A leakage reduction methodology for distributed MTCMOS." IEEE Journal of Solid-State Circuits 39, no. 5 (2004): 818–26. http://dx.doi.org/10.1109/jssc.2004.826335.

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10

Douseki, T., S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchiya. "A 0.5-V MTCMOS/SIMOX logic gate." IEEE Journal of Solid-State Circuits 32, no. 10 (1997): 1604–9. http://dx.doi.org/10.1109/4.634672.

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11

Chen, Shi-Hao, Youn-Long Lin, and Mango C. T. Chao. "Power-Up Sequence Control for MTCMOS Designs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 3 (2013): 413–23. http://dx.doi.org/10.1109/tvlsi.2012.2187689.

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12

SHRIVASTAVA, ANUJ KUMAR, and SHYAM AKASHE. "DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY." International Journal of Nanoscience 12, no. 06 (2013): 1350042. http://dx.doi.org/10.1142/s0219581x13500427.

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Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as use

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13

Yuan, Jiyao, and Xiaochuan Xue. "Solution to SRAM static power consumption with MTCMOS." Applied and Computational Engineering 78, no. 1 (2024): 143–52. http://dx.doi.org/10.54254/2755-2721/78/20240434.

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The rapid growth of mobile devices has led to an increasing demand for battery life and energy efficiency in recent years, the reduction of circuit power consumption has become extremely crucial. SRAM has become an indispensable component of modern System-on-Chip (SoC) designs, and reducing its power consumption holds significant importance in minimizing overall chip power consumption. On the other hand, as manufacturing processes advance, static power consumption resulting from leakage currents has gradually emerged as a primary source of power consumption. This paper analyzes the power compo

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14

C. Manoj Kumar, T. Navya, K. Swathi, T. Sunitha, and B. Thabitha. "Simulation and Analysis of Inverting and Non-Inverting Mixed Logic 2 To 4 Decoder Using 32 Nanometer Fin-FET Technology." International Journal of Scientific Research in Science, Engineering and Technology 12, no. 2 (2025): 637–45. https://doi.org/10.32628/ijsrset25122188.

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Because it is difficult to work with low-power devices for higher-ranking applications (such as microprocessors, DSPs, and SRAMs), this project emphasizes the need for applications that use less power yet have better performance. The Decoder's key role in memory and logical circuit design is well knowledge. According to the recommendations made for 32nm technology, I have been studying the specifications of 12T and 14T decoders based on MOS, Fin-FET, and MTCMOS, including latency, power consumption, and the power delay product. The suggested circuit may be improved as required by changing the

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15

You, Heng, Jia Yuan, Weidi Tang, Zenghui Yu, and Shushan Qiao. "A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS." Electronics 9, no. 5 (2020): 802. http://dx.doi.org/10.3390/electronics9050802.

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In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q

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16

Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than con

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17

Tada, Akira, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, and Masahiro Numa. "Charge recycling in MTCMOS circuits with block dividing." IEICE Electronics Express 4, no. 18 (2007): 562–68. http://dx.doi.org/10.1587/elex.4.562.

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18

Anis, M., S. Areibi, and M. Elmasry. "Design and optimization of multithreshold cmos (mtcmos) circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 10 (2003): 1324–42. http://dx.doi.org/10.1109/tcad.2003.818127.

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19

Zhou, Qiang, Xin Zhao, Yici Cai, and Xianlong Hong. "An MTCMOS technology for low-power physical design." Integration 42, no. 3 (2009): 340–45. http://dx.doi.org/10.1016/j.vlsi.2008.09.004.

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20

Gandla, Anusha. "A Low Power SEU Resilient 13T SRAM using MTCMOS." International Journal of Computer Sciences and Engineering 7, no. 4 (2019): 1120–25. http://dx.doi.org/10.26438/ijcse/v7i4.11201125.

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21

Sharroush, Sherif M., and Yasser S. Abdalla. "Optimum sizing of the sleep transistor in MTCMOS technology." AEU - International Journal of Electronics and Communications 138 (August 2021): 153882. http://dx.doi.org/10.1016/j.aeue.2021.153882.

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22

Oza, Amrita, and Poonam Kadam. "Low Power High Speed Multiplier Design based on MTCMOS Technique." Communications on Applied Electronics 5, no. 7 (2016): 18–21. http://dx.doi.org/10.5120/cae2016652318.

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23

Tamilmani, R., K. Rajesh, and N. Santhiyakumari. "Modified Divide by 2/3 Counter Design Using MTCMOS Techniques." i-manager's Journal on Electronics Engineering 4, no. 2 (2014): 22–27. http://dx.doi.org/10.26634/jele.4.2.2622.

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24

Myderrizi, Indrit, та Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology". Journal of Circuits, Systems and Computers 26, № 11 (2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.

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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with

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25

Douseki, Takakuni, Mitsuru Harada, and Toshiaki Tsuchiya. "Ultra-low-voltage MTCMOS/SIMOX technology hardened to temperature variation." Solid-State Electronics 41, no. 4 (1997): 519–25. http://dx.doi.org/10.1016/s0038-1101(96)00222-5.

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26

OHKUBO, N., and K. USAMI. "Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (2006): 3482–90. http://dx.doi.org/10.1093/ietfec/e89-a.12.3482.

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27

Song, Cen, Gang Zhao, and Binghan Wu. "Applications of Low-Power Design in Semiconductor Chips." Journal of Industrial Engineering and Applied Science 2, no. 4 (2024): 54–59. https://doi.org/10.5281/zenodo.12794397.

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As technology continues to evolve, the demand for high-performance yet low-power semiconductor chips has intensified. This paper explores the applications of low-power design in semiconductor chips, examining various methodologies, techniques, and their effectiveness. Through comprehensive analysis and experimental data, we highlight the significance of low-power design in modern electronics, its impact on performance, and future trends. The paper covers multiple low-power design strategies, including dynamic voltage and frequency scaling (DVFS), multi-threshold CMOS (MTCMOS), and power gating

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28

Mirania, Sanjay kumar, and Rajesh Mehra. "Power & Delay Analysis of D Flip Flop Using MTCMOS Technique." International Journal of Engineering Trends and Technology 36, no. 3 (2016): 121–24. http://dx.doi.org/10.14445/22315381/ijett-v36p223.

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29

Nagariya, Tanvi, and Braj Bihari. "A Survey Paper on Implementing MTCMOS Technique in Full Subtractor Circuit." International Journal of Computer Applications 138, no. 5 (2016): 1–4. http://dx.doi.org/10.5120/ijca2016908824.

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30

Sreekanth, Guguloth, Neelapala Sai Sruthi, and Ravindar Nunavath. "Design of Low Power Data Preserving Flip Flop Using MTCMOS Technique." International Journal of Advanced Engineering Research and Science 4, no. 1 (2016): 27–31. http://dx.doi.org/10.22161/ijaers.4.1.5.

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31

LEE, B. H. "Clock-Free MTCMOS Flip-Flops with High Speed and Low Power." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 6 (2005): 1416–24. http://dx.doi.org/10.1093/ietfec/e88-a.6.1416.

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32

Jiao, Hailong, and Volkan Kursun. "Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 5 (2011): 763–73. http://dx.doi.org/10.1109/tvlsi.2009.2039761.

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33

Kumar, C. S. Hemanth, and B. S. Kariyappa. "Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique." Indian Journal of Science and Technology 15, no. 23 (2022): 1143–50. http://dx.doi.org/10.17485/ijst/v15i23.1991.

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34

Esther Rani, T., and Dr Rameshwar Rao. "Design of Static Random Access Memory for Minimum Leakage using MTCMOS Technique." CVR Journal of Science & Technology 4, no. 1 (2013): 45–49. http://dx.doi.org/10.32377/cvrjst0409.

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35

f, J. Syamuel John, Ch Mohammad Ari. "Low Power 32-bit Improved Carry Select Adder based on MTCMOS Technique." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 8 (2015): 6831–37. http://dx.doi.org/10.15680/ijirset.2015.0408018.

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36

Lin, S., and H. Yang. "Vdd/2 clock swing D flip-flop using output feedback and MTCMOS." Electronics Letters 42, no. 15 (2006): 853. http://dx.doi.org/10.1049/el:20060776.

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37

Jiao, Hailong, and Volkan Kursun. "Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits." Microelectronics Journal 45, no. 8 (2014): 1125–31. http://dx.doi.org/10.1016/j.mejo.2014.05.006.

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38

Jiao, Hailong, and Volkan Kursun. "Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 3 (2013): 533–45. http://dx.doi.org/10.1109/tvlsi.2012.2190116.

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39

Ramalingam, Anand, Anirudh Devgan, and David Z. Pan. "Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce." Journal of Low Power Electronics 3, no. 1 (2007): 28–35. http://dx.doi.org/10.1166/jolpe.2007.116.

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40

Tian, Xi, Yu Wang, and Zaiwang Dong. "Ground bouncing noise reduction technique considering wake-up delay in MTCMOS circuits." Journal of Electronics (China) 28, no. 4-6 (2011): 596–601. http://dx.doi.org/10.1007/s11767-012-0706-1.

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41

Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to prop

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42

Sultana, Tarunnum. "A Novel Dual Stack Sleep Technique for Reactivation Noise suppression in MTCMOS circuits." IOSR Journal of VLSI and Signal Processing 3, no. 3 (2013): 32–37. http://dx.doi.org/10.9790/4200-0333237.

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43

Zabeli, Milaim, and Betim Hoxha. "Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation." International Review of Electrical Engineering (IREE) 17, no. 1 (2022): 66. http://dx.doi.org/10.15866/iree.v17i1.20555.

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44

Yadav, Ajay, Saurabh Khandelwalb, and Shyam Akashe. "A High Slew Rate Buffer Amplifier Employing MTCMOS Technique for Flat Panel Display." International Journal of Computer Applications 94, no. 13 (2014): 30–35. http://dx.doi.org/10.5120/16405-6104.

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45

Shigematsu, S., S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada. "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits." IEEE Journal of Solid-State Circuits 32, no. 6 (1997): 861–69. http://dx.doi.org/10.1109/4.585288.

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46

Shibata, N., H. Morimura, and M. Harada. "1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs." IEEE Journal of Solid-State Circuits 35, no. 10 (2000): 1396–407. http://dx.doi.org/10.1109/4.871315.

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47

Anis, M. H., M. W. Allam, and M. I. Elmasry. "Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10, no. 2 (2002): 71–78. http://dx.doi.org/10.1109/92.994977.

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48

Abdollahi, Afshin, Farzan Fallah, and Massoud Pedram. "A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 1 (2007): 80–89. http://dx.doi.org/10.1109/tvlsi.2007.891093.

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49

Srinivas, M., and K. V. Daya Sagar. "Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)." Journal of Physics: Conference Series 2089, no. 1 (2021): 012080. http://dx.doi.org/10.1088/1742-6596/2089/1/012080.

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Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. Tha

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50

Zhu, Jia Guo, and Jian Ping Hu. "Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes." Advanced Materials Research 121-122 (June 2010): 281–86. http://dx.doi.org/10.4028/www.scientific.net/amr.121-122.281.

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With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the l

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