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Journal articles on the topic 'Multi-Core and many-Core'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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1

Kumar, Neetesh, and Deo Prakash Vidyarthi. "Improved scheduler for multi-core many-core systems." Computing 96, no. 11 (August 3, 2014): 1087–110. http://dx.doi.org/10.1007/s00607-014-0420-y.

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2

Maliţa, Mihaela, Gheorghe Ştefan, and Dominique Thiébaut. "Not multi-, but many-core." ACM SIGARCH Computer Architecture News 35, no. 5 (December 2007): 32–38. http://dx.doi.org/10.1145/1360464.1360474.

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3

Kirschenmann, W., L. Plagne, A. Ponçot, and S. Vialle. "Parallel SPNon Multi-Core CPUS and Many-Core GPUS." Transport Theory and Statistical Physics 39, no. 2-4 (March 2010): 255–81. http://dx.doi.org/10.1080/00411450.2010.533741.

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4

Datta, Amitava, Amardeep Kaur, Tobias Lauer, and Sami Chabbouh. "Exploiting multi–core and many–core parallelism for subspace clustering." International Journal of Applied Mathematics and Computer Science 29, no. 1 (March 1, 2019): 81–91. http://dx.doi.org/10.2478/amcs-2019-0006.

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Abstract Finding clusters in high dimensional data is a challenging research problem. Subspace clustering algorithms aim to find clusters in all possible subspaces of the dataset, where a subspace is a subset of dimensions of the data. But the exponential increase in the number of subspaces with the dimensionality of data renders most of the algorithms inefficient as well as ineffective. Moreover, these algorithms have ingrained data dependency in the clustering process, which means that parallelization becomes difficult and inefficient. SUBSCALE is a recent subspace clustering algorithm which is scalable with the dimensions and contains independent processing steps which can be exploited through parallelism. In this paper, we aim to leverage the computational power of widely available multi-core processors to improve the runtime performance of the SUBSCALE algorithm. The experimental evaluation shows linear speedup. Moreover, we develop an approach using graphics processing units (GPUs) for fine-grained data parallelism to accelerate the computation further. First tests of the GPU implementation show very promising results.
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5

Benner, Peter, Pablo Ezzatti, Hermann Mena, Enrique Quintana-Ortí, and Alfredo Remón. "Solving Matrix Equations on Multi-Core and Many-Core Architectures." Algorithms 6, no. 4 (November 25, 2013): 857–70. http://dx.doi.org/10.3390/a6040857.

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6

Markall, G. R., A. Slemmer, D. A. Ham, P. H. J. Kelly, C. D. Cantwell, and S. J. Sherwin. "Finite element assembly strategies on multi-core and many-core architectures." International Journal for Numerical Methods in Fluids 71, no. 1 (January 19, 2012): 80–97. http://dx.doi.org/10.1002/fld.3648.

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7

Chitty, Darren M. "Fast parallel genetic programming: multi-core CPU versus many-core GPU." Soft Computing 16, no. 10 (June 9, 2012): 1795–814. http://dx.doi.org/10.1007/s00500-012-0862-0.

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8

Castells-Rufas, David, Eduard Fernandez-Alonso, and Jordi Carrabina. "Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems." International Journal of Reconfigurable Computing 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/736347.

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Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.
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9

Xie, Zhen, Guangming Tan, Weifeng Liu, and Ninghui Sun. "A Pattern-Based SpGEMM Library for Multi-Core and Many-Core Architectures." IEEE Transactions on Parallel and Distributed Systems 33, no. 1 (January 1, 2022): 159–75. http://dx.doi.org/10.1109/tpds.2021.3090328.

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10

Lessley, Brenton, Shaomeng Li, and Hank Childs. "HashFight: A Platform-Portable Hash Table for Multi-Core and Many-Core Architectures." Electronic Imaging 2020, no. 1 (January 26, 2020): 376–1. http://dx.doi.org/10.2352/issn.2470-1173.2020.1.vda-376.

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We introduce a new platform-portable hash table and collision-resolution approach, HashFight, for use in visualization and data analysis algorithms. Designed entirely in terms of dataparallel primitives (DPPs), HashFight is atomics-free and consists of a single code base that can be invoked across a diverse range of architectures. To evaluate its hashing performance, we compare the single-node insert and query throughput of Hash- Fight to that of two best-in-class GPU and CPU hash table implementations, using several experimental configurations and factors. Overall, HashFight maintains competitive performance across both modern and older generation GPU and CPU devices, which differ in computational and memory abilities. In particular, HashFight achieves stable performance across all hash table sizes, and has leading query throughput for the largest sets of queries, while remaining within a factor of 1.5X of the comparator GPU implementation on all smaller query sets. Moreover, HashFight performs better than the comparator CPU implementation across all configurations. Our findings reveal that our platform-agnostic implementation can perform as well as optimized, platform-specific implementations, which demonstrates the portable performance of our DPP-based design.
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11

Vargas, Vanessa, Pablo Ramos, Jean-Francois Méhaut, and Raoul Velazco. "NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors." Applied Sciences 8, no. 3 (March 17, 2018): 465. http://dx.doi.org/10.3390/app8030465.

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12

Rahmani, Amir M., Pasi Liljeberg, Jose L. Ayala, Hannu Tenhunen, and Alexander V. Veidenbaum. "Special issue on energy efficient multi-core and many-core systems, Part I." Journal of Parallel and Distributed Computing 95 (September 2016): 1–2. http://dx.doi.org/10.1016/j.jpdc.2016.04.013.

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13

Rahmani, Amir M., Pasi Liljeberg, Jose L. Ayala, Hannu Tenhunen, and Alexander V. Veidenbaum. "Special issue on energy efficient multi-core and many-core systems, Part II." Journal of Parallel and Distributed Computing 100 (February 2017): 128–29. http://dx.doi.org/10.1016/j.jpdc.2016.10.009.

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14

Aggarwal, Karan, and Uday Bondhugula. "Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems." ACM Transactions on Parallel Computing 7, no. 4 (December 2020): 1–45. http://dx.doi.org/10.1145/3418075.

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15

Shaaban, Adel, M. Sayed, Mohamed Farhat O. Hameed, Hassan I. Saleh, L. R. Gomaa, Yi-Chun Du, and S. S. A. Obayya. "Fast parallel beam propagation method based on multi-core and many-core architectures." Optik 180 (February 2019): 484–91. http://dx.doi.org/10.1016/j.ijleo.2018.11.111.

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16

Melab, Nouredine, and Mohand Mezmaz. "Multi and many-core computing for parallel metaheuristics." Concurrency and Computation: Practice and Experience 29, no. 9 (April 6, 2017): e4116. http://dx.doi.org/10.1002/cpe.4116.

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17

Melab, N., J. Gmys, M. Mezmaz, and D. Tuyttens. "Multi-core versus many-core computing for many-task Branch-and-Bound applied to big optimization problems." Future Generation Computer Systems 82 (May 2018): 472–81. http://dx.doi.org/10.1016/j.future.2016.12.039.

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18

Wu, Nan, Lei Deng, Guoqi Li, and Yuan Xie. "Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning." ACM Transactions on Design Automation of Electronic Systems 26, no. 2 (December 7, 2020): 1–27. http://dx.doi.org/10.1145/3418498.

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19

Silveira, Marcos, Paulo J. P. Gonçalves, and José M. Balthazar. "Multi-core and many-core SPMD parallel algorithms for construction of basins of attraction." Journal of Theoretical and Applied Mechanics 57, no. 4 (October 15, 2019): 1067–79. http://dx.doi.org/10.15632/jtam-pl/112463.

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20

Bethel, E. Wes, and Mark Howison. "Multi-core and many-core shared-memory parallel raycasting volume rendering optimization and tuning." International Journal of High Performance Computing Applications 26, no. 4 (April 3, 2012): 399–412. http://dx.doi.org/10.1177/1094342012440466.

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Given the computing industry trend of increasing processing capacity by adding more cores to a chip, the focus of this work is tuning the performance of a staple visualization algorithm, raycasting volume rendering, for shared-memory parallelism on multi-core CPUs and many-core GPUs. Our approach is to vary tunable algorithmic settings, along with known algorithmic optimizations and two different memory layouts, and measure performance in terms of absolute runtime and L2 memory cache misses. Our results indicate there is a wide variation in runtime performance on all platforms, as much as 254% for the tunable parameters we test on multi-core CPUs and 265% on many-core GPUs, and the optimal configurations vary across platforms, often in a non-obvious way. For example, our results indicate the optimal configurations on the GPU occur at a crossover point between those that maintain good cache utilization and those that saturate computational throughput. This result is likely to be extremely difficult to predict with an empirical performance model for this particular algorithm because it has an unstructured memory access pattern that varies locally for individual rays and globally for the selected viewpoint. Our results also show that optimal parameters on modern architectures are markedly different from those in previous studies run on older architectures. In addition, given the dramatic performance variation across platforms for both optimal algorithm settings and performance results, there is a clear benefit for production visualization and analysis codes to adopt a strategy for performance optimization through auto-tuning. These benefits will likely become more pronounced in the future as the number of cores per chip and the cost of moving data through the memory hierarchy both increase.
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21

Lopez-Novoa, Unai, Jon Sáenz, Alexander Mendiburu, and Jose Miguel-Alonso. "An efficient implementation of kernel density estimation for multi-core and many-core architectures." International Journal of High Performance Computing Applications 29, no. 3 (March 16, 2015): 331–47. http://dx.doi.org/10.1177/1094342015576813.

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22

Zhang, Jianting, Simin You, and Le Gruenwald. "Parallel online spatial and temporal aggregations on multi-core CPUs and many-core GPUs." Information Systems 44 (August 2014): 134–54. http://dx.doi.org/10.1016/j.is.2014.01.005.

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23

Zhu, Huming, Pei Li, Peng Zhang, and Zheng Luo. "A High Performance Parallel Ranking SVM with OpenCL on Multi-core and Many-core Platforms." International Journal of Grid and High Performance Computing 11, no. 1 (January 2019): 17–28. http://dx.doi.org/10.4018/ijghpc.2019010102.

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A ranking support vector machine (RSVM) is a typical pairwise method of learning to rank, which is effective in ranking problems. However, the training speed of RSVMs are not satisfactory, especially when solving large-scale data ranking problems. Recent years, many-core processing units (graphics processing unit (GPU), Many Integrated Core (MIC)) and multi-core processing units have exhibited huge superiority in the parallel computing domain. With the support of hardware, parallel programming develops rapidly. Open Computing Language (OpenCL) and Open Multi-Processing (OpenMP) are two of popular parallel programming interfaces. The authors present two high-performance parallel implementations of RSVM, an OpenCL version implemented on multi-core and many-core platforms, and an OpenMP version implemented on multi-core platform. The experimental results show that the OpenCL version parallel RSVM achieved considerable speedup on Intel MIC 7110P, NVIDIA Tesla K20M and Intel Xeon E5-2692v2, and it also shows good portability.
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24

de Doncker, E., F. Yuasa, A. Almulihi, N. Nakasato, H. Daisaka, and T. Ishikawa. "Numerical multi-loop integration on heterogeneous many-core processors." Journal of Physics: Conference Series 1525 (April 2020): 012002. http://dx.doi.org/10.1088/1742-6596/1525/1/012002.

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25

Cafaro, Massimo, Marco Pulimeno, Italo Epicoco, and Giovanni Aloisio. "Parallel space saving on multi- and many-core processors." Concurrency and Computation: Practice and Experience 30, no. 7 (April 27, 2017): e4160. http://dx.doi.org/10.1002/cpe.4160.

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26

Chi, Chi Ching, Mauricio Alvarez-Mesa, Jan Lucas, Ben Juurlink, and Thomas Schierl. "Parallel HEVC Decoding on Multi- and Many-core Architectures." Journal of Signal Processing Systems 71, no. 3 (December 15, 2012): 247–60. http://dx.doi.org/10.1007/s11265-012-0714-2.

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27

Bradatsch, Christian, Sebastian Schlingmann, Sascha Uhrig, and Theo Ungerer. "MANJAC — Ein Many-Core-Emulator auf Multi-FPGA-Basis." PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware 28, no. 1 (October 2011): 48–57. http://dx.doi.org/10.1007/bf03341984.

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28

Bolchini, Cristiana, Matteo Carminati, and Antonio Miele. "Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems." Journal of Electronic Testing 29, no. 2 (April 2013): 159–75. http://dx.doi.org/10.1007/s10836-013-5367-y.

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29

Torti, Emanuele, Alessandro Fontanella, Antonio Plaza, Javier Plaza, and Francesco Leporati. "Hyperspectral Image Classification Using Parallel Autoencoding Diabolo Networks on Multi-Core and Many-Core Architectures." Electronics 7, no. 12 (December 8, 2018): 411. http://dx.doi.org/10.3390/electronics7120411.

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One of the most important tasks in hyperspectral imaging is the classification of the pixels in the scene in order to produce thematic maps. This problem can be typically solved through machine learning techniques. In particular, deep learning algorithms have emerged in recent years as a suitable methodology to classify hyperspectral data. Moreover, the high dimensionality of hyperspectral data, together with the increasing availability of unlabeled samples, makes deep learning an appealing approach to process and interpret those data. However, the limited number of labeled samples often complicates the exploitation of supervised techniques. Indeed, in order to guarantee a suitable precision, a large number of labeled samples is normally required. This hurdle can be overcome by resorting to unsupervised classification algorithms. In particular, autoencoders can be used to analyze a hyperspectral image using only unlabeled data. However, the high data dimensionality leads to prohibitive training times. In this regard, it is important to realize that the operations involved in autoencoders training are intrinsically parallel. Therefore, in this paper we present an approach that exploits multi-core and many-core devices in order to achieve efficient autoencoders training in hyperspectral imaging applications. Specifically, in this paper, we present new OpenMP and CUDA frameworks for autoencoder training. The obtained results show that the CUDA framework provides a speed-up of about two orders of magnitudes as compared to an optimized serial processing chain.
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30

Kazemian, Fazeleh Sadat, Mahmood Fazlali, Ali Katanforoush, and Mojtaba Rezvani. "Parallel implementation of quorum planted (ℓ, d ) motif search on multi-core/many-core platforms." Microprocessors and Microsystems 46 (October 2016): 255–63. http://dx.doi.org/10.1016/j.micpro.2016.06.008.

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31

Xing, Yuxuan, Fang Liu, Nong Xiao, Zhiguang Chen, and Yutong Lu. "Capability for Multi-Core and Many-Core Memory Systems: A Case-Study With Xeon Processors." IEEE Access 7 (2019): 47655–62. http://dx.doi.org/10.1109/access.2018.2881460.

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32

Zhang, Jikai, Haidong Lan, Yuandong Chan, Yuan Shang, Bertil Schmidt, and Weiguo Liu. "BGSA: a bit-parallel global sequence alignment toolkit for multi-core and many-core architectures." Bioinformatics 35, no. 13 (November 16, 2018): 2306–8. http://dx.doi.org/10.1093/bioinformatics/bty930.

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Abstract Motivation Modern bioinformatics tools for analyzing large-scale NGS datasets often need to include fast implementations of core sequence alignment algorithms in order to achieve reasonable execution times. We address this need by presenting the BGSA toolkit for optimized implementations of popular bit-parallel global pairwise alignment algorithms on modern microprocessors. Results BGSA outperforms Edlib, SeqAn and BitPAl for pairwise edit distance computations and Parasail, SeqAn and BitPAl when using more general scoring schemes for pairwise alignments of a batch of sequence reads on both standard multi-core CPUs and Xeon Phi many-core CPUs. Furthermore, banded edit distance performance of BGSA on a Xeon Phi-7210 outperforms the highly optimized NVBio implementation on a Titan X GPU for the seed verification stage of a read mapper by a factor of 4.4. Availability and implementation BGSA is open-source and available at https://github.com/sdu-hpcl/BGSA. Supplementary information Supplementary data are available at Bioinformatics online.
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33

Burke, Neil, Andrew Rau-Chaplin, and Blesson Varghese. "Computing probable maximum loss in catastrophe reinsurance portfolios on multi-core and many-core architectures." Concurrency and Computation: Practice and Experience 28, no. 3 (October 12, 2015): 836–47. http://dx.doi.org/10.1002/cpe.3695.

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34

Silva Junior, Manoel Baptista, Jairo Panetta, and Stephan Stephany. "Portability with efficiency of the advection of BRAMS between multi-core and many-core architectures." Concurrency and Computation: Practice and Experience 29, no. 22 (September 16, 2016): e3959. http://dx.doi.org/10.1002/cpe.3959.

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35

Vigueras, Guillermo, Juan M. Orduña, Miguel Lozano, José M. Cecilia, and José M. García. "Accelerating collision detection for large-scale crowd simulation on multi-core and many-core architectures." International Journal of High Performance Computing Applications 28, no. 1 (February 19, 2013): 33–49. http://dx.doi.org/10.1177/1094342013476119.

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36

Nedjah, Nadia, Rogério de M. Calazan, Luiza de Macedo Mourelle, and Chao Wang. "Parallel Implementations of the Cooperative Particle Swarm Optimization on Many-core and Multi-core Architectures." International Journal of Parallel Programming 44, no. 6 (June 5, 2015): 1173–99. http://dx.doi.org/10.1007/s10766-015-0368-3.

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37

Hofmann, Johannes, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, and Gerhard Wellein. "Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors." Concurrency and Computation: Practice and Experience 29, no. 9 (August 3, 2016): e3921. http://dx.doi.org/10.1002/cpe.3921.

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38

Waltz, J., J. G. Wohlbier, L. D. Risinger, T. R. Canfield, M. R. J. Charest, A. R. Long, and N. R. Morgan. "Performance analysis of a 3D unstructured mesh hydrodynamics code on multi-core and many-core architectures." International Journal for Numerical Methods in Fluids 77, no. 6 (November 27, 2014): 319–33. http://dx.doi.org/10.1002/fld.3982.

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39

You, Yang, Haohuan Fu, Shuaiwen Leon Song, Maryam Mehri Dehnavi, Lin Gan, Xiaomeng Huang, and Guangwen Yang. "Evaluating multi-core and many-core architectures through accelerating the three-dimensional Lax–Wendroff correction stencil." International Journal of High Performance Computing Applications 28, no. 3 (March 5, 2014): 301–18. http://dx.doi.org/10.1177/1094342014524807.

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40

Kan, Guangyuan, Ke Liang, Jiren Li, Liuqian Ding, Xiaoyan He, Youbing Hu, and Mark Amo-Boateng. "Accelerating the SCE-UA Global Optimization Method Based on Multi-Core CPU and Many-Core GPU." Advances in Meteorology 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8483728.

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The famous global optimization SCE-UA method, which has been widely used in the field of environmental model parameter calibration, is an effective and robust method. However, the SCE-UA method has a high computational load which prohibits the application of SCE-UA to high dimensional and complex problems. In recent years, the hardware of computer, such as multi-core CPUs and many-core GPUs, improves significantly. These much more powerful new hardware and their software ecosystems provide an opportunity to accelerate the SCE-UA method. In this paper, we proposed two parallel SCE-UA methods and implemented them on Intel multi-core CPU and NVIDIA many-core GPU by OpenMP and CUDA Fortran, respectively. The Griewank benchmark function was adopted in this paper to test and compare the performances of the serial and parallel SCE-UA methods. According to the results of the comparison, some useful advises were given to direct how to properly use the parallel SCE-UA methods.
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41

Maity, Arka, Anuj Pathania, and Tulika Mitra. "PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications." Journal of Low Power Electronics and Applications 10, no. 4 (September 30, 2020): 31. http://dx.doi.org/10.3390/jlpea10040031.

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Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework.
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42

Martins, André Luís del Mestre, Alzemiro Henrique Lucas da Silva, Amir M. Rahmani, Nikil Dutt, and Fernando Gehm Moraes. "Hierarchical adaptive Multi-objective resource management for many-core systems." Journal of Systems Architecture 97 (August 2019): 416–27. http://dx.doi.org/10.1016/j.sysarc.2019.01.006.

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43

Rupp, Karl, Philippe Tillet, Florian Rudolf, Josef Weinbub, Andreas Morhammer, Tibor Grasser, Ansgar Jüngel, and Siegfried Selberherr. "ViennaCL---Linear Algebra Library for Multi- and Many-Core Architectures." SIAM Journal on Scientific Computing 38, no. 5 (January 2016): S412—S439. http://dx.doi.org/10.1137/15m1026419.

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44

Zapletal, Jan, Michal Merta, and Lukáš Malý. "Boundary element quadrature schemes for multi- and many-core architectures." Computers & Mathematics with Applications 74, no. 1 (July 2017): 157–73. http://dx.doi.org/10.1016/j.camwa.2017.01.018.

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45

Gu, Xiongli, Peng Liu, Mei Yang, Jie Yang, Cheng Li, and Qingdong Yao. "An efficient scheduler of RTOS for multi/many-core system." Computers & Electrical Engineering 38, no. 3 (May 2012): 785–800. http://dx.doi.org/10.1016/j.compeleceng.2011.09.009.

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46

Florimbi, Giordana, Emanuele Torti, Stefano Masoli, Egidio D’Angelo, Giovanni Danese, and Francesco Leporati. "Exploiting multi-core and many-core architectures for efficient simulation of biologically realistic models of Golgi cells." Journal of Parallel and Distributed Computing 126 (April 2019): 48–66. http://dx.doi.org/10.1016/j.jpdc.2018.12.004.

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47

Nagasaka, Yusuke, Satoshi Matsuoka, Ariful Azad, and Aydın Buluç. "Performance optimization, modeling and analysis of sparse matrix-matrix products on multi-core and many-core processors." Parallel Computing 90 (December 2019): 102545. http://dx.doi.org/10.1016/j.parco.2019.102545.

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48

Pereira, Pedro M. M., Patricio Domingues, Nuno M. M. Rodrigues, Gabriel Falcao, and Sergio M. M. Faria. "Assessing the Performance and Energy Usage of Multi-CPUs, Multi-Core and Many-Core Systems : The MMP Image Encoder Case Study." International Journal of Distributed and Parallel systems 7, no. 5 (September 30, 2016): 01–20. http://dx.doi.org/10.5121/ijdps.2016.750.

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49

Ma, Kai, Xue Li, Ming Chen, and Xiaorui Wang. "Scalable power control for many-core architectures running multi-threaded applications." ACM SIGARCH Computer Architecture News 39, no. 3 (June 22, 2011): 449–60. http://dx.doi.org/10.1145/2024723.2000117.

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50

Kegel, Philipp, Michel Steuwer, and Sergei Gorlatch. "dOpenCL: Towards uniform programming of distributed heterogeneous multi-/many-core systems." Journal of Parallel and Distributed Computing 73, no. 12 (December 2013): 1639–48. http://dx.doi.org/10.1016/j.jpdc.2013.07.021.

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