Relevant bibliographies by topics / Multi-core embedded system

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Multi-core embedded system'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Multi-core embedded system"

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Hussain, Tassadaq, Amna Haider, Adrian Cristal, and Eduard Ayguadé. "EMVS: Embedded Multi Vector-core System." Journal of Systems Architecture 87 (June 2018): 12–22. http://dx.doi.org/10.1016/j.sysarc.2018.04.002.

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Danese, G., M. Giachero, F. Leporati, and N. Nazzicari. "An embedded multi-core biometric identification system." Microprocessors and Microsystems 35, no. 5 (2011): 510–21. http://dx.doi.org/10.1016/j.micpro.2011.03.003.

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Chen, Haorui. "Optimization Methods of Multi-Core Embedded System." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 153–62. http://dx.doi.org/10.54097/hset.v71i.12686.

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With the development of the Internet of everything technology, embedded system has become one of the most common computing systems. Embedded system has high portability, but there are often stronger limitations in energy consumption, real-time and so on. In this work, have improved some traditional optimization algorithms, and finally get a task scheduling sequence, which can reduce the total execution time and cost of the task. Firstly, the multi-module division is used to divide multiple tasks into different modules, improve the classical Kernighan-Lin (KL) algorithm and clustering algorithm implement this process. Second, this paper invokes a series of algorithms to calculate the priority value of the task. Finally, this paper call two multi-core scheduling algorithms to schedule the tasks within each module to the Central Processing Unit (CPU) in the module. The proposed algorithm is implemented in this paper. With directed acyclic graph as input, the improvement effect of the algorithm and the direct advantages and disadvantages of different algorithms are evaluated with different task quantity.
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Madsen, Jan, Michael R. Hansen, Kristian S. Knudsen, Jens E. Nielsen, and Aske W. Brekling. "System-level Verification of Multi-Core Embedded Systems using Timed-Automata." IFAC Proceedings Volumes 41, no. 2 (2008): 9302–7. http://dx.doi.org/10.3182/20080706-5-kr-1001.01572.

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Castells-Rufas, David, Eduard Fernandez-Alonso, and Jordi Carrabina. "Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems." International Journal of Reconfigurable Computing 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/736347.

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Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.
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Yuan, Ningze, and Hao Meng. "Software architecture and implementation based on multi-core digital signal processors." Journal of Physics: Conference Series 2797, no. 1 (2024): 012053. http://dx.doi.org/10.1088/1742-6596/2797/1/012053.

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Abstract Embedded detection systems are a critical research topic in intelligent monitoring equipment. In response to the current challenges in balancing real-time performance, accuracy, and stability in embedded hardware detection systems, this paper proposes a software architecture system based on multi-core digital signal processing (DSP), incorporating the image detection Canny algorithm into this system. Initially, the paper discusses the selection criteria for multi-core DSPs and then introduces a multi-core self-check function that can effectively ensure system stability. It also proposes a multi-core communication handshake protocol that significantly enhances the system’s real-time performance. Furthermore, an improved multi-core master-slave architecture is presented, which includes the addition of a timer to the conventional architecture, providing a temporal guarantee for system operation. Finally, the Canny algorithm is selected and applied to this software architecture, with parallel acceleration processing applied to parts of the algorithm. Operational tests have demonstrated that the system maintains stable internal data flow, with its detection accuracy and speed meeting the set requirements.
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Pahikkala, Tapio, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, and Tapio Salakoski. "Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 3, no. 2 (2012): 73–91. http://dx.doi.org/10.4018/jertcs.2012040104.

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The authors introduce a machine learning approach based on parallel online regularized least-squares learning algorithm for parallel embedded hardware platforms. The system is suitable for use in real-time adaptive systems. Firstly, the system can learn in online fashion, a property required in real-life applications of embedded machine learning systems. Secondly, to guarantee real-time response in embedded multi-core computer architectures, the learning system is parallelized and able to operate with a limited amount of computational and memory resources. Thirdly, the system can predict several labels simultaneously. The authors evaluate the performance of the algorithm from three different perspectives. The prediction performance is evaluated on a hand-written digit recognition task. The computational speed is measured from 1 thread to 4 threads, in a quad-core platform. As a promising unconventional multi-core architecture, Network-on-Chip platform is studied for the algorithm. The authors construct a NoC consisting of a 4x4 mesh. The machine learning algorithm is implemented in this platform with up to 16 threads. It is shown that the memory consumption and cache efficiency can be considerably improved by optimizing the cache behavior of the system. The authors’ results provide a guideline for designing future embedded multi-core machine learning devices.
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Huang, Shujuan, Yi'an Zhu, Bailin Liu, and Feng Xiao. "Research on Three Dimensional Scheduling Model for Embedded Multi-Core System." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 36, no. 5 (2018): 1020–25. http://dx.doi.org/10.1051/jnwpu/20183651020.

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This paper proposes a new three-dimensional scheduling model which can divide the tasks into harmonic tasks and non-harmonic tasks for the high demands of embedded mucticne plactorim. According to the characteristic parameters of the tasks and make the value of the rectangular area as the attribute of the execution region which is divided into executive region, interference region and free region with the characteristic of the area. By using these attributes of the different region, the tasks are allocated to different cores. Experimental results show that the proposed method is more fully optimizing the system utilization and throughput than PEDF.
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Dong, Shichao, Shukun Yao, and Lijin Kang. "Underwater acoustic beacon detection device based on Embedded System." Journal of Physics: Conference Series 2528, no. 1 (2023): 012033. http://dx.doi.org/10.1088/1742-6596/2528/1/012033.

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Abstract Based on the current situation of large volume and single detection function of the underwater acoustic beacon detection device, combined with the requirements of multi-parameter detection of underwater acoustic beacon function and performance, an embedded underwater acoustic beacon multi-parameter detection device is developed. The detection device uses ARM as the core processor, carries Linux embedded system, and establishes QT graphical user interface. The detection device can realize the acoustic signal of underwater acoustic beacon Frequency, pulse width, period, sound source level, spectrum, and other multi-parameter detection and graphical display of the test results.
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Gou, Mingrui, Bangji Wang, and Xilin Zhang. "Development of Multi-Motor Servo Control System Based on Heterogeneous Embedded Platforms." Electronics 13, no. 15 (2024): 2957. http://dx.doi.org/10.3390/electronics13152957.

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Multi-motor servo systems are widely used in industrial control. However, the single-core microprocessor architecture based on the microcontroller unit (MCU) and digital signal processor (DSP) is not well suited for high-performance multi-motor servo systems due to the inherent limitations in computing performance and serial execution of code. The bus-based distributed architecture formed by interconnecting multiple unit controllers increases system communication complexity, reduces system integration, and incurs additional hardware and software costs. Field programmable gate array (FPGA) possesses the characteristics of high real-time performance, parallel processing, and modularity. A single FPGA can integrate multiple motor servo controllers. This research uses MCU + FPGA as the core to realize high-precision multi-axis real-time control, combining the powerful performance of the MCU processor and the high-speed parallelism of FPGA. The MCU serves as the central processor and facilitates data interaction with the host computer through the controller area network (CAN). After data parsing and efficient computation, MCU communicates with the FPGA through flexible static memory controller (FSMC). A motor servo controller intellectual property (IP) core is designed and packaged for easy reuse within the FPGA. A 38-axis micro direct current (DC) motor control system is constructed to test the performance of the IP core and the heterogeneous embedded platforms. The experimental results show that the designed IP core exhibits robust functionality and scalability. The system exhibits high real-time performance and reliability.
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Dissertations / Theses on the topic "Multi-core embedded system"

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Zhang, Wei. "Design and Implementation of Multi-core Support for an Embedded Real-time Operating System for Space Applications." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174880.

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Nowadays, multi-core processors are widely used in embedded applications due to the advantages of higher performance and lower power consumption. However, the complexity of multi-core architectures makes it a considerably challenging task to extend a single-core version of a real-time operating system to support multi-core platform. This thesis documents the process of design and implementation of a multi-core version of RODOS - an embedded real-time operating system developed by German Aerospace Center and the University of Würzburg - on a dual-core platform. Two possible models are proposed: Symmetric Multiprocessing and Asymmetric Multiprocessing. In order to prevent the collision of the global components initialization, a new multi-core boot loader is created to allow that each core boots up in a proper manner. A working version of multi-core RODOS is implemented that has an ability to run tasks on a multi-core platform. Several test cases are applied and verified that the performance on the multi-core version of RODOS achieves around 180% improved than the same tasks running on the original RODOS. Deadlock free communication and synchronization APIs are provided to let parallel applications share data and messages in a safe manner.
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Li, Lin [Verfasser], Andreas [Akademischer Betreuer] Herkersdorf, Frank [Gutachter] Slomka, and Andreas [Gutachter] Herkersdorf. "A Traced-based Automated System Diagnosis and Software Debugging Methodology for Embedded Multi-core Systems / Lin Li ; Gutachter: Frank Slomka, Andreas Herkersdorf ; Betreuer: Andreas Herkersdorf." München : Universitätsbibliothek der TU München, 2019. http://d-nb.info/1193177618/34.

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Zabel, Martin. "Effiziente Mehrkernarchitektur für eingebettete Java-Bytecode-Prozessoren." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84156.

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Die Java-Plattform bietet viele Vorteile für die schnelle Entwicklung komplexer Software. Für die Ausführung des Java-Bytecodes auf eingebetteten Systemen eignen sich insbesondere Java-(Bytecode)-Prozessoren, die den Java-Bytecode als nativen Befehlssatz unterstützen. Die vorliegende Arbeit untersucht detailliert die Gestaltung einer Mehrkernarchitektur für Java-Prozessoren zur effizienten Nutzung der auf Thread-Ebene ohnehin vorhandenen Parallelität eines Java-Programms. Für die Funktionalitäts- und Leistungsbewertung eines Prototyps wird eine eigene Trace-Architektur eingesetzt. Es wird eine hohe Leistungssteigerung bei nur geringem zusätzlichem Hardwareaufwand erzielt sowie eine höhere Leistung als bekannte alternative Ansätze erreicht.
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Grosic, Hasan, and Emir Hasanovic. "Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.

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The demand for computing power and performance in real-time embedded systems is continuously increasing since new customer requirements and more advanced features are appearing every day. To support these functionalities and handle them in a more efficient way, multi-core computing platforms are introduced. These platforms allow for parallel execution of tasks on multiple cores, which in addition to its benefits to the system's performance introduces a major problem regarding the timing predictability of the system. That problem is reflected in unpredictable inter-core interferences, which occur due to shared resources among the cores, such as the system bus. This thesis investigates the application of different optimization techniques for the offline scheduling of tasks on the individual cores, together with a global scheduling policy for the access to the shared bus. The main effort of this thesis focuses on optimizing the inter-core data propagation delays which can provide a new way of creating optimized schedules. For that purpose, Constraint Programming optimization techniques are employed and a Phased Execution Model of the tasks is assumed. Also, in order to enforce end-to-end timing constraints that are imposed on the system, job-level dependencies are generated prior and subsequently applied during the scheduling procedure. Finally, an experiment with a large number of test cases is conducted to evaluate the performance of the implemented scheduling approach. The obtained results show that the method is applicable for a wide spectrum of abstract systems with variable requirements, but also open for further improvement in several aspects.
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Åberg, Emil. "MINIMIZING INTER-CORE DATA-PROPAGATION DELAYS IN PARTITIONED MULTI-CORE REAL-TIME SYSTEMS USING SCHEDULING HEURISTICS." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-54616.

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In the field of embedded systems, computers embedded into machines ranging from microwaveovensto assembly lines impact the physical world. They do so under tight real-time constraintswith ever-increasing demand for computing power and performance. Development of higher speedprocessors have been hampered by diminishing returns on power consumption as clock frequency isfurther increased. For this reason, today, embedded processor development is instead moving towardfurther concurrency with multi-core processors being considered more and more every day. Withparallelism comes challenges, such as interference caused by shared resources. Contention betweenprocessor cores, such as shared memory, result in inter-core interference which is potentially unpredictableand unbounded. The focus of this thesis is placed on minimizing inter-core interferencewhile meeting local task timing requirements by utilizing scheduling heuristics. A scheduling heuristicis designed and a prototype scheduler which implements this algorithm is developed. Thescheduler is evaluated on randomly generated test cases, where its ability to keep inter-core datapropagationdelays low across different core counts and utilization values was evaluated. The algorithmis also compared with constraint programming in a real world industrial test case. Theobtained results show that the algorithm can produce schedules with low inter-core delays in a veryshort time, although not being able to optimize them fully compared to constraint programming.
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Vidović, Tin, and Lamija Hasanagić. "TIGHTER INTER-CORE DELAYS IN MULTI-CORE EMBEDDED SYSTEMS UNDER PARTITIONED SCHEDULING." Thesis, Mälardalens högskola, Inbyggda system, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-48575.

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There exists an increasing demand for computing power and performance in real-time embedded systems, as new, more complex customer requirements and function-alities are appearing every day. In order to support these requirements and func-tionalities without breaking the power consumption wall, many embedded systems areswitching from traditional single-core hardware architectures to multi-core architec-tures. Multi-core architectures allow for parallel execution of tasks on the multiplecores. This introduces many benets from the perspective of achievable performance,but in turn introduces major issues when it comes to the timing predictability ofthe real-time embedded system applications deployed on them. The problem arisesfrom unpredictable and potentially unbounded inter-core interferences, which occuras a result of contention for the shared resources, such as the shared system busor shared system memory. This thesis studies the possible application of constraintprogramming as a resource optimization technique for the purpose of creating oineschedules for tasks in real-time embedded system applications executing on a dual-core architecture. The main focus is placed on tightening inter-core data-propagationinterferences, which can result in lower over-all data-propagation delays. A proto-type of an optimization engine, employing constraint programming techniques on ap-plications comprised of tasks structured according to the Phased Execution Model isdeveloped. The prototype is evaluated through several experiments on a large numberof industry inspired intellectual-property free benchmarks. Alongside the experimentsa case study is conducted on an example engine-control application and the resultingschedule is compared to a schedule generated by the Rubus-ICE industrial tool suite.The obtained results show that the proposed method is applicable to a potentially widerange of abstract systems with dierent requirements. The limitations of the methodare also discussed and potential future work is debated based on these results.<br><p>Presentation was held over Zoom, due to the COVID-19 situation.</p>
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Kerrison, Steven P. "Energy modelling of multi-threaded, multi-core software for embedded systems." Thesis, University of Bristol, 2015. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.682488.

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Efforts to reduce energy consumption are being made across all disciplines. ICT's contribution to global energy consumption and by-products such as C02 emissions continues to grow, making it an increasingly significant area in which improvements must be made. This thesis focuses on software as a means to reducing energy consumption. It presents methods for profiling and modelling a multi-threaded, multi-core embedded processor at the instruction set level, establishing links between the software and the energy consumed by the underlying hardware. A framework is presented that profiles the energy consumption characteristics of a multi-threaded processor core, associating energy consumption with the instruction set and parallelism present in a multi-threaded program. This profiling data is used to build a model of the processor that allows instruction set simulations to be used to estimate the energy that programs will consume, with an average of 2.67 % error. The profiling and modelling is then raised to the multi-core level, examining a channel based message passing system formed of a network of embedded multi-threaded processors. Additional profiling is presented that determines network communication costs as well as giving consideration towards system level properties such as power supply efficiency. Then, this is used to form a system level energy model that can estimate consumption using simulations of multi-core programs. The system level model combines multiple instances of a core energy model with a network level communication cost model. The broader implications of this work are explored in the context of other embedded and multi-core processor architectures, identifying opportunities for expanding or transferring the models. The models in this thesis are formed at the instruction set level, but have been demonstrated to be effective at higher-levels of abstraction than instruction set simulation, through their support of further work carried out externally. This work is enabled by several pieces of development effort, including a profiling framework for taking power measurements-of the devices under investigation, tools for programming, routing and debugging software on a multi-core hardware platform called Swallow, and enhancements to an instruction set simulator for the simulation of this multi-core system. Through the work of this thesis, an embedded software developer for multi-threaded and multi-core systems is equipped with tools, techniques and new understanding that can help them in determining how their software consumes energy. This raises the status of energy efficiency in the software development cycle as we
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González-conde, pérez José Luis. "Analysis of task scheduling for multi-core embedded systems." Thesis, KTH, Maskinkonstruktion (Inst.), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-186330.

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This thesis performs a research on scheduling algorithms for parallel appli-cations. The main focus is their usage on multi-core embedded systems’ appli-cations. A parallel application can be described by a directed acyclic graph. A directed acyclic graph is a mathematical model that represents the parallel application as a set of nodes or tasks and a set of edges or communication messages between nodes.In this thesis scheduling is limited to the management of multiple cores on a multi-core platform for the execution of application tasks. Tasks are mapped onto the cores and their start times are determined afterwards. A toolchain is implemented to develop and schedule parallel applications on a Epiphany E16 developing board, which is a low-cost board with a 16 core chip called Epiphany. The toolchain is limited to the usage of o˜ine scheduling algorithms which compute a schedule before running the application.The programmer has to draw a directed acyclic graph with the main at-tributes of the application. The toolchain then generates the code for the target which automatically handles the inter-task communication. Some metrics are established to help evaluate the performance of applications on the target plat-form, such as the execution time and the energy consumption. Measurements on the Epiphany E16 developing board are performed to estimate the energy consumption of the multi-core chip as a function of the number of idle cores.A set of 12 directed acyclic graphs are used to verify that the toolchain works correctly. They cover di˙erent aspects: join nodes, fork nodes, more than one entry node, more than one exit node, di˙erent tasks weights and di˙erent communication costs.A use case is given, the development of a brake-by-wire demonstration platform. The platform aims to use the Epiphany board. Three experiments are performed to analyze the performance of parallel computing for the use case. Three brake-by-wire applications are implemented, one for a single core system and two for a multi-core system. The parallel application scheduled with a list-based algorithm requires 266% more time and 1346% more energy than the serial application. The parallel application scheduled with a task duplication algorithm requires 46% less time and 134% more energy than the serial application.The toolchain system has proven to be a useful tool for developing paral-lel applications since it automatically handles the inter-task communication. However, future work can be done to automatize the decomposition of serial applications from the source code. The conclusion is that this communication system is suitable for coarse granularity, where the communication overhead does not a˙ect so much. Task duplication is better to use for fine granularity since inter-core communication is avoided by doing extra computations.
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Gonzales-Conde, Perez José Luis. "Analysis of task scheduling for multi-core embedded systems." Thesis, KTH, Maskinkonstruktion (Inst.), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-202548.

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This thesis performs a research on scheduling algorithms for parallel applications.The main focus is their usage on multi-core embedded systems’ applications.A parallel application can be described by a directed acyclic graph.A directed acyclic graph is a mathematical model that represents the parallelapplication as a set of nodes or tasks and a set of edges or communicationmessages between nodes.In this thesis scheduling is limited to the management of multiple coreson a multi-core platform for the execution of application tasks. Tasks aremapped onto the cores and their start times are determined afterwards. Atoolchain is implemented to develop and schedule parallel applications on aEpiphany E16 developing board, which is a low-cost board with a 16 core chipcalled Epiphany. The toolchain is limited to the usage of offline schedulingalgorithms which compute a schedule before running the application.The programmer has to draw a directed acyclic graph with the main attributesof the application. The toolchain then generates the code for the targetwhich automatically handles the inter-task communication. Some metrics areestablished to help evaluate the performance of applications on the target platform,such as the execution time and the energy consumption. Measurementson the Epiphany E16 developing board are performed to estimate the energyconsumption of the multi-core chip as a function of the number of idle cores.A set of 12 directed acyclic graphs are used to verify that the toolchainworks correctly. They cover different aspects: join nodes, fork nodes, morethan one entry node, more than one exit node, different tasks weights anddifferent communication costs.A use case is given, the development of a brake-by-wire demonstrationplatform. The platform aims to use the Epiphany board. Three experimentsare performed to analyze the performance of parallel computing for the usecase. Three brake-by-wire applications are implemented, one for a single coresystem and two for a multi-core system. The parallel application scheduledwith a list-based algorithm requires 266% more time and 1346% more energythan the serial application. The parallel application scheduled with a taskduplication algorithm requires 46% less time and 134% more energy than theserial application.The toolchain system has proven to be a useful tool for developing parallelapplications since it automatically handles the inter-task communication.However, future work can be done to automatize the decomposition of serialapplications from the source code. The conclusion is that this communicationsystem is suitable for coarse granularity, where the communication overheaddoes not affect so much. Task duplication is better to use for fine granularitysince inter-core communication is avoided by doing extra computations.<br>Detta examensarbete utför en studie av om schemaläggningsalgoritmer förparallella applikationer. Huvudfokus är deras användning för flerkärniga inbyggdasystemapplikationer. En parallell applikation kan beskrivas genom enriktad acyklisk graf. En riktad acyklisk graf är en matematisk modell somrepresenterar den parallella applikationen som en uppsättning av noder, elleruppgifter, och en uppsättning av pilar, eller meddelanden, mellan noder.I denna uppsats är schemaläggning begränsad till hanteringen av flerakärnor på en multikärnig plattform för genomförandet av applikationens uppgifter.Uppgifter mappas på kärnorna och deras starttider bestäms efteråt. Enspeciell verktygskedja kallad ett ”toolchain system” har tagits fram för attutveckla och schemalägga parallella applikationer på ett Epiphany E16 kort,vilket är ett billigt kort med ett 16-kärnigt chip som kallas Epiphany. Toolchainsystemet är begränsat till användningen av offline schemaläggningsalgoritmersom beräknar ett schema innan du kör programmet.Programmeraren måste rita en riktad acyklisk graf med de viktigaste attributen.Toolchain systemet genererar därefter kod som automatiskt hanterarkommunikationen mellan uppgifterna. Ett antal prestandamått defineras föratt kunna utvärdera applikationer på målplattformen, såsom genomförandetidoch energiförbrukning. Mätningar på Epiphany E16 kortet genomförs för attuppskatta energiförbrukningen som en funktion av antalet lediga kärnor.En uppsättning av 12 riktade acykliska grafer används för att kontrolleraatt toolchain systemet fungerar korrekt. De täcker olika aspekter: noder somgår ihop, noder som går isär, fler än en ingångsnod, fler än en utgångsnod,olika vikter på uppgifterna och olika kommunikationskostnader.Ett användningsfall ges, utveckling av en brake-by-wire demonstrationsplattform. Plattformen syftar till att använda Epiphany kortet. Tre experimentutförs för att analysera resultatet av parallella beräkningar för användningsfallet.Tre brake-by-wire applikationer genomförs, en för ett enda kärnsystemoch två för ett multikärnigt system. Den parallella applikationen somvar schemalagd med en algoritm baserad på listor kräver 266% mer tid och1346% mer energi än den seriella applikationen. Den parallella applikationensom var schemalagd med en uppgiftsduplicerings-algoritm kräver 46% mindretid och 134% mer energi än den seriella applikationen.Toolchain systemet har visat sig att vara ett användbart verktyg för attutveckla parallella applikationer eftersom det automatiskt hanterar kommunikationmellan uppgifter. Däremot kan framtida arbete göras för att automatiseranedbrytningen av seriella program från källkod. Slutsatsen är att dettakommunikationssystem är lämpligt för grovkorning parallellism, där kommunikationskostnadeninte påverkar lika mycket. Uppgiftsdupliceringen är bättreatt använda för finkorning parallellism eftersom kommunikation mellan kärnorundviks genom att göra extra beräkningar.
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Afonso, Tiago Emanuel Urze. "FPGA and multi-core embedded systems for video processing." Master's thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12678.

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Mestrado em Engenharia Electrónica e Telecomunicações<br>O presente trabalho apresenta técnicas de processamento digital de sinal, nomeadamente em processamento de vídeo, recorrendo a tecnologia FPGA. Consiste numa introdução teórica sobre tópicos tais como o papel da visão artificial nos dias de hoje, reconhecimento de imagem, e técnicas matemáticas de processamento e análise morfol ógica de imagem. Aborda o tema do papel das FPGAs na tecnologia actual, e as suas vantagens quando utilizadas no processamento digital de sinal. Finalmente e demonstrado e explicado o algoritmo implementado na FPGA para deteção de contornos no processamento de vídeo, concluindo com uma análise a nível da sua eficiência, e discussão de melhorias a fazer num possível trabalho futuro em termos de otimização de recursos utilizados e velocidade de processamento.<br>The present work presents techniques of digital signal processing, namely in video processing, using FPGA technology. It consists of a theoretical introduction about topics such as the role of artificial vision nowadays, image recognition and mathematical techniques of image processing and morphological analysis. It discusses the role of an FPGA in today's technology and its advantages when used in digital signal processing. Finally, it is demonstrated and explained the algorithm that was implemented in the FPGA for edge detection in video processing, concluding with an analysis in terms of efficiency, and discussion of improvements to do in a possible future work regarding the optimization of used resources and also of its processing speed.
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Books on the topic "Multi-core embedded system"

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Georgios, Kornaros, ed. Multi-core embedded systems. Taylor & Francis, 2010.

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Kornaros, Georgios. Multi-core embedded systems. Taylor & Francis, 2010.

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Mohammad, Baker. Embedded Memory Design for Multi-Core and Systems on Chip. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-8881-1.

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Kornaros, Georgios. Multi-Core Embedded Systems. CRC Press, 2010. http://dx.doi.org/10.1201/9781315218199.

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Kornaros, Georgios, ed. Multi-Core Embedded Systems. CRC Press, 2010. http://dx.doi.org/10.1201/9781439811627.

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Kornaros, Georgios. Multi-Core Embedded Systems. Taylor & Francis Group, 2018.

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Kornaros, Georgios. Multi-Core Embedded Systems. Taylor & Francis Group, 2018.

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Kornaros, Georgios. Multi-Core Embedded Systems. Taylor & Francis Group, 2018.

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Kornaros, Georgios. Multi-Core Embedded Systems. Taylor & Francis Group, 2018.

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Kornaros, Georgios. Multi-Core Embedded Systems. Taylor & Francis Group, 2019.

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Book chapters on the topic "Multi-core embedded system"

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Lee, Liang-Teh, Hung-Yuan Chang, and Wai-Min Luk. "An Adaptive Embedded Multi-core Real-Time System Scheduling." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-20975-8_29.

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Salehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.

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AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.
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Ranjbar, Behnaz, Alireza Ejlali, and Akash Kumar. "Fault-Tolerance- and Power-Aware Multi-core Mixed-Criticality System Design." In Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-38960-3_6.

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Hu, Congliang, Huaqing Wan, and Liang Li. "The Improved Parallel Ray Casting Algorithm in Embedded Multi-core DSP System." In Advances in Intelligent Systems and Computing. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-14680-1_4.

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Thillai Rani, M., R. Rajkumar, K. P. Sai Pradeep, M. Jaishree, and S. TamilSelvan. "Cache Coherence for Embedded Multi-core System Architectures: A Survey and Challenges." In IoT Based Control Networks and Intelligent Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-5845-8_49.

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Nikolaou, Panagiota, Zacharias Hadjilambrou, Panayiotis Englezakis, et al. "Evaluating System-Level Monitors and Knobs on Real Hardware." In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91962-1_8.

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Kriebel, Florian, Kuan-Hsun Chen, Semeen Rehman, Jörg Henkel, Jian-Jia Chen, and Muhammad Shafique. "Dependable Software Generation and Execution on Embedded Systems." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_6.

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AbstractFor generating and executing dependable software, the effects of hardware layer faults at the software layer have to be accurately analyzed and modeled. This requires relevant information from the hardware and software layers, as well as an in-depth analysis of how an application’s outputs are affected by errors, and quantifying the error masking and error propagation on the software layer. Based on this analysis, techniques for generating dependable software can be proposed, e.g., by different dependability-aware compiler-based software transformations or selective instruction protection. Beside functional aspects, timing also plays an important role, as oftentimes tasks have to be finished before a certain deadline to provide useful information, especially in real-time systems. Both aspects are jointly taken into account by the run-time system software which decides—with the help of offline and online-generated data—for multiple concurrently executing applications how to protect and when to execute which application task to optimize for dependability and timing correctness. This is achieved for example by selecting appropriate application versions and protection levels for single and multi-core systems—for example using redundant multithreading (RMT) in different modes—under tolerable performance overhead constraints.
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Sassi, Federico, Alessandro Bacchini, and Giuseppe Massari. "Beesper SmartBridge: A Real-World HARPA Application in the Low-End Embedded System Domain." In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91962-1_13.

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Portero, Antoni, Radim Vavrik, Martin Golasowski, et al. "Floreon+ Modules: A Real-World HARPA Application in the High-End HPC System Domain." In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91962-1_12.

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Huang, Xin, KenLi Li, and RenFa Li. "A Energy Efficient Scheduling Base on Dynamic Voltage and Frequency Scaling for Multi-core Embedded Real-Time System." In Algorithms and Architectures for Parallel Processing. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03095-6_14.

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Conference papers on the topic "Multi-core embedded system"

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Ayari, Rabeh, Imane Hafnaoui, Giovanni Beltrame, and Gabriela Nicolescu. "Schedulability-guided exploration of multi-core systems." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. ACM, 2016. http://dx.doi.org/10.1145/2990299.2990319.

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Kim, Hyoseung, and Ragunathan (Raj) Rajkumar. "Real-time cache management for multi-core virtualization." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. ACM, 2016. http://dx.doi.org/10.1145/2968478.2968480.

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Kurth, Andreas, Andreas Tretter, Pascal A. Hager, et al. "Mobile Ultrasound Imaging on Heterogeneous Multi-Core Platforms." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. ACM, 2016. http://dx.doi.org/10.1145/2993452.2993565.

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Ernst, Rolf. "Session details: Managing parallelism in multi-core systems." In ESWEEK'12: Eighth Embedded System Week. ACM, 2012. http://dx.doi.org/10.1145/3250268.

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Chen, Jing, Chung-Ping Young, Da-Wei Chang, et al. "Building Multi-kernel Embedded System on PAC Multi-core Platform." In 2010 10th International Conference on Quality Software (QSIC). IEEE, 2010. http://dx.doi.org/10.1109/qsic.2010.65.

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Chen, He, Liang Yin, and Guihua Peng. "Implementation of multi-core embedded system on compound guidance system." In 2011 International Conference on Electronics, Communications and Control (ICECC). IEEE, 2011. http://dx.doi.org/10.1109/icecc.2011.6066633.

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Abdel-Qader, Jareer, and Roger Walker. "Modeling Real-Time Multi-Core Embedded System Using UML." In 2009 Sixth International Conference on Information Technology: New Generations. IEEE, 2009. http://dx.doi.org/10.1109/itng.2009.244.

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Mohamed, Ahmed S. S., Ali A. El-Moursy, and Hossam A. H. Fahmy. "Real-Time Memory Controller for Embedded Multi-core System." In 2015 IEEE 17th International Conference on High-Performance Computing and Communications; 2015 IEEE 7th International Symposium on Cyberspace Safety and Security; and 2015 IEEE 12th International Conference on Embedded Software and Systems. IEEE, 2015. http://dx.doi.org/10.1109/hpcc-css-icess.2015.133.

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Mauroner, Fabian, and Marcel Baunach. "mosartMCU: Multi-core operating-system-aware real-time microcontroller." In 2018 7th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2018. http://dx.doi.org/10.1109/meco.2018.8406007.

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Naghashi, M., S. H. Mozafari, and S. Hessabi. "Heterogeneous redundancy to address performance and cost in multi-core SIMT." In ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK. ACM, 2017. http://dx.doi.org/10.1145/3125502.3125547.

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