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Dissertations / Theses on the topic 'Multi-core embedded system'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Zhang, Wei. "Design and Implementation of Multi-core Support for an Embedded Real-time Operating System for Space Applications." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174880.

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Nowadays, multi-core processors are widely used in embedded applications due to the advantages of higher performance and lower power consumption. However, the complexity of multi-core architectures makes it a considerably challenging task to extend a single-core version of a real-time operating system to support multi-core platform. This thesis documents the process of design and implementation of a multi-core version of RODOS - an embedded real-time operating system developed by German Aerospace Center and the University of Würzburg - on a dual-core platform. Two possible models are proposed:

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Li, Lin [Verfasser], Andreas [Akademischer Betreuer] Herkersdorf, Frank [Gutachter] Slomka, and Andreas [Gutachter] Herkersdorf. "A Traced-based Automated System Diagnosis and Software Debugging Methodology for Embedded Multi-core Systems / Lin Li ; Gutachter: Frank Slomka, Andreas Herkersdorf ; Betreuer: Andreas Herkersdorf." München : Universitätsbibliothek der TU München, 2019. http://d-nb.info/1193177618/34.

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Zabel, Martin. "Effiziente Mehrkernarchitektur für eingebettete Java-Bytecode-Prozessoren." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84156.

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Die Java-Plattform bietet viele Vorteile für die schnelle Entwicklung komplexer Software. Für die Ausführung des Java-Bytecodes auf eingebetteten Systemen eignen sich insbesondere Java-(Bytecode)-Prozessoren, die den Java-Bytecode als nativen Befehlssatz unterstützen. Die vorliegende Arbeit untersucht detailliert die Gestaltung einer Mehrkernarchitektur für Java-Prozessoren zur effizienten Nutzung der auf Thread-Ebene ohnehin vorhandenen Parallelität eines Java-Programms. Für die Funktionalitäts- und Leistungsbewertung eines Prototyps wird eine eigene Trace-Architektur eingesetzt. Es wird eine

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Grosic, Hasan, and Emir Hasanovic. "Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.

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The demand for computing power and performance in real-time embedded systems is continuously increasing since new customer requirements and more advanced features are appearing every day. To support these functionalities and handle them in a more efficient way, multi-core computing platforms are introduced. These platforms allow for parallel execution of tasks on multiple cores, which in addition to its benefits to the system's performance introduces a major problem regarding the timing predictability of the system. That problem is reflected in unpredictable inter-core interferences, which occ

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Åberg, Emil. "MINIMIZING INTER-CORE DATA-PROPAGATION DELAYS IN PARTITIONED MULTI-CORE REAL-TIME SYSTEMS USING SCHEDULING HEURISTICS." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-54616.

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In the field of embedded systems, computers embedded into machines ranging from microwaveovensto assembly lines impact the physical world. They do so under tight real-time constraintswith ever-increasing demand for computing power and performance. Development of higher speedprocessors have been hampered by diminishing returns on power consumption as clock frequency isfurther increased. For this reason, today, embedded processor development is instead moving towardfurther concurrency with multi-core processors being considered more and more every day. Withparallelism comes challenges, such as i

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Vidović, Tin, and Lamija Hasanagić. "TIGHTER INTER-CORE DELAYS IN MULTI-CORE EMBEDDED SYSTEMS UNDER PARTITIONED SCHEDULING." Thesis, Mälardalens högskola, Inbyggda system, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-48575.

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There exists an increasing demand for computing power and performance in real-time embedded systems, as new, more complex customer requirements and function-alities are appearing every day. In order to support these requirements and func-tionalities without breaking the power consumption wall, many embedded systems areswitching from traditional single-core hardware architectures to multi-core architec-tures. Multi-core architectures allow for parallel execution of tasks on the multiplecores. This introduces many benets from the perspective of achievable performance,but in turn introduces major

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Kerrison, Steven P. "Energy modelling of multi-threaded, multi-core software for embedded systems." Thesis, University of Bristol, 2015. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.682488.

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Efforts to reduce energy consumption are being made across all disciplines. ICT's contribution to global energy consumption and by-products such as C02 emissions continues to grow, making it an increasingly significant area in which improvements must be made. This thesis focuses on software as a means to reducing energy consumption. It presents methods for profiling and modelling a multi-threaded, multi-core embedded processor at the instruction set level, establishing links between the software and the energy consumed by the underlying hardware. A framework is presented that profiles the ener

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González-conde, pérez José Luis. "Analysis of task scheduling for multi-core embedded systems." Thesis, KTH, Maskinkonstruktion (Inst.), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-186330.

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This thesis performs a research on scheduling algorithms for parallel appli-cations. The main focus is their usage on multi-core embedded systems’ appli-cations. A parallel application can be described by a directed acyclic graph. A directed acyclic graph is a mathematical model that represents the parallel application as a set of nodes or tasks and a set of edges or communication messages between nodes.In this thesis scheduling is limited to the management of multiple cores on a multi-core platform for the execution of application tasks. Tasks are mapped onto the cores and their start times a

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Gonzales-Conde, Perez José Luis. "Analysis of task scheduling for multi-core embedded systems." Thesis, KTH, Maskinkonstruktion (Inst.), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-202548.

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This thesis performs a research on scheduling algorithms for parallel applications.The main focus is their usage on multi-core embedded systems’ applications.A parallel application can be described by a directed acyclic graph.A directed acyclic graph is a mathematical model that represents the parallelapplication as a set of nodes or tasks and a set of edges or communicationmessages between nodes.In this thesis scheduling is limited to the management of multiple coreson a multi-core platform for the execution of application tasks. Tasks aremapped onto the cores and their start times are determ

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Afonso, Tiago Emanuel Urze. "FPGA and multi-core embedded systems for video processing." Master's thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12678.

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Mestrado em Engenharia Electrónica e Telecomunicações<br>O presente trabalho apresenta técnicas de processamento digital de sinal, nomeadamente em processamento de vídeo, recorrendo a tecnologia FPGA. Consiste numa introdução teórica sobre tópicos tais como o papel da visão artificial nos dias de hoje, reconhecimento de imagem, e técnicas matemáticas de processamento e análise morfol ógica de imagem. Aborda o tema do papel das FPGAs na tecnologia actual, e as suas vantagens quando utilizadas no processamento digital de sinal. Finalmente e demonstrado e explicado o algoritmo implementad

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Paolieri, Marco. "A Multi-core processor for hard real-time systems." Doctoral thesis, Universitat Politècnica de Catalunya, 2011. http://hdl.handle.net/10803/51578.

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The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in current embedded processors. Multi-core processors represent a good design solution to cope with such higher performance requirements due to their better performance-per-watt ratio while maintaining the core design simple. Moreover, multi-cores also allow executing mixed-criticality level workloads composed of tasks with and without hard real-time requirements, maximizing the uti

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Fan, Ming. "Real-Time Scheduling of Embedded Applications on Multi-Core Platforms." FIU Digital Commons, 2014. http://digitalcommons.fiu.edu/etd/1243.

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For the past several decades, we have experienced the tremendous growth, in both scale and scope, of real-time embedded systems, thanks largely to the advances in IC technology. However, the traditional approach to get performance boost by increasing CPU frequency has been a way of past. Researchers from both industry and academia are turning their focus to multi-core architectures for continuous improvement of computing performance. In our research, we seek to develop efficient scheduling algorithms and analysis methods in the design of real-time embedded systems on multi-core platforms. Real

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Shekhar, Mayank. "ARCHITECTURE-AWARE HARD-REAL-TIME SCHEDULING ON MULTI-CORE ARCHITECTURES." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/971.

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The increasing dependency of man on machines have led to increase computational load on systems. The increasing computational load can be handled to some extent by scaling up processor frequencies. However, this approach has hit a frequency and power wall and the increasing awareness towards green computing discourages this solution. This leads us to use multi-core architectures. Due to the same reason, real-time systems are also migrating from single-core towards multi-core systems. While multi-core systems provide scalable high computational power, they also expose real-time systems to sever

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Iyer, Shankar Vanchesan. "REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35911.

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The increasing complexity of vehicular embedded systems has encouraged researchers and practitioners to adopt model-driven engineering in the development of these systems. In particular, several modelling languages have been introduced for representing the vehicular software architecture and its quality attributes. Current trend in the automotive domain is to shift from single-core architectures to multi-core ones in the attempt of providing the computational power required from the next generation of vehicles, particularly autonomous ones. On the one hand, multi-core architectures introduce n

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Kim, Hyoseung. "Towards Predictable Real-Time Performance on Multi-Core Platforms." Research Showcase @ CMU, 2016. http://repository.cmu.edu/dissertations/836.

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Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities to monitor and control operations in the physical environment. A key requirement of such systems is the need to provide predictable real-time performance: the timing correctness of the system should be analyzable at design time with a quantitative metric and guaranteed at runtime with high assurance. This requirement of predictability is particularly important for safety-critical domains such as automobiles, aerospace, defense, manufacturing and medical devices. The work in this dissertation foc

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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion.

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SECCHI, SIMONE. "Simulating complex multi-core computing systems: techniques and tools." Doctoral thesis, Università degli Studi di Cagliari, 2011. http://hdl.handle.net/11584/266327.

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Chen, Zhimin. "SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/51256.

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Nowadays, we use embedded electronic devices in almost every aspect of our daily lives. They represent our electronic identity; they store private information; they monitor health status; they do confidential communications, and so on. All these applications rely on cryptography and, therefore, present us a research objective: how to implement cryptography on embedded systems in a trustworthy and efficient manner. Implementing embedded cryptography faces two challenges - constrained resources and physical attacks. Due to low cost constraints and power budget constraints, embedded device

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Leung, Lap-Fai. "Designing high-performance and low-energy real-time embedded systems based on single-core and multi-cores structures /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LEUNG.

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Zaki, Youssef. "An Embedded Multi-Core Platform for Mixed-Criticality Systems : Study and Analysis of Virtualization Techniques." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-197306.

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The common availability of multiple processors in modern CPU devices and the need to reduce cost of embedded systems has created a drive for integrating functionalities from different parts of a system into a single Multi- Processor System-on-Chip (MPSoC) device. As a result, system resources are shared amongst the critical and non-critical components of the system, which results in a mixed-criticality system (MCS). An example of a MCS is to combine an airbag control unit with the infotainment system of a car, in such a case, both components must be certified unless an isolation mechanism that

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Guan, Nan. "New Techniques for Building Timing-Predictable Embedded Systems." Doctoral thesis, Uppsala universitet, Avdelningen för datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-209623.

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Embedded systems are becoming ubiquitous in our daily life. Due to close interaction with physical world, embedded systems are typically subject to timing constraints. At design time, it must be ensured that the run-time behaviors of such systems satisfy the pre-specified timing constraints under any circumstance. In this thesis, we develop techniques to address the timing analysis problems brought by the increasing complexity of underlying hardware and software on different levels of abstraction in embedded systems design. On the program level, we develop quantitative analysis techniques to p

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Kekec, Burak. "Effects Of Parallel Programming Design Patterns On The Performance Of Multi-core Processor Based Real Time Embedded Systems." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612101/index.pdf.

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Increasing usage of multi-core processors has led to their use in real time embedded systems (RTES). This entails high performance requirements which may not be easily met when software development follows traditional techniques long used for single processor systems. In this study, parallel programming design patterns especially developed and reported in the literature will be used to improve RTES implementations on multi-core systems. Specific performance parameters will be selected for assessment, and performance of traditionally developed software will be compared with that of software dev

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SHA, SHI. "The Thermal-Constrained Real-Time Systems Design on Multi-Core Platforms -- An Analytical Approach." FIU Digital Commons, 2018. https://digitalcommons.fiu.edu/etd/3713.

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Over the past decades, the shrinking transistor size enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps

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Cordes, Daniel Alexander [Verfasser], Peter [Akademischer Betreuer] Marwedel, and Albert [Gutachter] Cohen. "Automatic parallelization for embedded multi-core systems using high level cost models / Daniel Alexander Cordes. Betreuer: Peter Marwedel. Gutachter: Albert Cohen." Dortmund : Universitätsbibliothek Dortmund, 2013. http://d-nb.info/1104738082/34.

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Payami, Maryam. "Instruction prefetching techniques for ultra low-power multicore architectures." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amslaurea.unibo.it/12462/.

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As the gap between processor and memory speeds increases, memory latencies have become a critical bottleneck for computing performance. To reduce this bottleneck, designers have been working on techniques to hide these latencies. On the other hand, design of embedded processors typically targets low cost and low power consumption. Therefore, techniques which can satisfy these constraints are more desirable for embedded domains. While out-of-order execution, aggressive speculation, and complex branch prediction algorithms can help hide the memory access latency in high-performance systems, yet

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Paolillo, Antonio. "Optimisation of Performance Metrics of Embedded Hard Real-Time Systems using Software/Hardware Parallelism." Doctoral thesis, Universite Libre de Bruxelles, 2018. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/277427.

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Optimisation of Performance Metrics of Embedded Hard Real-Time Systems using Software/Hardware Parallelism. Nowadays, embedded systems are part of our daily lives.Some of these systems are called safetycritical and have strong requirements in terms of safety and reliability.Additionally, these systems must have a long autonomy, good performance and minimal costs.Finally, these systems must exhibit predictable behaviour and provide their results within firm deadlines.When these different constraints are combined in the requirement specifications of a modern product, classic design techniques ma

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Herber, Christian [Verfasser], Andreas [Akademischer Betreuer] [Gutachter] Herkersdorf, and Samarjit [Gutachter] Chakraborty. "Enablement of Multi-Core-Based Automotive Embedded Systems through I/O- and Network Virtualization / Christian Herber. Betreuer: Andreas Herkersdorf. Gutachter: Andreas Herkersdorf ; Samarjit Chakraborty." München : Universitätsbibliothek der TU München, 2016. http://d-nb.info/1111776482/34.

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Bin, Jingyi. "Controlling execution time variability using COTS for Safety-critical systems." Phd thesis, Université Paris Sud - Paris XI, 2014. http://tel.archives-ouvertes.fr/tel-01061936.

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While relying during the last decade on single-core Commercial Off-The-Shelf (COTS) architectures despite their inherent runtime variability, the safety critical industry is now considering a shift to multi-core COTS in order to match the increasing performance requirement. However, the shift to multi-core COTS worsens the runtime variability issue due to the contention on shared hardware resources. Standard techniques to handle this variability such as resource over-provisioning cannot be applied to multi-cores as additional safety margins will offset most if not all the multi-core performanc

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Lai, Yu-Hsun, and 賴昱勳. "The Performance Evaluation and Analysis of Embedded Multi-core System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/45822508555471527945.

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碩士<br>大同大學<br>資訊工程學系(所)<br>98<br>Recently years, as the on physical limitations, the current processor to enhance the core clock has been stuck. Therefore, multi-core technology has been introduced to embedded systems in order to improve performance and reduce power consumption. The current benchmarks are based on single-core system, it does not fully develop and evaluate parallel hardware architecture the advantages and performance. In this thesis proposes the use of multi-core architecture of parallel programming framework and library to modify six benchmarks: Integer Sort (IS), Conjugate Gr

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Lin, Jyun-Wei, and 林俊瑋. "Hardware-Assisted Performance/Energy Evaluation Tool for Multi-core Embedded System." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/90426414081342276052.

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碩士<br>國立交通大學<br>資訊科學與工程研究所<br>97<br>Effective performance and energy evaluation of embedded systems is one of the critical issues during design phase. However, conventional approaches suffer from difficulties to provide fast and accurate evaluation of the system, especially for those embedded systems using multi-core technology. In this thesis, we propose and realize a hardware-assisted performance and energy evaluation tool for a multi-core embedded system. Our approach provides hardware monitor for runtime programs, and uses these monitor information to estimate the system energy consumption

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Cai, Shang Syuan, and 蔡尚軒. "Design and Implementation of Wheeled Robots Based on Multi-Core Embedded System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/c32yn6.

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Chen, Jian-Ming, and 陳建銘. "Dynamic Task Scheduling Optimization for Multi-Core Embedded System Using Computational Intelligence." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/32729300751528652251.

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碩士<br>國立東華大學<br>電機工程學系<br>94<br>This thesis proposes an intelligent algorithm of task scheduling for heterogeneous multi-core processor system. The algorithm can help system to well utilize the computation ability of each processor. This algorithm can be embedded in operating system kernel. Once the algorithm was involved in kernel of multi-core system, the system will distribute the task to available processors according to each processor’s loading and the computation ability for current task, so as to meet the real-time requirement. Based on the two intelligent algorithms, Genetic Algorithm

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CHEN, ZONG-TING, and 陳宗霆. "The Implementation of Color Detection Algorithm on Multi-core DSP Based Embedded System." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/99176004996496526630.

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碩士<br>輔仁大學<br>電機工程學系碩士班<br>104<br>In this paper, we implement a color correction and a color detection algorithm on multi-core DSP based embedded system. We used LRMSR(Light Random Memory Sprays Retinex) for color correction before doing color detection. The detecting rate of color detection is improved by color correction. Our implementation utilizes both ARM and DSP simultaneously. ARM is used to control operating system and I/O, and DSP is used for color correction. Color correction and color detection can improve the performance by this architecture.

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陳薪中. "Evaluation of Performance and Energy Consumption of Multi-core Embedded System with Scratch-Pad Memor." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/78097536949969393055.

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Sun, Wei-Chen, and 孫瑋辰. "Integrate and Develop a Real-Time Driving Safety Assistance and Driver Status Monitoring System on a Multi-core Embedded Platform." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/dzfbe8.

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碩士<br>國立臺北科技大學<br>資訊工程系所<br>101<br>According to the statistic report of the UN World Health Organization, 1.2 million people die from traffic accidents worldwide and twenty million to fifty million people injured, resulting in loss of many lives and property. Traffic accident is expected to be the fifth cause of death in 2030. The purpose of this paper is to develop a safety driving assistant system based on handheld embedded devices with the aid of the computer vision technology. In recent years, handheld embedded devices are becoming popular and powerful, such as smart phones. We can place a

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Zabel, Martin. "Effiziente Mehrkernarchitektur für eingebettete Java-Bytecode-Prozessoren." Doctoral thesis, 2011. https://tud.qucosa.de/id/qucosa%3A24907.

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Die Java-Plattform bietet viele Vorteile für die schnelle Entwicklung komplexer Software. Für die Ausführung des Java-Bytecodes auf eingebetteten Systemen eignen sich insbesondere Java-(Bytecode)-Prozessoren, die den Java-Bytecode als nativen Befehlssatz unterstützen. Die vorliegende Arbeit untersucht detailliert die Gestaltung einer Mehrkernarchitektur für Java-Prozessoren zur effizienten Nutzung der auf Thread-Ebene ohnehin vorhandenen Parallelität eines Java-Programms. Für die Funktionalitäts- und Leistungsbewertung eines Prototyps wird eine eigene Trace-Architektur eingesetzt. Es wird eine

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Alzahrani, Ali Saeed. "Design of multi-core dataflow cryptprocessor." Thesis, 2018. https://dspace.library.uvic.ca//handle/1828/9972.

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Embedded multi-core systems are implemented as systems-on-chip that rely on packet store-and-forward networks-on-chip for communications. These systems do not use buses nor global clock. Instead routers are used to move data between the cores and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such systems is very much facilitated using dataflow concepts. In this work, we propose a methodology for implementing algorithms on dataflow platforms. The methodology can be applied to multi-threaded, multi-core platforms or a combination o

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Liao, Shun-Mao, and 廖舜茂. "Performance Evaluation of Image Engine on Multi-core Embedded Systems." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/07441739090845019086.

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碩士<br>南開科技大學<br>電子工程研究所<br>102<br>MATLAB is the commercial mathematical software developed by MathWorks. MATLAB has a complete and powerful library on matrix operations, so it is widely used in the imaging algorithms, communication studies or numerical analysis. However, when MATLAB code is used to implement the research of the algorithm, most of the MATLAB codes still need to be translated into Java, C, or machine languages, especially in the codes need to implement on a hardware device. Hence, the FPGA or C language is considered. The algorithm has better performance without distorting the p

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Liao, Han-chiang, and 廖翰強. "Real-time on-line Task Scheduling for Heterogeneous Multi-core Embedded Systems." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ya9ata.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>99<br>This paper explores the real-time scheduling problems for heterogeneous multi-core systems. With the precedence constraint consideration, we test the performance of heterogeneous dual-core systems under varying schedulers, protocols, preemption point and context switch overhead. In heterogeneous multi-core systems, we discuss the performance of system under varying dispatchers, migration cost and task structures. We also propose an efficient algorithm to reduce the number of preemption in heterogeneous multi-core systems.

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Luk, Wai-min, and 陸慧敏. "A DYNAMIC FEEDBACK SCHEDULING MECHANISM FOR EMBEDDED MULTI-CORE REAL-TIME SYSTEMS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/21338519027270310015.

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碩士<br>大同大學<br>資訊工程學系(所)<br>98<br>In recent years, because of the increasing popularity of multi-core systems, multi-core scheduling and parallel processing technology have been studied. Most of application software can also support multi-threading and multi-core platform. It can not achieve a satisfactory performance if only using single-core scheduling rules. It is important to design a practical multi-core scheduling for multi-core system, to improve performance of multi-core system effectively. The majority of well-known real-time operating scheduling algorithm is to use the setting of prio

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Lin, Ming Ham, and 林明翰. "Energy Efficient Workload-Aware DVS Scheduling for Multi-core Real-time Embedded Systems." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/79906963934612974983.

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碩士<br>國立交通大學<br>網路工程研究所<br>96<br>Memory is an important shared resource in a multi-core real-time embedded system. The memory contentions between cores will lengthen the total execution time due to waiting for memory requests being served. In this thesis, we focus on the tasks partition scheduling problem while considering memory contentions in multi-core real-time embedded systems. We propose an energy efficient scheduling mechanism with consideration to the memory workload of tasks, called WAS-DVS (workload-aware scheduling-dynamic voltage scaling), which is an improvement of an existing met

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Razaghi, Parisa. "Dynamic time management for improved accuracy and speed in host-compiled multi-core platform models." Thesis, 2014. http://hdl.handle.net/2152/25049.

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With increasing complexity and software content, modern embedded platforms employ a heterogeneous mix of multi-core processors along with hardware accelerators in order to provide high performance in limited power budgets. Due to complex interactions and highly dynamic behavior, static analysis of real-time performance and other constraints is challenging. As an alternative, full-system simulations have been widely accepted by designers. With traditional approaches being either slow or inaccurate, so-called host-compiled simulators have recently emerged as a solution for rapid evaluation of co

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Tsai, Chao-kai, and 蔡朝凱. "A SCHEDULING WITH DYNAMIC VOLTAGE SCALING MECHANISM FOR EMBEDDED MULTI-CORE REAL-TIME SYSTEMS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/25845227382047970977.

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碩士<br>大同大學<br>資訊工程學系(所)<br>98<br>With the advancement of technology, embedded systems have been widely used in portable devices. Portable embedded systems must have rather superior computing capability in order to meet real-time application demands. As the computation increases, so does the corresponding energy consumption. The energy consumption of portable embedded system is a very important issue due to limited battery capacity of the system. The working time of portable device can be prolonged if energy consumption of the system can be effectively reduced. Therefore it is very important fo

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Capalija, Davor. "Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture." Thesis, 2008. http://hdl.handle.net/1807/11134.

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We design the microarchitecture of the Multi-Level Computing Architecture (MLCA), focusing on its Control Processor (CP). The design of the microarchitecture of the CP faces us with both opportunities and challenges that stem from the coarse granularity of the tasks and the large number of inputs and outputs for each task instruction. Thus, we explore changes to standard superscalar microarchitectural techniques. We design the entire CP microarchitecture and implement it on an FPGA using SystemVerilog. We synthesize and evaluate the MLCA system based on a 4-processor shared-memory multiprocess

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Wang, Bo-Hsuan, and 王柏軒. "Synchronization-Aware Dynamic Thread Scheduling for Improving Performance and Saving Energy in Multi-Core Embedded Systems." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/37827013294031310996.

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碩士<br>國立中正大學<br>資訊工程研究所<br>100<br>Nowadays, Chip Multi-Processors (CMP) are being widely used in embedded sys- tems because they provide superior performance via parallel computing. However, they also incur a significantly large power consumption. To solve this issue, de- signers of embedded operating system must provide an efficient thread scheduling algorithm, which not only maximizes the system performance, but also minimizes the energy consumption. Further, if the scheduler makes decisions without considering the precedence relationships among threads, the decisions could conflict with the

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Serra, João Filipe Marques. "Multi-criticality Hypervisor for Automotive Domain." Master's thesis, 2014. http://hdl.handle.net/10316/40419.

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Dissertação de Mestrado Integrado em Engenharia Electrotécnica e de Computadores apresentada à Faculdade de Ciências e Tecnologia da Universidade de Coimbra<br>xLuna is a real-time kernel technology that enables concurrent mixed-criticality applications running simultaneously on the same hardware platform, bridging a safety critical application, hard-real-time task set and certifiable real-time operating system alongside a feature rich, nonsecure, non-critical, non-real-time general purpose operating system. The xLuna program, an hypervisor originally developed by Critical Software for spac

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Unnikrishnan, Deepak C. "Application Specific Customization and Scalability of Soft Multiprocessors." 2009. https://scholarworks.umass.edu/theses/274.

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Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-

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