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Journal articles on the topic 'Multi-core embedded system'

Author: Grafiati

Published: 4 June 2025

Last updated: 23 June 2025

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1

Hussain, Tassadaq, Amna Haider, Adrian Cristal, and Eduard Ayguadé. "EMVS: Embedded Multi Vector-core System." Journal of Systems Architecture 87 (June 2018): 12–22. http://dx.doi.org/10.1016/j.sysarc.2018.04.002.

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2

Danese, G., M. Giachero, F. Leporati, and N. Nazzicari. "An embedded multi-core biometric identification system." Microprocessors and Microsystems 35, no. 5 (2011): 510–21. http://dx.doi.org/10.1016/j.micpro.2011.03.003.

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3

Chen, Haorui. "Optimization Methods of Multi-Core Embedded System." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 153–62. http://dx.doi.org/10.54097/hset.v71i.12686.

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With the development of the Internet of everything technology, embedded system has become one of the most common computing systems. Embedded system has high portability, but there are often stronger limitations in energy consumption, real-time and so on. In this work, have improved some traditional optimization algorithms, and finally get a task scheduling sequence, which can reduce the total execution time and cost of the task. Firstly, the multi-module division is used to divide multiple tasks into different modules, improve the classical Kernighan-Lin (KL) algorithm and clustering algorithm implement this process. Second, this paper invokes a series of algorithms to calculate the priority value of the task. Finally, this paper call two multi-core scheduling algorithms to schedule the tasks within each module to the Central Processing Unit (CPU) in the module. The proposed algorithm is implemented in this paper. With directed acyclic graph as input, the improvement effect of the algorithm and the direct advantages and disadvantages of different algorithms are evaluated with different task quantity.

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Madsen, Jan, Michael R. Hansen, Kristian S. Knudsen, Jens E. Nielsen, and Aske W. Brekling. "System-level Verification of Multi-Core Embedded Systems using Timed-Automata." IFAC Proceedings Volumes 41, no. 2 (2008): 9302–7. http://dx.doi.org/10.3182/20080706-5-kr-1001.01572.

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Castells-Rufas, David, Eduard Fernandez-Alonso, and Jordi Carrabina. "Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems." International Journal of Reconfigurable Computing 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/736347.

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Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.

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Yuan, Ningze, and Hao Meng. "Software architecture and implementation based on multi-core digital signal processors." Journal of Physics: Conference Series 2797, no. 1 (2024): 012053. http://dx.doi.org/10.1088/1742-6596/2797/1/012053.

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Abstract Embedded detection systems are a critical research topic in intelligent monitoring equipment. In response to the current challenges in balancing real-time performance, accuracy, and stability in embedded hardware detection systems, this paper proposes a software architecture system based on multi-core digital signal processing (DSP), incorporating the image detection Canny algorithm into this system. Initially, the paper discusses the selection criteria for multi-core DSPs and then introduces a multi-core self-check function that can effectively ensure system stability. It also proposes a multi-core communication handshake protocol that significantly enhances the system’s real-time performance. Furthermore, an improved multi-core master-slave architecture is presented, which includes the addition of a timer to the conventional architecture, providing a temporal guarantee for system operation. Finally, the Canny algorithm is selected and applied to this software architecture, with parallel acceleration processing applied to parts of the algorithm. Operational tests have demonstrated that the system maintains stable internal data flow, with its detection accuracy and speed meeting the set requirements.

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Pahikkala, Tapio, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, and Tapio Salakoski. "Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 3, no. 2 (2012): 73–91. http://dx.doi.org/10.4018/jertcs.2012040104.

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The authors introduce a machine learning approach based on parallel online regularized least-squares learning algorithm for parallel embedded hardware platforms. The system is suitable for use in real-time adaptive systems. Firstly, the system can learn in online fashion, a property required in real-life applications of embedded machine learning systems. Secondly, to guarantee real-time response in embedded multi-core computer architectures, the learning system is parallelized and able to operate with a limited amount of computational and memory resources. Thirdly, the system can predict several labels simultaneously. The authors evaluate the performance of the algorithm from three different perspectives. The prediction performance is evaluated on a hand-written digit recognition task. The computational speed is measured from 1 thread to 4 threads, in a quad-core platform. As a promising unconventional multi-core architecture, Network-on-Chip platform is studied for the algorithm. The authors construct a NoC consisting of a 4x4 mesh. The machine learning algorithm is implemented in this platform with up to 16 threads. It is shown that the memory consumption and cache efficiency can be considerably improved by optimizing the cache behavior of the system. The authors’ results provide a guideline for designing future embedded multi-core machine learning devices.

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8

Huang, Shujuan, Yi'an Zhu, Bailin Liu, and Feng Xiao. "Research on Three Dimensional Scheduling Model for Embedded Multi-Core System." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 36, no. 5 (2018): 1020–25. http://dx.doi.org/10.1051/jnwpu/20183651020.

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This paper proposes a new three-dimensional scheduling model which can divide the tasks into harmonic tasks and non-harmonic tasks for the high demands of embedded mucticne plactorim. According to the characteristic parameters of the tasks and make the value of the rectangular area as the attribute of the execution region which is divided into executive region, interference region and free region with the characteristic of the area. By using these attributes of the different region, the tasks are allocated to different cores. Experimental results show that the proposed method is more fully optimizing the system utilization and throughput than PEDF.

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Dong, Shichao, Shukun Yao, and Lijin Kang. "Underwater acoustic beacon detection device based on Embedded System." Journal of Physics: Conference Series 2528, no. 1 (2023): 012033. http://dx.doi.org/10.1088/1742-6596/2528/1/012033.

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Abstract Based on the current situation of large volume and single detection function of the underwater acoustic beacon detection device, combined with the requirements of multi-parameter detection of underwater acoustic beacon function and performance, an embedded underwater acoustic beacon multi-parameter detection device is developed. The detection device uses ARM as the core processor, carries Linux embedded system, and establishes QT graphical user interface. The detection device can realize the acoustic signal of underwater acoustic beacon Frequency, pulse width, period, sound source level, spectrum, and other multi-parameter detection and graphical display of the test results.

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Gou, Mingrui, Bangji Wang, and Xilin Zhang. "Development of Multi-Motor Servo Control System Based on Heterogeneous Embedded Platforms." Electronics 13, no. 15 (2024): 2957. http://dx.doi.org/10.3390/electronics13152957.

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Multi-motor servo systems are widely used in industrial control. However, the single-core microprocessor architecture based on the microcontroller unit (MCU) and digital signal processor (DSP) is not well suited for high-performance multi-motor servo systems due to the inherent limitations in computing performance and serial execution of code. The bus-based distributed architecture formed by interconnecting multiple unit controllers increases system communication complexity, reduces system integration, and incurs additional hardware and software costs. Field programmable gate array (FPGA) possesses the characteristics of high real-time performance, parallel processing, and modularity. A single FPGA can integrate multiple motor servo controllers. This research uses MCU + FPGA as the core to realize high-precision multi-axis real-time control, combining the powerful performance of the MCU processor and the high-speed parallelism of FPGA. The MCU serves as the central processor and facilitates data interaction with the host computer through the controller area network (CAN). After data parsing and efficient computation, MCU communicates with the FPGA through flexible static memory controller (FSMC). A motor servo controller intellectual property (IP) core is designed and packaged for easy reuse within the FPGA. A 38-axis micro direct current (DC) motor control system is constructed to test the performance of the IP core and the heterogeneous embedded platforms. The experimental results show that the designed IP core exhibits robust functionality and scalability. The system exhibits high real-time performance and reliability.

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Rinku, Dhruva R., and M. AshaRani. "Reinforcement learning based multi core scheduling (RLBMCS) for real time systems." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1805. http://dx.doi.org/10.11591/ijece.v10i2.pp1805-1813.

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Embedded systems with multi core processors are increasingly popular because of the diversity of applications that can be run on it. In this work, a reinforcement learning based scheduling method is proposed to handle the real time tasks in multi core systems with effective CPU usage and lower response time. The priority of the tasks is varied dynamically to ensure fairness with reinforcement learning based priority assignment and Multi Core MultiLevel Feedback queue (MCMLFQ) to manage the task execution in multi core system.

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Dhruva, R. Rinku, and AshaRani M. "Reinforcement learning based multi core scheduling (RLBMCS) for real time systems." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1805–13. https://doi.org/10.11591/ijece.v10i2.pp1805-1813.

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Embedded systems with multi core processors are increasingly popular because of the diversity of applications that can be run on it. In this work, a reinforcement learning based scheduling method is proposed to handle the real time tasks in multi core systems with effective CPU usage and lower response time. The priority of the tasks is varied dynamically to ensure fairness with reinforcement learning based priority assignment and Multi Core MultiLevel Feedback queue (MCMLFQ) to manage the task execution in multi core system

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13

XIA, BINGBING, FEI QIAO, ZIDONG DU, DI ZHU, and HUAZHONG YANG. "A "NEAR-THE-BEST" SYSTEM-LEVEL DESIGN METHODOLOGY OF MULTI-CORE H.264 VIDEO DECODER BASED ON THE PARALLELIZED MULTI-CORE SIMULATOR." Journal of Circuits, Systems and Computers 21, no. 07 (2012): 1250058. http://dx.doi.org/10.1142/s0218126612500582.

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H.264 video decoder is a good choice for embedded video processing applications because of its higher compression ratio than MPEG2, although it has higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization capability, and can be used to fit well with the requirements for such video processing algorithms. To simulate and evaluate the performance of these multi-core systems effectively, a design flow at the system level is developed, at the higher level, the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is used for such transaction-level simulation, and at the lower level, a multi-core simulator based on the extension of the SimpleScalar 3.0 ToolSet is developed for the cycle-accurate level simulation. Compared with other high-level simulation methods, ours has the ability to realize the true-parallelization simulation. What is more, experiments show that such simulation methodology can effectively simulate these complex multi-core applications in a short time to get the appropriate core number and the task allocation strategy (much less than RTL-level simulation) and the results can get at less than 15% deviated from the ideal ones calculated based on Amadal's Law, so the parallelization strategy obtained from such simulation is the best one that can be further applied for the RTL-level design of the final multi-core system.

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Bui, Phuc, Minh Le, Binh Hoang, Nguyen Ngoc, and Huong Pham. "Data Partitioning and Asynchronous Processing to Improve the Embedded Software Performance on Multicore Processors." Informatics and Automation 21, no. 2 (2022): 243–74. http://dx.doi.org/10.15622/ia.21.2.2.

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Nowadays, ensuring information security is extremely inevitable and urgent. We are also witnessing the strong development of embedded systems, IoT. As a result, research to ensure information security for embedded software is being focused. However, studies on optimizing embedded software on multi-core processors to ensure information security and increase the performance of embedded software have not received much attention. The paper proposes and develops the embedded software performance improvement method on multi-core processors based on data partitioning and asynchronous processing. Data are used globally to be retrieved by any threads. The data are divided into different partitions, and the program is also installed according to the multi-threaded model. Each thread handles a partition of the divided data. The size of each data portion is proportional to the processing speed and the cache size of the core in the multi-core processor. Threads run in parallel and do not need synchronization, but it is necessary to share a general global variable to check the executing status of the system. Our research on embedded software is based on data security, so we have tested and assessed the method with several block ciphers like AES, DES, etc., on Raspberry PI3. The average performance improvement rate achieved was 59.09%.

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15

Nurmi, Jari. "International Symposium on System-on-Chip 2010." International Journal of Embedded and Real-Time Communication Systems 2, no. 4 (2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.

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International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks.

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Rivera, J. Germán. "HiRTOS: A Multi-core RTOS Written in SPARK Ada." ACM SIGAda Ada Letters 44, no. 2 (2025): 89–92. https://doi.org/10.1145/3742939.3742959.

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This paper describes the design of HiRTOS (High- Integrity RTOS), a simple real-time operating system kernel and separation kernel written in SPARK Ada. HiRTOS targets safety-critical and security-sensitive embedded software applications that run in multi-core microcontrollers.

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17

Liu, Xiaojian, Shuo Liu, and Hao Lv. "A Dynamic Reconfiguration Scheme for Embedded System Based on Multi-core DSP." Journal of Physics: Conference Series 1802, no. 4 (2021): 042099. http://dx.doi.org/10.1088/1742-6596/1802/4/042099.

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18

Jang, Suyeon, Hyun Woo Oh, Young Hyun Yoon, Dong Hyun Hwang, Won Sik Jeong, and Seung Eun Lee. "A Multi-Core Controller for an Embedded AI System Supporting Parallel Recognition." Micromachines 12, no. 8 (2021): 852. http://dx.doi.org/10.3390/mi12080852.

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Recent advances in artificial intelligence (AI) technology encourage the adoption of AI systems for various applications. In most deployments, AI-based computing systems adopt the architecture in which the central server processes most of the data. This characteristic makes the system use a high amount of network bandwidth and can cause security issues. In order to overcome these issues, a new AI model called federated learning was presented. Federated learning adopts an architecture in which the clients take care of data training and transmit only the trained result to the central server. As the data training from the client abstracts and reduces the original data, the system operates with reduced network resources and reinforced data security. A system with federated learning supports a variety of client systems. To build an AI system with resource-limited client systems, composing the client system with multiple embedded AI processors is valid. For realizing the system with this architecture, introducing a controller to arbitrate and utilize the AI processors becomes a stringent requirement. In this paper, we propose an embedded AI system for federated learning that can be composed flexibly with the AI core depending on the application. In order to realize the proposed system, we designed a controller for multiple AI cores and implemented it on a field-programmable gate array (FPGA). The operation of the designed controller was verified through image and speech applications, and the performance was verified through a simulator.

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Yang, Xu, Deyuan Guo, Hu He, et al. "Parallel Programming Environment Designed for a Real-Time Embedded Multi-Core System." Advanced Science, Engineering and Medicine 5, no. 5 (2013): 500–505. http://dx.doi.org/10.1166/asem.2013.1300.

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Nie, Yang, Zhenhuan Ma, and Lili Jing. "Research on the Design of Multi-Core Embedded System Based on Microblaze." International Journal of Control and Automation 8, no. 12 (2015): 425–34. http://dx.doi.org/10.14257/ijca.2015.8.12.39.

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Deng, Yao Hua, Gui Xiong Liu, Wei Han, Zi Wei Fang, Li Ming Wu, and Qing Fu Liao. "Research on Multi-Core Collaborative Computing for FWP Image Processing Algorithm by FPGA." Advanced Materials Research 230-232 (May 2011): 1340–44. http://dx.doi.org/10.4028/www.scientific.net/amr.230-232.1340.

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On the basis of analysis of research on embedded soft hardware collaborative design method, image processing SOPC collaborative design principle is elaborated, relation between complicated algorithm time and soft hardware implementation and the implementation method to accelerate algorithm by multi-processor and multi-core is studied, thus the logical relationship between equipment IP core on the chip with Fast Simplex Link(FSL) bus and bus bridge, connecting conditions and application flow is organized. Finally, design SOPC, for which, multi-core and multi-processor collaborative work with the core of PowerPC 405 processor by taking flexible workpiece path (FWP) image as an example. The test manifests that the computation speed of SOPC designed in this passage is higher 10 times than that of common single-core SOPC in terms of image processing computing, effectively solving the problem of slow speed for computing image preprocessing by software in the embedded system.

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Sha, Edwin H. M., Mingrui Xu, Shouzhen Gu, and Qingfeng Zhuge. "Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system." Journal of Systems Architecture 117 (August 2021): 102145. http://dx.doi.org/10.1016/j.sysarc.2021.102145.

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Hyodo, Kazuhito, Hirokazu Noborisaka, and Takashi Yada. "Development of Mechatronics Teaching Materials for Embedded System Engineer Education." Journal of Robotics and Mechatronics 23, no. 5 (2011): 611–17. http://dx.doi.org/10.20965/jrm.2011.p0611.

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We have developed a learning environment for embedded system design. The learning environment consists of a multi-purpose controller and terminal devices. The controller consists of main processor (arm) and a multi-core microprocessor (Propeller). The main processor provides the software development environment. The Propeller chip has eight 32-bit processors and can perform simultaneous tasks for multiple users. In addition, the Propeller chip provides a reconfigurable peripheral module. This feature is very useful for the development of educational materials. Teachers can develop various educational materials with this control module.

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Salamy, Hassan, and Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.

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Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

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Qu, Bo, and Zhao Zhi Wu. "Design of ARM Based Embedded Operating System Micro Kernel." Applied Mechanics and Materials 347-350 (August 2013): 1799–803. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1799.

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This paper describes the design and implementation of an ARM based embedded operating system micro kernel developed on Linux platform with GNU tool chain in technical details, including the three-layer architecture of the kernel (boot layer, core layer and task layer), multi-task schedule (priority for real-time and round-robin for time-sharing), IRQ handler, SWI handler, system calls, and inter-task communication based on which the micro-kernel architecture is constructed. On the foundation of this micro kernel, more components essential to a practical operating system, such as file system and TCP/IP processing, can be added in order to form a real and practical multi-task micro-kernel embedded operating system.

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Zhao, Zhikang, Chuankang Wei, and Rentao Zhao. "Turbine bearing fault diagnosis based on embedded system." Journal of Physics: Conference Series 2787, no. 1 (2024): 012034. http://dx.doi.org/10.1088/1742-6596/2787/1/012034.

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Abstract Failure of the main components of the transmission mechanism of large machinery and equipment usually uses sensors to collect real-time vibration or audio information, followed by data processing on the computer to analyze whether the equipment is operating normally. In this paper, a multi-core embedded fault diagnosis platform based on ARM and DSP is designed. It is small in size. It can independently set the signal types, ranges, and filter parameters of multiple acquisition channels, and synchronously set high-precision acquisition and storage of voltage signals output from various sensors. The DSP adopts the fast Fourier algorithm to analyze the multi-channel sampling data in real time and extracts the fault characteristics through the analysis of envelope demodulation. The operation results show that the system can meet the routine online fault diagnosis of mechanical equipment transmission mechanism, and the fault analysis and diagnosis can reach 95% accuracy within one minute, with high real-time accuracy.

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Jing, Wang, and Zhang Shuangyan. "Design of sports course management system based on multi-core embedded system and motion capture." Microprocessors and Microsystems 82 (April 2021): 103924. http://dx.doi.org/10.1016/j.micpro.2021.103924.

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28

Jia, Long, Gang Li, Meili Lu, Xile Wei, and Guosheng Yi. "Efficient Distributed Mapping-Based Computation for Convolutional Neural Networks in Multi-Core Embedded Parallel Environment." Electronics 12, no. 18 (2023): 3747. http://dx.doi.org/10.3390/electronics12183747.

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Embedded systems are the best solution to achieve high-performance edge terminal computing tasks. With the rapid increase in the amount of data generated by edge devices, it is imperative to implement intelligent algorithms with large amounts of data and computation on embedded terminal systems. In this paper, a novel multi-core ARM-based embedded hardware platform with a three-dimensional mesh structure was first established to support the decentralized algorithms. To deploy deep convolutional neural networks (CNNs) in this embedded parallel environment, a distributed mapping mechanism was proposed to efficiently decentralize computation tasks in the form of a multi-branch assembly line. In addition, a dimensionality reduction initialization method was also utilized to successfully resolve the conflict between the storage requirement of computation tasks and the limited physical memories. LeNet-5 networks with different sizes were optimized and implemented in the embedded platform to verify the performance of our proposed strategies. The results showed that memory usage can be controlled within the usable range through dimensionality reduction. The down-sampling layer as the base point of the mapping for the inter-layer segmentation achieved the optimal operation in lateral dispersion with a reduction of around 10% in the running time compared with the other layers. Further, the computing speed for a network with an input size of 105 × 105 in the multi-core parallel environment is nearly 20 times faster than that in a single-core system. This paper provided a feasible strategy for edge deployments of artificial intelligent algorithms on multi-core embedded devices.

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Zhu, Gui Xin. "Based on Embedded Distributed Control System of the Poultry House Environment." Advanced Materials Research 926-930 (May 2014): 1222–25. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.1222.

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Poultry breeding environment factors such as temperature and air humidity directly affect poultry production performance for large-scale poultry farms in the demand for environmental monitoring, research and application of CAN bus technology to build a distributed multi-variable environmental monitoring system, which an embedded core from the monitoring center and the PIC microcontroller as the core component of intelligent monitoring terminal, control center real-time monitoring of collection, analysis and processing of environmental information collected from the terminal, the control requirements based on user input, combined with the results of data processing, to the terminal sends control parameters, and breeding farms to monitor more than one poultry house.

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Ruan, Yue, Ying Tang, and Wen Ji Yao. "Design and Implementation of a Single Chip Multi-Waveform Signal Generator Based on SOPC Design Methodology." Advanced Materials Research 482-484 (February 2012): 550–54. http://dx.doi.org/10.4028/www.scientific.net/amr.482-484.550.

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This work presents a highly integrated multi-functional, multi-waveform signal generator which can generate various waveforms, with digital controller inside to adapt embedded and low power applications. The proposed system uses Nios II, a reconfigurable, programmable and optimizable soft-core embedded CPU together with modern EDA tools to accomplish system HW/SW co-design and implementation. Utilizing characteristics of Nios II, we put together core and peripheral logical units that system needs and implant them into a single FPGA chip, then uses the Avalon bus to connect peripheral modules (such as function switch buttons and 7-segment LED display units) to Nios II's Avalon bus main port (instruction and data control port). The realized system is flexible to reduce, extend, with low power consumption, and has System on Programmable Chip (SOPC) function which means the system’s software and hardware is online programmable.

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Choi, Jin-Yong, and Jae-Heung Lee. "An Improving Method of Android Boot Speed in Multi-core based Embedded System." Journal of IKEEE 17, no. 4 (2013): 564–69. http://dx.doi.org/10.7471/ikeee.2013.17.4.564.

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Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.

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Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.

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Salamy, Hassan. "Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip." Journal of Circuits, Systems and Computers 29, no. 09 (2019): 2050135. http://dx.doi.org/10.1142/s0218126620501352.

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Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.

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Mahamud, N. H., Z. Zainal Abidin, H. F. Mohd Zaki, et al. "Software Optimization of Vision-Based Around View Monitoring System on Embedded Platform." Journal of the Society of Automotive Engineers Malaysia 4, no. 1 (2020): 73–81. http://dx.doi.org/10.56381/jsaem.v4i1.52.

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   Image processing algorithm requires high computational power. Optimizing the algorithm to be run on an embedded platform is very critical as the platform provides limited computational resources. This research focused on optimizing and implementing a vision-based Around View Monitoring (AVM) system running on two embedded boards of Cortex-A7 quad and Cortex-A15 quad-core, and desktop platform of Intel i7 core. This paper presented a study on several techniques of software optimization that is removing code redundancy and multi-threading. The two methods improve the total processing time of the AVM system by 45% on ARM Cortex-A15 and 47% on ARM Cortex-A7.  

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Zhao, Huatao, Xiao Luo, Chen Zhu, Takahiro Watanabe, and Tianbo Zhu. "Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems." Modern Physics Letters B 31, no. 19-21 (2017): 1740067. http://dx.doi.org/10.1142/s021798491740067x.

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In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache resource demands as the cache allocation bases, so that we can optimally configure the cache hierarchy to meet the runtime demand. The BACH was implemented on the GEM5 simulator. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead.

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Ma, Hong Rui, Jian Xian Cai, and Rui Hong Yu. "Embedded Machine Vision System Design Based on Davinci DM355." Applied Mechanics and Materials 300-301 (February 2013): 729–34. http://dx.doi.org/10.4028/www.scientific.net/amm.300-301.729.

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Most existing machine vision processing system is 8-bit or 16-bit processor control system, complex algorithms and multi-tasking of the vision system have been severely constrained. DaVinci DM355 integrated ARM926 RISC processor core and specialized image processor is a programmable DMSoC development platform with digital multimedia codecs, high integration, low-power consumption. The machine vision system based on DaVinci DM355 development goal is to establish a low-power hardware development board based on the DaVinci DM355, transplant Linux operating system based on the hardware board and develop corresponding driver.This will provide the basis for the realization of complex algorithm and multitasking system for machine vision system.

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Li, Yixiao, Yutaka Matsubara, Hiroaki Takada, Kenji Suzuki, and Hideaki Murata. "A Performance Evaluation of Embedded Multi-core Mixed-criticality System Based on PREEMPT_RT Linux." Journal of Information Processing 31 (2023): 78–87. http://dx.doi.org/10.2197/ipsjjip.31.78.

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Shing-Tai, Pan, Chen Ching-Fa, and Tseng Wen-Sin. "Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core." International Journal of Reconfigurable and Embedded Systems 9, no. 2 (2020): 109–15. https://doi.org/10.11591/ijres.v9.i2.pp109-115.

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The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.

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Pan, Shing-Tai, Ching-Fa Chen, and Wen-Sin Tseng. "Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (2020): 109. http://dx.doi.org/10.11591/ijres.v9.i2.pp109-115.

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The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.

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Feng, Shuai, Li Hui Jiang, Xing Long Xiong, and Zi Bo Zhuang. "Achievement of the Novel Lidar Visibility Measurement System." Advanced Materials Research 479-481 (February 2012): 2525–28. http://dx.doi.org/10.4028/www.scientific.net/amr.479-481.2525.

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Atmospheric visibility is close to the transportation safety. In order to get accurate atmospheric visibility, according to atmosphere backscattering theory, a novel visibility measurement system is designed. The system adopts many modular devices such as semiconductor laser, silicon avalanche photodiode detector, multi channel photon counting card, embedded computer and so on. Where embedded computer is the core of the system, to realize system timing control, visibility inversion and information display. Finally, the objective and convenient measurement of atmospheric horizontal visibility and slant visibility are achieved. Outfield comparison experiments show that in low visibility weather conditions, the system obtains high measurement accuracy, which has high practical value and wonderful development prospect.

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Li, Zhi Yong, Zhen Liang Ye, and Chen Tao Liu. "Parallel Programming Methods Based on the Multi-Core DSP TMS320C6670." Applied Mechanics and Materials 198-199 (September 2012): 1487–92. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1487.

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While the frame rate is higher and the image size is larger, sequence images processing is harder. Good real-time can be ensured by the multi-core DSP in the embedded image processing system. TMS320C6670 which is the multi-core DSP designed by TI corporation is selected as study object. Based on hardware characteristics analyzed, the Data Flow model is adopted as the multi-core processing model. Two data processing subtasks assigning methods are analyzed by comparing their advantages and disadvantages on the system idle time and memory requirements. The data processing subtask assigning flow is design for a serial sequence images processing example. An inter-core data transfer flow design idea is put forward. Using methods and occasion of two kinds of data buffer establishing techniques is studied and defined. An inter-core notification flow design idea is put forward. Using methods and occasion of three notification methods based on the interrupt controller and the Semaphore2 module is studied and defined.

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Cao, Haotian, and Uwe Meyer-Baese. "XML-Based Automatic NIOS II Multi-Processor System Generation for Intel FPGAs." Electronics 11, no. 18 (2022): 2840. http://dx.doi.org/10.3390/electronics11182840.

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Many embedded systems are introducing processing units to accelerate the processing speed of tasks, such as for multi-media applications. The units are mostly customized designs. Another method of designing multi-unit systems is using pre-defined standard intellectual properties. However, the procedure of arranging IP cores in a system and maintaining a high performance as well are the remaining challenges. Implementing softcore processors on field-programmable gate arrays (FPGAs) is a relatively fast and inexpensive choice to design and validate a desired system. This paper describes the rapid prototyping of hardware/software co-design based on FPGAs. A novel system generator to effortlessly design a multiple NIOS II soft-processor core systems is also purposed. The NIOS II CPU is a configurable RISC processor designed by Altera/Intel and can be trimmed to complete specific tasks. The error-prone and time-consuming process of designing an IP block-based system is improved by the new novel system generator. The detail of the implementation of such system is discussed. To test the performance of a multi-NIOS II system, a parallel application is executed on 1-, 2-, 5-, and 10-core NIOS II systems separately. Test results prove the feasibility of the proposed methodology (for an FIR filter, a dual-core system is 29% faster than a single-core system; a 5-core system is 28% faster than the dual-core system).

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Su, Te-Feng, Chih-Hsueh Duan, Shu-Fan Wang, Yu-Tzu Lee, and Shang-Hong Lai. "Automatic Facial Expression Exaggeration System with Parallelized Implementation on a Multi-Core Embedded Computing Platform." Journal of Signal Processing Systems 75, no. 2 (2013): 155–68. http://dx.doi.org/10.1007/s11265-013-0751-5.

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Aradhya, Sumalatha, and N. K. Srinath Dr. "Intrinsic Compilation Model to enhance Performance of real time application in embedded multi core system." International Journal of Engineering and Technology 10, no. 3 (2018): 854–64. http://dx.doi.org/10.21817/ijet/2018/v10i3/181003098.

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Gopadi, Mr Harish Kumar, E Samanvitha, G Deepthi, and G sahithi. "VEHICLE ANTI-THEFT SECURITY SYSTEM WITH IGNITION LOCKING USING EMBEDDED SYSTEM." Industrial Engineering Journal 54, no. 01 (2024): 70–76. https://doi.org/10.36893/iej.2024.v54i1.010.

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The Vehicle Anti-Theft Security System is an advanced embedded solution designed to prevent unauthorized access and safeguard vehicles. This system integrates multiple technologies, including GSM communication, fingerprint authentication, and a password keypad, to provide a robust, multi-layered security framework. At its core, the system is powered by an Arduino microcontroller, which interfaces with various components: a fingerprint sensor for biometric verification, a password keypad for additional security, an LCD display for user interaction and status updates, and a GSM module for real-time notifications. A DC motor simulates the vehicle’s ignition system, locking or unlocking based on successful authentication. To access the vehicle, users must authenticate their identity via fingerprint scanning or password entry. In the event of unauthorized attempts, the system triggers an alarm and sends an SMS alert to the owner, ensuring prompt action. The LCD provides clear feedback during the authentication process, enhancing the user experience. Additionally, the GSMmodule enables remote monitoring and control, allowing the owner to lock or unlock the ignition via SMS in emergencies. This solution is costeffective, scalable, and highly versatile, making it suitable for both individual vehicle owners and commercial applications.

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Chen, Gang, Kai Huang, Long Cheng, Biao Hu, and Alois Knoll. "Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality." Journal of Circuits, Systems and Computers 25, no. 06 (2016): 1650062. http://dx.doi.org/10.1142/s0218126616500626.

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Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.

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Jiang, Shu Bin, та Jie Ru Su. "Research on μC/OS Operating System in GPS". Applied Mechanics and Materials 539 (липень 2014): 543–46. http://dx.doi.org/10.4028/www.scientific.net/amm.539.543.

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The article design a vehicle monitoring terminal system based on μC/OS and introduces the hardware system design of STM32F407 as the control core. On the basis of transplant μC/OS operating system, the system software architecture , application-layer multi-task and the priority has been designed, focuses on the use GPRS tasks, preparation methods GPS tasks. After experimental tests, the system is stable and reliable, the realization of real-time vehicle monitoring. System design methodology for embedded system application development has a certain reference value.

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Huang, Jing Long, Zhong Zhong Peng, and Pan Qing. "Design of the AC Motor Speed Regulator Controlled by ARM." Advanced Engineering Forum 2-3 (December 2011): 475–79. http://dx.doi.org/10.4028/www.scientific.net/aef.2-3.475.

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The paper proposes an AC motor speed regulate system based on ARM. The system's hardware core is the LPC2131, in which processor successfully transplanted the μC/OS-II real-time operating system. In the form of task, each functional module of the system can be achieved on the processor LPC2131.The system is simple hardware circuit, software module to realize the complex control algorithms. Experiments show that the multi-task classify program is feasible on the embedded real-time operating system based on LPC2131 and μC / OS-II, it ensures the system's real-time, has good multi-task operating and transferring characteristics and improves the system stability and reliability.

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He, Kuan Fang, Xue Jun Li, Ji Gang Wu та Jing Long Huang. "Inverter Control System of Alternating Current Motors Based on ARM and μC/OS-II". Advanced Engineering Forum 2-3 (грудень 2011): 480–85. http://dx.doi.org/10.4028/www.scientific.net/aef.2-3.480.

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This paper aims to design the inverter control system of alternating current (AC) motors based on Advanced RISC Machines (ARM) and μC/OS-II. The system's hardware core is the LPC2131 in which processor successfully transplanted the μC/OS-II real-time operating system. In the form of task, each functional module of the system is achieved on the processor LPC2131. Testing and experiments show that the multi-task classify program is feasible on the embedded real-time operating system based on LPC2131 and μC/OS-II, it ensures the system's real-time, has good multi-task operating and transferring characteristics and improves the system stability and reliability.

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Jang, Hyeoksoo, Sihyeong Park, and Hyungshin Kim. "Deferrable Task Execution Model for Reducing Memory Interference in a Real-Time Multi-Core Embedded System." Journal of Korean Institute of Information Technology 22, no. 2 (2024): 63–69. http://dx.doi.org/10.14801/jkiit.2024.22.2.63.

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