Relevant bibliographies by topics / Multi-Gate Transistors

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  2. Dissertations / Theses
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Academic literature on the topic 'Multi-Gate Transistors'

Author: Grafiati
Published: 14 March 2023

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Journal articles on the topic "Multi-Gate Transistors"

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Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (November 1, 2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.

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The advancement and challenges of field effect transistors are based on multi-gate transistors from the perspective of structure and material. Multi-gate field-effect transistors (Multi-gate FET) have steeper sub-threshold slopes, which can reduce the short channel effect and improve mobility and drive current. A fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are attractive multi-gate structures most compatible with today’s standard machining technologies. As the future moves towards smaller processes, FinFET and GAAFET processes limit the spacing between n-to-p devices. In order to increase the possibility of transistor miniaturization, innovative structures such as Forksheet FET and Complementary-FET (CFET) have been proposed.
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Sporea, Radu Alexandru. "(Invited) Multi-Gate Contact-Controlled Transistors." ECS Meeting Abstracts MA2021-01, no. 32 (May 30, 2021): 1058. http://dx.doi.org/10.1149/ma2021-01321058mtgabs.

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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.
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ZHANG, WEIQIANG, LI SU, YU ZHANG, LINFENG LI, and JIANPING HU. "LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 147–62. http://dx.doi.org/10.1142/s0218126611007128.

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The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.
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Mo, Zening, Zhidi Jiang, and Jianping Hu. "A Novel Three-Input Field Effect Transistor with Parallel Switching Function Using T-Shaped Channel." Journal of Electrical and Computer Engineering 2022 (April 11, 2022): 1–12. http://dx.doi.org/10.1155/2022/1432545.

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In this article, a novel three-input field effect transistor with parallel switching function (PSF-TiFET) is proposed. The channels of the new device consist of a vertical subchannel and two horizontal subchannels. The two horizontal subchannels are manufactured over the vertical subchannel by using smart-cut process. The top gate is located above the two horizontal subchannels. The front gate and back gate below the two horizontal subchannels are located on the two sides of the vertical subchannel, respectively. Each of the all three gates has roughly the same control area on the channel, and thus, the all three gates have roughly the same effect on the device channel. Due to its special structure, the new device is logically equivalent to three conventional single-input transistors in parallel. Compared with the traditional field effect transistors with a single-input terminal, the new device can be used to simplify the circuit with the reduced transistor number. The impacts of body thickness, gate oxide thickness, and work function on device performance are investigated, and then the device optimizations are carried out. The current characteristic of the device is theoretically analyzed. Silvaco TCAD simulations show that the theoretical analysis agrees well with the TCAD simulation results. This work explores the feasibility of multi-input devices, which would facilitate its development.
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Yang, Maolong, Yao Lu, Qiancui Zhang, Zhao Han, Yichi Zhang, Maliang Liu, Ningning Zhang, Huiyong Hu, and Liming Wang. "Charge transport behaviors in a multi-gated WSe2/MoS2 heterojunction." Applied Physics Letters 121, no. 4 (July 25, 2022): 043501. http://dx.doi.org/10.1063/5.0097390.

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Heterojunctions and multi-gated structures facilitate the fabrication of high-performance and multifunctional transistors. Here, a WSe2/MoS2 heterojunction structure transistor with a back gate and two top gates is proposed. The back gate controls the carrier transport of the entire heterojunction channel, and the top gates independently control the carrier transports of MoS2 or WSe2 channels. The rectification direction of the heterojunction device could be reversed, and the rectification ratio could be modulated from 10−4 to 104 by changing the back-gate voltage. In addition, an evident negative-differential transconductance phenomenon with a current peak and a current valley are observed in the back-gate transfer characteristic curve, which results from the different control ability of the same gate voltage to the Fermi levels in MoS2 and WSe2. The current peak can be obviously modulated and eliminated by the MoS2 top gate, while the WSe2 top gate can control the position of the current valley from −8 to +12 V, which clearly supports the heterostructure energy band model. Moreover, the diversity of output states under multi-gate modulation makes applications in logic circuits possible. These results demonstrate the potential of this approach for the development of next-generation electronic functional devices.
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Chu, Shunan. "Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder." Journal of Physics: Conference Series 2290, no. 1 (June 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2290/1/012008.

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Abstract Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.
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Kondo, Jun, Murali Lingalugari, Pik-Yiu Chan, Evan Heller, and Faquir Jain. "Modeling and Fabrication of Quantum Dot Channel Field Effect Transistors Incorporating Quantum Dot Gate." MRS Proceedings 1551 (2013): 149–54. http://dx.doi.org/10.1557/opl.2013.899.

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ABSTRACTQuantum dot gate (QDG) field-effect transistors (FET) have shown three-state transfer characteristics. Quantum dot channel (QDC) field-effect transistors (FET) have exhibited fourstate ID-VG characteristics. This project aims at studying the effect of incorporating cladded quantum dot layers in the gate region of QDC-FET. Four-state characteristics are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot superlattice (QDSL) channel. QDSL is formed by an array of cladded quantum dots (such as SiOx-Si and GeOx-Ge). Multi-state FETs are needed in multi-valued logic (MVL) that can reduce the number of gates and transistors in digital circuits. The fabricated device showed the four-state characteristic (OFF, ‘I1’, ‘I2’, ON).
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Boampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.

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We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.
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Bhadra, Debabrata. "USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE." International Journal of Advanced Research 9, no. 11 (November 30, 2021): 1095–101. http://dx.doi.org/10.21474/ijar01/13846.

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Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (<1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (εr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have been investigated. This device was showed highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of -1.6V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such a High-ε three layered (3L) PVDF/CuO gate dielectric appears to be highly promising candidates for organic non-volatile memory, sensor and field-effect transistors (FETs).
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Dissertations / Theses on the topic "Multi-Gate Transistors"

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Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.

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L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l’ús de materials d’alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s’han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l’escalat. Aquesta tesi s’enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s’utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material “high-κ”. Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l’aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel “International Technology Roadmap of Semiconductors” (ITRS) sobre la necessitat existent de modelatge i simulació d’estructures semiconductores multi-porta.
The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.
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Tocci, Gabriele. "Performance estimation and Variability from Random Dopant Fluctuations in Multi-Gate Field Effect Transistors : a Simulation Study." Thesis, KTH, Integrerade komponenter och kretsar, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-93419.

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As the formation of nearly abrupt p-n junctions in aggressively scaled transistors has become a complex task, a novel type of device in which there are no junctions has recently been suggested (J. P. Colinge et al., Nature 2010). The device of interest is referred to as the junctionless transistor, and it has demonstrated excellent functionality, with the advantage of a simpler fabrication process than conventional FETs. Despite the remarkable performances exhibited by the junctionless transistor, this device has to be tested against variability before it may be produced in large scale. Hence, the study of how the fluctuations in the number and in the position of the dopant atoms affects a large number of devices has been developed in this work. Such variability source is referred to as Random Dopant Fluctuations (RDF) and it is among the most critical ones for conventional MOSFETs. Our view is that RDF ought to largely affect the junctionless transistors. Hence, in this work we mainly aim at investigating the impact of RDF in these type of devices. Firstly, we provide a detailed analysis on the performance of an ideal junctionless transistor with a uniform non-random doping concentration, by mean of simulations developed using a TCAD software. Secondly, we investigate the effects of RDF in the junctionless transistor, as the principal aim of our study. Here, we determine how the I-V characteristics are affected by the random dopants and we illustrate fundamental the causes of the variations. A first estimation of the impact of RDF is provided by the illustration of the threshold voltage and beta [1] distributions, and by the computation of the fundamental statistical quantities relating to the two parameters. A further and last estimation is provided by the comparison obtained studying RDF on the inversion mode FET.
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Gaben, Loic. "Fabrication et caractérisation de transistors MOS à base de nanofils de silicium empilés et à grille enrobante réalisés par approche Gate-Last pour les noeuds technologiques sub-7 nm." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT095/document.

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La diminution de la taille des transistors actuellement utilisés en microélectronique ainsi que l’augmentation de leurs performances demeure encore au centre de toutes les attentions. Cette thèse propose d’étudier et de fabriquer des transistors à base de nanofils empilés. Cette architecture avec des grilles enrobantes est l’ultime solution pour concentrer toujours plus de courant électrique dans un encombrement minimal. Les simulations ont par ailleurs révélé le potentiel des nanofeuillets de silicium qui permettent à la fois d’optimiser l’espace occupé tout en proposant des performances supérieures aux dispositifs actuels. L’importance de l’ajout de certaines étapes de fabrication a également été soulignée. En ce sens, deux séries d’étapes de fabrication ont été proposées : la première option vise à minimiser le nombre de variations par rapport à ce qui est aujourd’hui en production tandis que la deuxième alternative offre potentiellement de meilleures performances au prix de développements plus importants. Les transistors ainsi fabriqués proposent des performances prometteuses supérieures à ce qui a pu être fabriqué dans le passé notamment grâce à l’introduction de contraintes mécaniques importantes favorables au transport du courant électrique
The future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport
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Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.

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Ce travail de thèse étudie de nouvelles configurations d'alimentation de commande rapprochée et un nouveau concept de packaging afin d'améliorer les performances des MOSFETs SiC connectés en série. Les nouvelles configurations de commande rapprochée sont proposées afin de réduire les courants de bruit qui circulent dans la partie commande du système électrique. De plus, une nouvelle alimentation de commande de grille est proposée pour augmenter le dv / dt de la cellule de commutation. Ces améliorations, c'est-à-dire la réduction du courant de bruit et l'amplification du dv/dt, sont obtenues en modifiant l'impédance des circuits de commande de grille. Le nouveau concept de packaging est proposé afin d'améliorer les performances d’équilibrage de tension. Les nouvelles configurations de commande rapprochée et les concepts de packaging sont introduits et analysés grâce à des modèles analytique et des simulations. Ensuite, des essayes expérimentales sont effectuées pour confirmer que les concepts proposés sont meilleurs que les concepts traditionnels en termes d'équilibrage de tension, de vitesse de commutation et de réduction EMI conduite
This work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction
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Zbierska, Inga Jolanta. "Study of electrical characteristics of tri-gate NMOS transistor in bulk technology." Thesis, Lyon 1, 2014. http://www.theses.fr/2014LYO10282/document.

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Afin de dépasser la limite d'échelle, il existe une solution innovante qui permet de fabriquer des structures multi-grilles. Ainsi, un NMOSFET composé de trois grilles indépendantes fabriquées dans la technologie CMOS. En dehors de leur forme, géométrique, le transistor multi-grille est similaire à une structure classique. Une multi-grille NMOSFET peut être fabriquée par l'intégration de tranchées de polysilicium. Ces tranchées sont utilisées dans diverses applications telles que les mémoires DRAM, électronique de puissance ou de capteurs d'image. Les capteurs d'image présentent le problème des charges parasites entre les pixels, appelées diaphonie. Les tranchées sont l'une des solutions qui réduisent ce phénomène. Ces tranchées assurent l'isolation électrique sur toute la matrice des pixels. Nous avons étudié ses caractéristiques en utilisant des mesures I-V, méthode du split C-V et de pompage de charge à deux et à trois niveaux. Son multi-seuil caractéristique a été vérifié. Nous n'avons observé aucune dégradation significative de ces caractéristiques grâce à l'intégration des tranchées. La structure a été simulée par la méthode des éléments finis en 3D via le logiciel TCAD. Ses caractéristiques électriques ont été simulées et confrontées avec les résultats obtenus à partir de mesures électriques. La tension de seuil et la longueur de canal effective ont été extraites. Sa mobilité effective et les pièges de l'interface Si/SiO2 ont également été simulés ou calculés. En raison des performances électriques satisfaisantes et d'un bon rendement, nous avons remarqué que ce dispositif est une solution adéquate pour les applications analogiques grâce aux niveaux de tension multi-seuil
One of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages
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ANTIDORMI, ALEANDRO. "Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643159.

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Silicon Nanowires (SiNWs) are considered the fundamental component blocks of future nanoelectronics. Many interesting properties have gained them such a prominent position in the investigation in recent decades. Large surface-to-volume ratio, bio-compatibility, band-gap tuning are among the most appealing features of SiNWs. More importantly, in the ongoing process of dimension miniaturization, SiNWs compatibility with the existing and reliable silicon technology stands as a fundamental advantage. Consequently, the employment of SiNWs spred in several application fields: from computational logic where SiNWs are used to realize transistors, to bio-chemical sensing and nanophotonic applications. In this thesis work we concentrate our attention on the employment of SiNWs in computational logic and bio-chemical sensing. In particular, we aim at giving a contribution in the modelling and simulation of SiNW-based electron devices. Given the current intense investigation of new devices, the modelling of their electrical behaviour is strongly required. On one side, modelling procedures could give an insight on the physical phenomena of transport in nanometer scale systems where quantum effects are dominant. On the other side, the availability of compact models for actual devices can be of undeniable help in the future design process. This work is divided into two parts. After a brief introduction on Silicon Nanowires, the main fabrication techniques and their properties, the first part is dedicated to the modelling of Multiple-Independent Gate Transistors, a new generation of devices arisen from the composition of Gate-All-Around Transistors, finFETs and Double-Gate Transistors. Interesting applications resulting from their employment are Vertically-stacked Silicon Nanowire FETs, known to have an ambipolar behaviour, and Silicon Nanowire Arrays. We will present a compact numerical model for composite Multiple-Independent Gate Transistors which allows to compute current and voltages in complex structures. Validation of the model through simulation proves the accuracy and the computational efficiency of the resulting model. The second part of the thesis work is instead devoted to Silicon Nanowires for bio-chemical sensing. In this respect, major attention is given to Porous Silicon (PS), a non-crystalline material which demonstrated peculiar features apt for sensing. Given its not regular microscopic morphology made of a complex network of crystalline and non-crystalline regions, PS has large surface-to-volume ratio and a relevant chemical reactivity at room temperature. In this work we start from the fabrication of PS nanowires at Istituto Nazionale di Ricerca Metrologica in Torino (I.N.Ri.M.) to devise two main models for PSNWs which can be used to understand the effects of porosity on electron transport in these structures. The two modelling procedures have different validity regimes and efficiently take into account quantum effects. Their description and results are presented. The last part of the thesis is devoted to the impact of surface interaction of molecular compounds and dielectric materials on the transport properties of SiNWs. Knowing how molecules interact with silicon atoms and how the conductance of the wire is affected is indeed the core of SiNWs used for bio-chemical sensing. In order to study the phenomena involved, we performed ab-initio simulations of silicon surface interacting with SO2 and NO2 via the SIESTA package, implementing DFT code. The calculations were performed at Institut de Ciencia De Materials de Barcelona (ICMAB-CSIC) using their computational resources. The results of this simulation step are then exploited to perform simulation of systems made of an enormous quantity of atoms. Due to their large dimensions, atomistic simulations are not affordable and other approaches are necessary. Consequently, calculations with physics-based softwares on a larger spatial scale were adopted. The description of the obtained results occupies the last part of the work together with the discussion of the main theoretical insight gained with the conducted study.
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Baldauf, Tim. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-132044.

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Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab
Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work
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Weisz, Mario. "Electrothermal device-to-circuit interactions for half THz SiGe∶C HBT technologies." Thesis, Bordeaux 1, 2013. http://www.theses.fr/2013BOR14909/document.

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Ce travail concerne les transistors bipolaires à hétérogène TBH SiGe. En particulier, l'auto-échauffement des transistors unitaires et le couplage thermique avec leurs plus proches voisins périphériques sont caractérisés et modélisés. La rétroaction électrothermique intra- et inter-transistor est largement étudiée. En outre, l’impact des effets thermiques sur la performance de deux circuits analogiques est évalué. L'effet d'autoéchauffement est évalué par des mesures à basse fréquence et des mesures impulsionnelles DC et AC. L'auto-échauffement est diminué de manière significative en utilisant des petites largeurs d'impulsion. Ainsi la dépendance fréquentielle de l’autoéchauffementa été étudiée en utilisant les paramètres H et Y. De nouvelles structures de test ont été fabriqués pour mesurer l'effet de couplage. Les facteurs de couplage thermique ont été extraits à partir de mesures ainsi que par simulations thermiques 3D. Les résultats montrent que le couplage des dispositifs intra est très prononcé. Un nouvel élément du modèle de résistance thermique récursive ainsi que le modèle de couplage thermique a été inclus dans un simulateur de circuit commercial. Une simulation transitoire entièrement couplée d'un oscillateur en anneau de 218 transistors a été effectuée. Ainsi, un retard de porte record de 1.65ps est démontré. À la connaissance des auteurs, c'est le résultat le plus rapide pour une technologie bipolaire. Le rendement thermique d'un amplificateur de puissance à 60GHz réalisé avec un réseau multi-transistor ou avec un transistor à plusieurs doigts est évalué. La performance électrique du transistor multidoigt est dégradée en raison de l'effet de couplage thermique important entre les doigts de l'émetteur. Un bon accord est constaté entre les mesures et les simulations des circuits en utilisant des modèles de transistors avec le réseau de couplage thermique. Enfin, les perspectives sur l'utilisation des résultats sont données
The power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed
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Baldauf, Tim [Verfasser], Gerald [Akademischer Betreuer] Gerlach, and Roland [Akademischer Betreuer] Stenzel. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie / Tim Baldauf. Gutachter: Gerald Gerlach ; Roland Stenzel. Betreuer: Gerald Gerlach ; Roland Stenzel." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://d-nb.info/1068444916/34.

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Wilson, Veas Alan Hjalmar [Verfasser], Steffen [Gutachter] Bernet, Mariusz [Gutachter] Malinowski, and Steffen [Akademischer Betreuer] Bernet. "Investigation of Multi-Level Neutral Point Clamped Voltage Source Converters using Isolated Gate Bipolar Transistor Modules / Alan Hjalmar Wilson Veas ; Gutachter: Steffen Bernet, Mariusz Malinowski ; Betreuer: Steffen Bernet." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1226899463/34.

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Books on the topic "Multi-Gate Transistors"

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Colinge, Jean-Pierre, ed. FinFETs and Other Multi-Gate Transistors. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-71752-4.

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Colinge, J. P. FinFETs and Other Multi-Gate Transistors. Springer, 2010.

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Colinge, J. P. FinFETs and Other Multi-Gate Transistors. Springer London, Limited, 2007.

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FinFETs and Other Multi-Gate Transistors (Series on Integrated Circuits and Systems). Springer, 2007.

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Book chapters on the topic "Multi-Gate Transistors"

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Kumar, Subindu, and Tarun Kumar Sharma. "On-Chip Carbon Nanotube Interconnects: Adaptation to Multi-gate Transistors." In Carbon Related Materials, 127–47. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7610-2_7.

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Saini, Gaurav, and Trailokya Nath Sasamal. "Asymmetric Junctionless Transistor." In High-k Materials in Multi-Gate FET Devices, 141–50. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003121589-9.

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Usha, C., and P. Vimala. "Influence of High-k Material in Gate Engineering and in Multi-Gate Field Effect Transistor Devices." In High-k Materials in Multi-Gate FET Devices, 33–54. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003121589-3.

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Kumar, Raj, Shashi Bala, and Arvind Kumar. "Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors." In Advances in Computer and Electrical Engineering, 54–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch003.

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To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.
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"Multi-Gate Transistor Model." In BSIM4 and MOSFET Modeling For IC Simulation, 387–410. WORLD SCIENTIFIC, 2011. http://dx.doi.org/10.1142/9789812813992_0011.

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Conference papers on the topic "Multi-Gate Transistors"

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Weber, Cory, Dipanjan Basu, Roza Kotlyar, and Saurabh Morarka. "Technology CAD challenges of modeling multi-gate transistors." In 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2013. http://dx.doi.org/10.1109/sispad.2013.6650588.

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Saha, Jhuma, Subindu Kumar, and Shankaranand Jha. "A comparative analysis of some multi-gate junctionless transistors." In 2015 6th International Conference on Computers and Devices for Communication (CODEC). IEEE, 2015. http://dx.doi.org/10.1109/codec.2015.7893201.

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Soares, Caroline S., Pranay K. R. Baikadi, Alan C. J. Rossetto, Marcelo A. Pavanello, Dragica Vasileska, and Gilson I. Wirth. "Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential." In 2022 36th Symposium on Microelectronics Technology (SBMICRO). IEEE, 2022. http://dx.doi.org/10.1109/sbmicro55822.2022.9881047.

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Thean, A. V.-Y., Z.-H. Shi, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, et al. "Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors." In 2006 International Electron Devices Meeting. IEEE, 2006. http://dx.doi.org/10.1109/iedm.2006.346923.

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Chatterjee, A., S. Aur, T. Niuya, P. Yang, and J. A. Seitchik. "Failure in CMOS circuits induced by hot carriers in multi-gate transistors." In 26th International Reliability Physics Symposium. IEEE, 1988. http://dx.doi.org/10.1109/irps.1988.362195.

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Han, Shu-Jen, Satoshi Oida, Keith A. Jenkins, and Darsen D. Lu. "High fMAX/fT ratio in multi-finger embedded T-shaped gate graphene transistors." In 2013 71st Annual Device Research Conference (DRC). IEEE, 2013. http://dx.doi.org/10.1109/drc.2013.6633781.

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Zhang, Xuncai, Dongjun Luo, Guangzhao Cui, Yanfeng Wang, and Buyi Huang. "Construction of Logic Gate Based on Multi-channel Carbon Nanotube Field-Effect Transistors." In 2011 International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC). IEEE, 2011. http://dx.doi.org/10.1109/ihmsc.2011.93.

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Hoque, Asiful, Mohammad Rabib Hossain, and Md Ishfak Tahmid. "A Comparative Study on Design and Characterization of Single Gate and Double Gate Multi-Channel Junctionless Nanowire Transistors." In 2020 IEEE Region 10 Symposium (TENSYMP). IEEE, 2020. http://dx.doi.org/10.1109/tensymp50017.2020.9230591.

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Jin, Seonghoon, Sung-Min Hong, Woosung Choi, Keun-Ho Lee, and Youngkwan Park. "Coupled drift-diffusion (DD) and multi-subband Boltzmann transport equation (MSBTE) solver for 3D multi-gate transistors." In 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2013. http://dx.doi.org/10.1109/sispad.2013.6650646.

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Chin, Hock-Chun, Moh-Lung Ling, Bin Liu, Xingui Zhang, Jie Li, Yongdong Liu, Jiangtao Hu, and Yee-Chia Yeo. "Metrology solutions for high performance germanium multi-gate field-effect transistors using optical scatterometry." In SPIE Advanced Lithography, edited by Alexander Starikov and Jason P. Cain. SPIE, 2013. http://dx.doi.org/10.1117/12.2013413.

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Reports on the topic "Multi-Gate Transistors"

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Nochetto, Horacio C., Nicholas R. Jankowski, Brian Morgan, and Avram Bar-Cohen. A Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance. Fort Belvoir, VA: Defense Technical Information Center, October 2012. http://dx.doi.org/10.21236/ada570599.

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