Dissertations / Theses on the topic 'Multi-level converters'

A new concept, the multi level voltage/current reinjection ac/dc conversion, is described in this thesis. Novel voltage and current source converter configurations, based on voltage and current reinjection concepts are proposed. These converter configurations are thoroughly analyzed in their ac and dc system sides. The fundamentals of the reinjection concept is discussed briefly, which lead to the derivation of the ideal reinjection waveform for complete harmonic cancellation and approximations for practical implementation. The concept of multi level voltage reinjection VSC is demonstrated through two types of configurations, based on standard 12-pulse parallel and series connected VSC modified with reinjection bridges and transformers. Firing control strategies and steady state waveform analysis are presented and verified by EMTDC simulations. The multi level current reinjection CSC is also described using two configurations based on standard 12-pulse parallel and series connected CSC modified with associated reinjection circuitry. Firing control strategies and steady state waveform analysis are presented and verified by EMTDC simulations. Taking the advantage of zero current switching in the main bridge valves, achieved through multi level current reinjection, an advanced multi level current reinjection scheme, consisting thyristor main bridges and self-commutated reinjection circuitry is proposed. This hybrid scheme effectively incorporates self-commutated capability into a conventional thyristor converter. The ability of the main bridge valves to commutate without the assistance of a turn-off pulse or line commutating voltage under the zero current condition is explained and verified by EMTDC simulations. Finally, the applications of the MLCR-CSC are discussed in terms of a back to back HVDC link and a long distance HVDC transmission system. The power and control structures and closed loop control strategies are presented. Dynamic simulation is carried out on PSCAD/EMTDC to demonstrate the two systems ability to respond to varying active and reactive power operating conditions.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.<br>Thesis advisor(s): Robert W. Ashton, John G. Ciezki, Douglas J. Fouts. Includes bibliographical references (p. 125-126). Also available online.

Power dissipation of integrated circuits is the most demanding issue for very large scale integration (VLSI) design engineers, especially for portable and mobile applications. Use of multiple supply voltages systems, which employs level converter between two voltage islands is one of the most effective ways to reduce power consumption. In this thesis work, a unique level converter known as universal level converter (ULC), capable of four distinct level converting operations, is proposed. The schematic and layout of ULC are built and simulated using CADENCE. The ULC is characterized by performing three analysis such as parametric, power, and load analysis which prove that the design has an average power consumption reduction of about 85-97% and capable of producing stable output at low voltages like 0.45V even under varying load conditions.

Thesis (M.S.)--Missouri University of Science and Technology, 2010.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed July 26, 2010) Includes bibliographical references (p. 96-102).

This thesis reports on the investigations, simulations and analyses of novel power electronics topologies and control strategies. The research is financed by an Australian Research Council (ARC) Linkage (07-09) grant. Therefore, in addition to developing original research and contributing to the available knowledge of power electronics, it also contributes to the design of a DC-DC converter for specific application to the auxiliary power supply in electric trains. Specifically, in this regard, it contributes to the design of a 7.5 kW DC-DC converter for the industrial partner (Schaffler and Associates Ltd) who supported this project. As the thesis is formatted as a ‘thesis by publication’, the contents are organized around published papers. The research has resulted in eleven papers, including seven peer reviewed and published conference papers, one published journal paper, two journal papers accepted for publication and one submitted journal paper (provisionally accepted subject to few changes). In this research, several novel DC-DC converter topologies are introduced, analysed, and tested. The similarity of all of the topologies devised lies in their ‘current circulating’ switching state, which allows them to store some energy in the inductor, as extra inductor current. The stored energy may be applied to enhance the performance of the converter in the occurrence of load current or input voltage disturbances. In addition, when there is an alternating load current, the ability to store energy allows the converter to perform satisfactorily despite frequently and highly varying load current. In this research, the capability of current storage has been utilised to design topologies for specific applications, and the enhancement of the performance of the considered applications has been illustrated. The simplest DC-DC converter topology, which has a ‘current circulating’ switching state, is the Positive Buck-Boost (PBB) converter (also known as the non-inverting Buck-Boost converter). Usually, the topology of the PBB converter is operating as a Buck or a Boost converter in applications with widely varying input voltage or output reference voltage. For example, in electric railways (the application of our industrial partner), the overhead line voltage alternates from 1000VDC to 500VDC and the required regulated voltage is 600VDC. In the course of this research, our industrial partner (Schaffler and Associates Ltd) industrialized a PBB converter–the ‘Mudo converter’–operating at 7.5 kW. Programming the onboard DSP and testing the PBB converter in experimental and nominal power and voltage was part of this research program. In the earlier stages of this research, the advantages and drawbacks of utilization of the ‘current circulating’ switching state in the positive Buck-Boost converter were investigated. In brief, the advantages were found to be robustness against input voltage and current load disturbances, and the drawback was extra conduction and switching loss. Although the robustness against disturbances is desirable for many applications, the price of energy loss must be minimized to attract attention to the utilization of the PBB converter. In further stages of this research, two novel control strategies for different applications were devised to minimise the extra energy loss while the advantages of the positive Buck-Boost converter were fully utilized. The first strategy is Smart Load Controller (SLC) for applications with pre-knowledge or predictability of input voltage and/or load current disturbances. A convenient example of these applications is electric/hybrid cars where a master controller commands all changes in loads and voltage sources. Therefore, the master controller has a pre-knowledge of the load and input voltage disturbances so it can apply the SLC strategy to utilize robustness of the PBB converter. Another strategy aiming to minimise energy loss and maximise the robustness in the face of disturbance is developed to cover applications with unexpected disturbances. This strategy is named Dynamic Hysteresis Band (DHB), and is used to manipulate the hysteresis band height after occurrence of disturbance to reduce dynamics of the output voltage. When no disturbance has occurred, the PBB converter works with minimum inductor current and minimum energy loss. New topologies based on the PBB converter have been introduced to address input voltage disturbances for different onboard applications. The research shows that the performance of applications of symmetrical/asymmetrical multi-level diode-clamped inverters, DC-networks, and linear-assisted RF amplifiers may be enhanced by the utilization of topologies based on the PBB converter. Multi-level diode-clamped inverters have the problem of DC-link voltage balancing when the power factor of their load closes to unity. This research has shown that this problem may be solved with a suitable multi-output DC-DC converter supplying DClink capacitors. Furthermore, the multi-level diode-clamped inverters supplied with asymmetrical DC-link voltages may improve the quality of load voltage and reduce the level of Electromagnetic Interference (EMI). Mathematical analyses and experiments on supplying symmetrical and asymmetrical multi-level inverters by specifically designed multi-output DC-DC converters have been reported in two journal papers. Another application in which the system performance can be improved by utilization of the ‘current circulating’ switching state is linear-assisted RF amplifiers in communicational receivers. The concept of ‘linear-assisted’ is to divide the signal into two frequency domains: low frequency, which should be amplified by a switching circuit; and the high frequency domain, which should be amplified by a linear amplifier. The objective is to minimize the overall power loss. This research suggests using the current storage capacity of a PBB based converter to increase its bandwidth, and to increase the domain of the switching converter. The PBB converter addresses the industrial demand for a DC-DC converter for the application of auxiliary power supply of a typical electric train. However, after testing the industrial prototype of the PBB converter, there were some voltage and current spikes because of switching. To attenuate this problem without significantly increasing the switching loss, the idea of Active Gate Signalling (AGS) is presented. AGS suggests a smart gate driver that selectively controls the switching process to reduce voltage/current spikes, without unacceptable reduction in the efficiency of switching.

Over the past ten years, there has been increased use of electronic power processing in alternative, sustainable, and distributed energy sources, as well as energy storage systems, transportation systems, and the power grid. Three-phase voltage source converters (VSCs) have become the converter of choice in many ac medium- and high-power applications due to their many advantages, such as high efficiency and fast response. For transportation applications, high power density is the key design target, since increasing power density can reduce fuel consumption and increase the total system efficiency. While power electronics devices have greatly improved the efficiency, overall performance and power density of power converters, using power electronic devices also introduces EMI issues to the system, which means filters are inevitable in those systems, and they make up a significant portion of the total system size and cost. Thus, designing for high power density for both power converters and passive components, especially filters, becomes the key issue for three-phase converters. This dissertation explores two different approaches to reducing the EMI filter size. One approach focuses on the EMI filters itself, including using advanced EMI filter structures to improve filter performance and modifying the EMI filter design method to avoid overdesign. The second approach focuses on reducing the EMI noise generated from the converter using a three-level and/or interleaving topology and changing the modulation and control methods to reduce the noise source and reduce the weight and size of the filters. This dissertation is divided into five chapters. Chapter 1 describes the motivations and objectives of this research. After an examination of the surveyed results from the literature, the challenges in this research area are addressed. Chapter 2 studies system-level EMI modeling and EMI filter design methods for voltage source converters. Filter-design-oriented EMI modeling methods are proposed to predict the EMI noise analytically. Based on these models, filter design procedures are improved to avoid overdesign using in-circuit attenuation (ICA) of the filters. The noise propagation path impedance is taken into consideration as part of a detailed discussion of the interaction between EMI filters, and the key design constraints of inductor implementation are presented. Based on the modeling, design and implementation methods, the impact of the switching frequency on EMI filter weight design is also examined. A two-level dc-fed motor drive system is used as an example, but the modeling and design methods can also be applied to other power converter systems. Chapter 3 presents the impact of the interleaving technique on reducing the system passive weight. Taking into consideration the system propagation path impedance, small-angle interleaving is studied, and an analytical calculation method is proposed to minimize the inductor value for interleaved systems. The design and integration of interphase inductors are also analyzed, and the analysis and design methods are verified on a 2 kW interleaved two-level (2L) motor drive system. Chapter 4 studies noise reduction techniques in multi-level converters. Nearest three space vector (NTSV) modulation, common-mode reduction (CMR) modulation, and common-mode elimination (CME) modulation are studied and compared in terms of EMI performance, neutral point voltage balancing, and semiconductor losses. In order to reduce the impact of dead time on CME modulation, the two solutions of improving CME modulation and compensating dead time are proposed. To verify the validity of the proposed methods for high-power applications, a 100 kW dc-fed motor drive system with EMI filters for both the AC and DC sides is designed, implemented and tested. This topology gains benefits from both interleaving and multilevel topologies, which can reduce the noise and filter size significantly. The trade-offs of system passive component design are discussed, and a detailed implementation method and real system full-power test results are presented to verify the validity of this study in higher-power converter systems. Finally, Chapter 5 summarizes the contributions of this dissertation and discusses some potential improvements for future work.<br>Ph. D.

Une étude sur la réduction/suppression de l'inductance de limitation di/dt pour IGCTs et du clamp RCD en utilisant des diodes rapides en silicium (Si) et des diodes en carbure de silicium (SiC) dans les convertisseurs multiniveaux modulaires (MMC). Cette thèse contient :- Analyse des sous-modules de MMC HVDC existants.- Évaluation de l'intérêt des IGCTs dans les sous-modules MMC HVDC et comparaison des pertes avec les IGBT, en utilisant des facteurs de mérite spécifiques aux MMC créés dans cette thèse.- Test de double pulse avec diode à récupération rapide dans un module plastique pour tenter de réduire et supprimer l'inductance limitant le di/dt.- Packaging de puces de diodes SiC PiN à haute tension et courant élevé, test avec IGCT dans le même montage, pour tenter de réduire et supprimer l'inductance limite di/dt, et analyser les spécificités de la diode SiC dans ce montage<br>A study on Integrated gate-commutated thyristors (IGCT) di/dt limiting inductance and RCD-clamp reduction/suppression using plastic module silicon (Si) fast recovery diodes and silicon carbide (SiC) diodes, in Modular Multilevel Converters (MMC). This PhD contains:- Analysis of existing HVDC MMC Submodules.- Assessment of the interest of the IGCT in HVDC MMC Submodules and losses comparison with IGBTs, using MMC-specific figures-of-merit created in this thesis.- Double pulse test with fast recovery diode in plastic module to attempt to reduce and suppress the limiting di/dt inductor.- Packaging of High-Voltage High-Current SiC PiN diode dies, test with IGCT in the same setup to attempt to reduce and suppress the limiting di/dt inductor and analyze the specificities of the SiC diode in this setup

Les Alimentations Sans Interruption sont utilisées pour assurer la qualité et la continuité de l'énergie fournie aux charges sensibles. Basées sur deux conversions d'énergie électrique, ces alimentations supportent en permanence la puissance de la charge, rendant crucial leur rendement. Cette thèse a exploré différentes voies d'amélioration du rendement du commutateur assurant la conversion : le choix des composants semi-conducteurs, celui de la structure de conversion et du mode de fonctionnement. Le filtrage a été pris en compte sans faire l'objet d'investigations poussées. La méthode d'estimation du rendement, exploitant des données des constructeurs, a permis de quantifier l'impact et les limites de chaque voie explorée. Plusieurs structures de conversion multi-niveaux en commutation douce ont été développées, utilisant un pôle résonant. Enfin, plusieurs expérimentations ont validé les modèles utilisés, le concept du pôle résonant et la réalisation d'un prototype fonctionnel de 125 kVA.

AC and DC impedances of switching power converters are used for the stability analysis of modern power electronics systems at three-phase AC and single-phase DC interfaces. Therefore, a small-signal characterization algorithm for switching power converter, which is based on FFT, will be presented and explained. The presented extraction algorithm is general and can be used to obtain other small-signal transfer functions of arbitrary power converter switching simulation models. Furthermore, FFT algorithm is improved by using cross power spectral density functions for identification, resulting in an algorithm, which is more noise immune. Both small-signal identification algorithms are validated in simulations, and CPSD algorithm is used in experimental measurement procedure. Several wide bandwidth injection signals, among which are chirp, multi-tone, pulse and white noise, are compared and theoretically analyzed. Several hardware examples are included in the analysis. The second part of the dissertation will focus on the modeling of small-signal input dq admittance of multi-pulse diode rectifiers, providing comparison between well-known averaged value models (AVMs), parametric averaged value models (PAVM), the switching simulation model and hardware measurements. Analytical expressions for all four admittances present in the dq matrix are derived and analyzed in depth, revealing the accuracy range of the averaged models. Furthermore, a hardware set-up is built, measured and modeled, showing that the switching simulation model captures nonlinear sideband effects accurately. In the end, a multi-pulse diode rectifier feeding a constant power load is analyzed with modified AVM and through detailed simulations of switching model, proving effectiveness of the proposed modifications. The third part describes implementation and design of a single-phase multi-level single-phase shunt current injection converter based on cascaded H-bridge topology. Special attention is given toward the selection of inductors and capacitors, trying to optimize the selected component values and fully utilize operating range of the converter. The proposed control is extensively treated, including inner current, outer voltage loop and voltage balancing loops. The designed converter is constructed and integrated with measurement system, providing experimental verification. The proposed multi-level single-phase converter is a natural solution for single-phase shunt current injection with the following properties: modular design, capacitor energy distribution, reactive element minimization, higher equivalent switching frequency, capability to inject higher frequency signals, suitable to perturb higher voltage power systems and capable of generating cleaner injection signals. Finally, a modular interleaved single-phase series voltage injection converter, consisting of multiple paralleled H-bridges is designed and presented. The decoupling control is proposed to regulate ac injection voltage, providing robust and reliable strategy for series voltage injection. The designed converter is simulated using detailed switching simulation model and excellent agreement between theory and simulation results are obtained. The presented control analysis treats different loads, examining robustness of the circuit to load variations. Simulation model and hardware prototype results verify the effectiveness of the proposed wide-bandwidth identification of small-signal dq impedances via single-phase injections.<br>Ph. D.

Les travaux de thèse s’inscrivent dans les problématiques des travaux de recherche de l’équipe thématique : Maitrise des Energies Renouvelables et systèmes de Stockage (MERS) du laboratoire GREAH-EA3220. Ils englobent le dimensionnement des éléments constitutifs du système et la gestion optimale de l’énergie électrique pour un système hybride (Diesel à vitesse variable, Eolien, PV et Batteries) dédié aux sites isolés. Les sources de production d'énergie alimentent des charges par le biais de convertisseurs multi-niveaux d’électronique de puissance. Le groupe électrogène comportant un moteur diesel à vitesse variable est considéré comme la principale source d’énergie utilisée pour contrôler la tension continue du point de couplage. Ce type de groupe électrogène est choisi pour optimiser la consommation du carburant. Il est sollicité pour délivrer une puissance électrique compatible avec le régime du moteur qui supporte mal les variations fréquentes et rapides. Les sources d’énergie renouvelables dont on cherche à augmenter la part d’énergie pour satisfaire la demande sont pilotées de manière à extraire instantanément le maximum de puissances disponible par les ressources (ensoleillement, vent). Celles-ci imposent ainsi leurs dynamiques et leurs intermittences au point de couplage. Le pack des batteries sert à compenser les fluctuations rapides de l’énergie provenant des sources d’énergie renouvelables par rapport à une évolution plus lente prise en charge par le groupe électrogène. La gestion des interactions au sein du système électrique hybride résultant est assurée au moyen de convertisseurs statiques multi-niveaux (AC / DC, DC / DC et DC / AC). Une approche de gestion d’énergie électrique fondée sur la répartition fréquentielle des perturbations induites au point de couplage par les sources renouvelables. Une plateforme expérimentale à échelle réduite (1/22) a été développée pour valider expérimentalement les approches théoriques et les simulations. Les résultats de simulations obtenus dans l’environnement logiciel Matlab/Simulink/SimPowerSystems et ceux issus du dispositif expérimental réalisé et piloté par dSPACE-1104 prouvent l’adéquation des méthodes de contrôle proposées<br>The thesis works are part of the research work of the thematic team: Mastery of Renewable Energies and Storage Systems (MERS) of the GREAH-EA3220 laboratory. They include the dimensioning of the constituent elements of the system and the optimal management of electrical energy for a hybrid system (Variable speed Diesel, Wind, PV and Batteries) dedicated to isolated sites. Power sources supply loads through multi-level converters of power electronics. The generator set with a variable speed diesel engine is considered to be the main source of energy used to control the DC voltage at the coupling point. This type of generator is chosen to optimize fuel consumption. It is used to deliver an electrical power compatible with the engine speed which does not tolerate frequent and rapid variations. Renewable energy sources whose share of energy is sought to meet demand are managed so as to instantly extract the maximum power available from resources (sunshine, wind). These thus impose their dynamics and their intermittences at the coupling point. The battery pack is used to compensate for rapid fluctuations in energy from renewable energy sources compared to a slower evolution supported by the generator. Interactions within the resulting hybrid electrical system are managed by means of multi-level static converters (AC / DC, DC / DC and DC / AC). An electrical energy management approach based on the frequency distribution of disturbances induced at the coupling point by renewable sources. An experimental platform on a reduced scale (1/22) has been developed to experimentally validate theoretical approaches and simulations. The results of simulations obtained in the Matlab / Simulink / SimPowerSystems software environment and those from the experimental device produced and piloted by dSPACE-1104 prove the adequacy of the proposed control methods

This thesis explains the working principles of an AC/DC converter topology intended for HVDC applications, called the Alternate Arm Converter (AAC). It consists of a hybrid between the modular multi-level converter (MMC) through the presence of H-bridge cells and the 2-level converter because of the director switches in each arm. Thanks to its cells, the AAC is able to generate a multi-level staircase AC voltage waveform which results a low distortion AC current while the director switches control which arms are conducting at any given time. By synchronising the conduction period of an arm with the zero-crossing points of the AC voltage waveform, the voltage rating of the stacks can be reduced, hence minimizing the number of cells. In case of a DC-side fault, an AAC with enough cells is able to keep control of the current in the phase reactor and even be operated to support the AC grid by providing reactive power similarly to a STATCOM. Since the AAC relies on pre-charged H-bridge cells, an effective energy management is required to control their level of charge. An ideal working point has been identified, called 'Sweet-Spot'. This operating point describes a set of conditions where the incoming and outgoing energy flows equate, in effect nullifying the average energy drift of the cells. Additional energy techniques based on current modulation have been developed in order to redistribute the energy inside the converter. The study of the AAC has provided an understanding of its working and device requirement and a hierarchical structure for its control system has been developed. Simulation results confirm these findings both on the operation of the AAC under normal and abnormal situations and on the effectiveness of the developed energy management system. Post-processing of the simulation data has also shown that the AAC is on par with the half-bridge MMC on power efficiency.

This thesis investigates space-vector modulation and one-dimensional modulation applied to the cascaded H-bridge multi-level converter as a model for one port of the UNIFLEX-PM power converter system. The UNIFLEX-PM converter is a modular system including galvanic isolation at medium frequency intended to replace transformers in future distribution and transmission systems. Power converters in this application must produce good quality voltage waveforms with low power loss. In this work, modulation methods are developed using theoretical analyses and simulation studies, before being verified experimentally using a low voltage, laboratory-based power converter operating at the low switching frequencies applicable to high-power applications. Using space-vector modulation, the relationship between the phase of the sampling process and the distortion of the line voltages is used to reduce the harmonic distortion of the output voltages. Different loads are attached to the cells of the cascaded H-bridge converter and limits are derived determining the range of loads for which it is possible to equalize the capacitor voltages. An algorithm which uses redundant states to balance the capacitor voltages without increasing the switching frequency is applied to space-vector modulation and one-dimensional modulation and its performance is compared to the derived limits. The geometrical effect of capacitor voltage ripple on the space-vector diagram is used to derive the influence on the spectrum of the line-voltages. It is identified that second and fourth harmonics of the capacitor voltages contribute to fifth and seventh harmonics of the line voltages. A feed-forward scheme to compensate for the ripple of the capacitor voltage is derived and is shown to reduce the magnitude of un-wanted harmonics. All the methods developed in this thesis can be applied to converters with any number of cells.

Two vital and dynamically changing issues are arising in the electric grid - an increase in electrical power demand, and subsequent reduction in power quality. Power electronics based solutions such as the Static Synchronous Compensator are increasingly deployed to mitigate power quality issues while High Voltage DC Transmission converters are currently installed to support the existing grid transmission capacity. Both applications require high power and high voltage power converters using switching devices with limited voltage ratings. The advent of Modular Multilevel Converters (MMC) is one of the recent responses to this need. These use half or full H-bridge circuits stacked up to form a chain, and hence can withstand high voltages using lower-rated switching devices. This thesis introduces a new member into the MMC family, i.e the Modular Multi-level Flying Capacitor Converter (MMFCC). This uses a three-level flying capacitor full-bridge circuit as a sub-module and offers features of modularity, scalability and fault tolerance. The choice of FC topology in place of the simple H-bridge stems from the FC’s ability to offer two extra voltage levels in the sub-module output and hence more degrees of freedom per module in controlling the voltage waveform. A three-level full-bridge FC sub-module uses three capacitors - an outer one for supporting the sub-module voltage, and two inner floating ones with half of the outer one’s capacitance and voltage rating. This use of slightly more complex FC sub-modules gives the benefits of a modular structure but without using twice as many sub-modules with their associated capacitors for the same total voltage. The thesis presents the principles of this topology, switching states redundancies and a method for capacitor voltage balancing. Also discussed are: the configuration of MMCC including the MMFCC in Single-Star Bridge-Cell (SSBC) or Single-Delta Bridge-Cell (SDBC) for FACTS and Battery Energy Storage System (BESS) applications; and Double-Star Chopper-Cell (DSCC) or Double-Star Bridge-Cell (DSBC) for HVDC systems. A novel overlapping hexagon pulse width modulation scheme is introduced and discussed for switching control of the MMFCC. This uses multiple hexagons all centred on one point, the same in number as the cascaded FC sub-modules, which are phase displaced relative to each other. The approach simplifies the modulation algorithm and brings flexibility in shaping the output voltage waveforms for different applications. An MMFCC experimental rig was designed and built in-house to validate some of the simulation results obtained for the modulation of this new topology. Details of the rig as well as results captured are discussed.

Doctor of Philosophy<br>Department of Electrical and Computer Engineering<br>Ruth Douglas Miller<br>This dissertation presents the design of a novel multi-level inverter with FACTS capability for small to mid-size (10–20kW) permanent-magnet wind installations using modular multi-level converter (MMC) topology. The aim of the work is to design a new type of inverter with D-STATCOM option to provide utilities with more control on active and reactive power transfer of distribution lines. The inverter is placed between the renewable energy source, specifically a wind turbine, and the distribution grid in order to fix the power factor of the grid at a target value, regardless of wind speed, by regulating active and reactive power required by the grid. The inverter is capable of controlling active and reactive power by controlling the phase angle and modulation index, respectively. The unique contribution of the proposed work is to combine the two concepts of inverter and D-STATCOM using a novel voltage source converter (VSC) multi-level topology in a single unit without additional cost. Simulations of the proposed inverter, with 5 and 11 levels, have been conducted in MATLAB/Simulink for two systems including 20 kW/kVAR and 250 W/VAR. To validate the simulation results, a scaled version (250 kW/kVAR) of the proposed inverter with 5 and 11 levels has been built and tested in the laboratory. Experimental results show that the reduced-scale 5- and 11-level inverter is able to fix PF of the grid as well as being compatible with IEEE standards. Furthermore, total cost of the prototype models, which is one of the major objectives of this research, is comparable with market prices.

Approved for public release; distribution is unlimited<br>Next-generation U.S. Navy destroyers, known as DD(X), will use electric drive motors to meet their propulsion needs instead of the traditional mechanical drives. The use of electric drive motors in naval vessels has spurred the development of high power converters. This thesis examines the feasibility of using an advanced control algorithm known as Sine-triangle Pulse Width Modulation (SPWM) in combination with a Cascaded Multi-Level Converter (CMLC) in order to meet the U.S. Navy's strict requirements. The SPWM control algorithm was designed in Simulink and experimentally tested on a CMLC previously constructed at the Naval Postgraduate School. The controller and converter successfully powered a quarter horsepower three-phase induction motor.<br>Ensign, United States Navy

A new power conditioning system (PCS) for superconductive magnetic energy storage (SMES) is developed and its prototype test system is built and tested. The PCS uses IGBTs for high-speed PWM operation and has a multi-level chopper-VSC structure. The prototype test system has three-level that can handle up to 250-kVA with a 1800-V DC link, a 200-A maximum load current , and a switching frequency reaching 20-kHz with the help of zero-current-transition (ZCT) soft-switching. This PCS has a great number of advantages over conventional ones in terms of size, speed, and cost. Conventional PCSs use thyristors, due to the power capacity of the SMES system. The speed limit of the thyristor uses a six-pulse operation that generates a high harmonic. To reduce the harmonic, multiple PCSs are connected together with phase-matching transformers that need to be precise to be effective in reducing the harmonics. So, the system becomes large and expensive. In addition, the dynamic range of the PCSs are also limited by the six-pulse operation, because it limits the useful area of the PCS applications. By employing a high-speed PWM, the new PCS can reduce the harmonics without using the transformers reducing size and cost, and has wide dynamic range. However, the speed of a switching device is generally inversely proportional to its power handling capacity. Therefore, employing a multi-level structure is one method of extending the power-handling capability of the high-speed device. Switching loss is another factor that limits the speed of the switch, but it can be reduced by soft-switching techniques. The 20-kHz switching frequency can be obtained with the help of the ZCT soft-switching technique, which can reduce about 90% of switching losses from the IGBT during both turn-on and turn-off transients. There are two different topologies of the PCS; the current source converter (CSC) type and the chopper and voltage source converter (VSC) type. In terms of the SMES system efficiency, the chopper-VSC type shows a less volt-ampere requirement of the power device. Therefore, the new PCS system has a chopper-VSC structure. Since the chopper-VSC structure consists of multiple legs that can be modularized, a power electronics building block (PEBB) leg is a good choice; all of the system problems caused by the high frequency can be solved within the PEBB leg. The VSC is built with three of the PEBB legs. Three-phase AC is implemented with a three-level space vector modulation (SVM) that can reduce the number of switching and harmonic contents from the output current. A closed-loop control system is also implemented for the VSC, and shows 600-Hz control bandwidth. The multi-level structure used requires too many high-speed switches. However, not all of them are used at the same time during normal multi-level operation. A new multi-level topology is suggested that requires only two high-speed switches, regardless of the number of levels. Other switches can be replaced with slow-speed switches that can allow additional cost savings.<br>Ph. D.

This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.

This thesis describes multilevel converters (MLC) designed for use with a repurposed electronic vehicle battery (battery 2nd life). MLC is of particular interest due to the low harmonic distortion content and reduced voltage stress in the switching devices. A detailed study of the MLC topologies and modulation techniques is presented. Space vector modulation is analysed and implemented to evaluate the converter. A comprehensive assessment of the MLC is presented using wide bandgap (WBG) devices highlighting the devices’ thermal and high switching frequency features.

High power multi-level converters are deemed as the mainstay power conversion technology for renewable energy systems including the battery storage system, PV farm and electrical vehicle charge station. This thesis is focused on the study of three-level DC/DC converter with multi-phase interleaved structure, with coupled and integrated magnetics to achieve high power density. The proposed interleaved phased legs offer the benefit of output current ripple reduction, while inversed coupled inductors can suppress the circulating current between phase legs. Compared with conventional non-interleaving three-level DC/DC converter with non-coupling inductors, both inductor current ripple and output current ripple are largely reduced by interleaving with inverse-coupled inductors. Because of the non-linearity of the inductor coupling, the equivalent circuit model is developed for the proposed interleaving structure. The model identifies the existence of multiple equivalent inductances during one switching cycle. A combination of them determines the inductor current ripple and dynamics of the system. By virtue of inverse coupling and means of controlling the coupling coefficients, one can minimize the current ripple and the unwanted circulating current. To further reduce the magnetic volume, the four inductors in two-phase three-level DC/DC converter are integrated into one common structure, incorporating the negative coupling effects. The integrated magnetic structure can effectively suppress the circulating current and reduce the inductor current ripple and it is easy to manufacture. This thesis provides an equivalent circuit model to facilitate the design optimization of the integrated system. A prototype of integrated coupled inductors is assembled with nano-crystalline C-C core and powder block core. It is tested with both impedance analyzer and single pulse tester, to guarantee proper mutual inductance for inductor current ripple and output current ripple target. With a two-phase three-level DC/DC converter hardware, the concept of integrated coupled inductors is verified, showing its good performance in high-voltage, high-power conversion applications.<br>Master of Science

A DC power distribution system (PDS) of a transport aircraft was modeled and analyzed using MATLAB/Simulink software. The multi-level modeling concept was used as a modeling approach, which assumes modeling subsystem of the PDS at three different levels of complexity. The subsystem models were implemented in Simulink and combined into the whole PDS model according to certain interconnection rules. Effective modeling of different scenarios of operation was achieved by mixing subsystem models of different levels in one PDS model. Linearized models were obtained from the nonlinear PDS model for stability analysis and control design. The PDS model was used to examine the system stability and the DC bus power quality under bidirectional power flow conditions. Small-signal analysis techniques were employed to study stability issues resulting from subsystem interactions. The DC bus stability diagram was proposed for predicting stability of the PDS with different types of loads without performing an actual stability test based on regular stability analysis tools. Certain PDS configurations and operational scenarios leading to instability were identified. An analysis of energy transfer in the PDS showed that a large energy storage capacitor in the input filter of a flight control actuator is effective for reduction of the DC bus voltage disturbances produced by regenerative action of the actuator. However, energy storage capacitors do not provide energy savings in the PDS and do not increase its overall efficiency.<br>Master of Science

L’objectif de ce travail de Thèse est d’évaluer les capacités de composants numérique de type Système-sur-Puce (SoC en anglais) pour l’implantation de Simulateurs Temps Réel Embarqués (ERTS en anglais) de systèmes électromécaniques et d’électronique de puissance. En effet, l’utilisation de ces simulateurs n’est pas seulement limitée aux validations matériel dans la boucle (en anglais Hardware-in-the-Loop ou HIL) du système mais doivent également être embarqués avec le contrôleur afin d’assurer plusieurs fonctionnalités additionnelles comme l'observation, l'estimation, commande sans capteur (ou sensorless), le diagnostic ou la surveillance de la santé, commande tolérante aux défauts, etc.La réalisation de ces simulateurs doit néanmoins considérer plusieurs contraintes à plusieurs niveaux de développement : durant la modélisation de la partie du système à simuler en temps-réel, durant la réalisation numérique et enfin durant l’implantation sur le composant numérique utilisé. Ainsi, le travail réalisé durant cette Thèse s’est focalisé sur ce dernier niveau et l’objectif était d’évaluer les capacités temps/ressources des composants de type SoC pour l’implantation de modules ERTS. Ce type de plateformes intègrent dans un même composant de puissants processeurs, un circuit logique programmable (de type Field-Programmable Gate Array ou FPGA), et d’autres périphériques, ce qui offre plusieurs opportunités d’implantation.Afin de pallier les limitations liées au codage VHDL de la partie FPGA, il existe des outils High-Level Synthesis (HLS) qui permettent de programmer ces dispositifs en utilisant des langages à haut niveau d'abstraction comme C, C++ ou SystemC. De plus, en incluant des directives et contraintes au code source, ces outils peuvent produire des implémentations matérielles différentes (architecture totalement combinatoire, « pipeline », architecture parallélisées ou factorisées, arranger les données et leurs formats pour une meilleure utilisation des ressources de mémoire, etc.).Dans le but d’évaluer ces différentes implantations, deux cas d’études ont été choisis : le premier se compose d’un Générateur Asynchrone à Double Alimentation (GADA) et le second d’un Convertisseur Modulaire Multiniveau (ou Modular Multi-level Converter - MMC). Vu que la GADA a une dynamique basse/moyenne (dynamiques électriques et mécaniques), deux versions d’implantations ont été évaluées : (i) une implantation full-software en utilisant seulement les processeurs ARM; et (ii) une implantation full-hardware en utilisant l’outil HLS pour programmer la partie FPGA. Ces deux versions ont été évaluées avec différentes optimisations du compilateur et trois formats de données: 64/32-bit en virgule flottante, et 32-bit en virgule flottante. L’approche mixe software/hardware a également été évaluée à travers la caractérisation des transferts de données entre le processeur et l’IP ERTS implantée dans la partie FPGA. Quant au convertisseur MMC, sa complexité et sa forte dynamique (dynamique de commutation) impose une implantation exclusivement full-hardware. Celle-ci a également été réalisée à base d’outils HLS.Enfin pour la validation expérimentale de ce travail de Thèse, une maquette à base de convertisseur MMC a été construite dans le but de comparer des mesures du système réel avec les résultats fournis par l’IP ERTS<br>This Doctoral Thesis is a detailed study of how suitable System-on-Chip (SoC) devices are for implementing Embedded Real-Time Simulators (ERTS) of electromechanical and power electronic systems. This emerging class of Real-Time Simulators (RTS) are not only expected for Hardware-in-the-Loop (HIL) validations of systems; but they also have to be embedded within the controller to play several roles like observers, parameter estimation, diagnostic, health monitoring, fault-tolerant and sensorless control, etc.The design of these Intellectual Properties (IP) must rigorously consider a set of constraints at different development stages: (i) during the modeling of the system to be real-time simulated; (ii) during the digital realization of the IP; and also (iii) during its final implementation in the digital platform. Thus, the conducted work of this Thesis focuses specially on this last stage and its aim is to evaluate the time/resource performances of recent SoC devices and study how suitable they are for implementing ERTSs. These kind of digital platforms combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling and monitoring a complete system.One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which needs extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ or SystemC. Moreover, by inserting directives and constraints to the source code, these tools can produce different hardware implementations (e.g. full-combinatorial design, pipelined design, parallel or factorized design, partition or arrange data for a better utilisation of memory resources, etc.).This dissertation is based on the implementation of two representative applications that are well known in our laboratory: a Doubly-fed Induction Generator (DFIG) commonly used as wind turbines; and a Modular Multi-level Converter (MMC) that can be arranged in different configurations and utilized for many different energy conversion purposes. Since the DFIG has low/medium system dynamics (electrical and mechanical ones), both a full-software implementation using solely the ARM processor and a full-hardware implementation using HLS to program the FPGA will be evaluated with different design optimizations and data formats (64/32-bit floating-point and 32-bit fixed-point). Moreover, it will also be investigated whether a system of these characteristics is interesting to be run as a hardware accelerator. Different data transfer options between the Processor System (PS) and the Programmable Logic (PL) have been studied as well for this matter. Conversely, because of its harsh dynamics (switching dynamics), the MMC will be implemented only with a full-hardware approach using HLS tools, as well.For the experimental validation of this Thesis work, a complete MMC test bench has been built from scratch in order to compare the real-world results with its SoC ERTS implementation

Dans les réseaux de distribution électrique et les réseaux intelligents, l'adoption généralisée des composants électroniques de puissance pose divers défis en matière de qualité de l'énergie. L'intégration des sources d'énergie renouvelable aggrave ces défis en raison des fluctuations de tension, des écarts de fréquence et de la distorsion des formes d'onde inhérents à ces sources, dont les performances dépendent des conditions météorologiques. Cette thèse aborde ces défis à travers trois solutions visant à améliorer la qualité de l'énergie électrique dans les réseaux de distribution, en se focalisant sur l'intégration des systèmes photovoltaïques (PV) dans la troisième solution.La première solution introduit une Structure Multi-Niveaux Développée du Convertisseur AC/DC/AC. Elle vise à réguler l'amplitude de tension, à garantir une tension de sortie en escalier approchant une sinusoïde et à éliminer un large rang d'harmoniques, y compris les harmoniques prédominantes affectant les charges sensibles telles que les entraînements de moteurs asynchrones. Ce travail développe une nouvelle technique de modulation pour contrôler la partie DC/AC du convertisseur, configurée via un onduleur en pont en H asymétrique en cascade.La deuxième solution implique un Système Avancé de Contrôle Hybride pour le Filtre Actif Parallèle (SAF) basé sur un Onduleur Multi-Niveaux (MLI). Cette solution améliore les performances du filtre actif parallèle, augmente sa fréquence de commutation apparente et réduit la taille de son filtre de couplage de sortie. Le contrôleur hybride, mis en œuvre à l'aide de réseaux de Petri (PN), assure un suivi de haute performance du courant de compensation, en plus de stabiliser, contrôler et équilibrer les tensions DC sur les entrées d'onduleur multi-niveaux. Une stabilité pratique des erreurs de tension continue est prouvée via le théorème de Lyapunov. Cette solution est explorée pour n modules en pont en H par phase, et les validations de mesure réelle et de simulation sont testées pour 2 et 3 modules dans un milieu industriel réel pour prouver son efficacité.La troisième solution présente une Structure PV connectée au réseau avec Filtre Actif Parallèle (SAF) basé sur un Onduleur Multi-Niveaux (MLI). Cette configuration améliore la qualité de l'énergie électrique et fournit de l'énergie renouvelable pour les charges et le réseau. Les entrées DC de l'onduleur multi-niveaux sont connectées directement aux sous-systèmes PV ou via des convertisseurs DC-DC. Des contrôleurs linéaires établissent la stratégie de contrôle du filtre actif parallèle basée sur (n) modules en pont H, comprenant l'injection de courant de compensation, la maximisation de la puissance produite par le système PV et la régulation des tensions DC sur les condensateurs. La modulation par largeur d'impulsion multi-porteuses assure une distribution équilibrée de l'énergie entre les modules. Des algorithmes de suivi du point de puissance maximale (MPPT), tels que Perturber et Observer (P&amp;O), avec trois stratégies de contrôle comprenant le contrôleur proportionnel intégral, le rapport cyclique, et la commande prédictive (MPC), maximisent la génération d'énergie du sous-système PV. Le convertisseur DC-DC utilise des techniques de modulation PWM pour maintenir une fréquence de commutation constante.Les performances des trois solutions sont validées dans une usine textile souffrant d'impacts harmoniques sur la principale machine textile, représentant une charge sensible de 50 kVA, fournie par un entraînement de moteur asynchrone. Cet entraînement de moteur est sensible aux rangs prédominants du couple et des harmoniques de tension, nécessitant un contrôle approprié. Pour garantir des résultats fiables, des mesures sur site à l'aide d'appareils d'analyse de la qualité de l'énergie électrique sont collectées pour modéliser numériquement le réseau de l'usine. Les performances de chaque solution sont étudiées sur la charge sensible de cette usine textile<br>In the electrical distribution networks and smart grids, the widespread adoption of power electronics components among customer loads poses diverse challenges to power quality. The integration of renewable energy sources further exacerbates these challenges due to voltage fluctuations, frequency deviations, and waveform distortion inherent in these sources, significantly dependent on weather conditions. This thesis addresses these challenges through three distinct solutions for power quality improvement in distribution networks, focusing on integrating renewable energy sources, particularly photovoltaic (PV) systems, in the third solution.The first solution introduces a developed multi-level structure of an AC/DC/AC Converter. This solution aims to regulate voltage amplitude, ensure sinusoidal-like output stepping voltage, and mitigate a wide range of harmonics, including the predominant harmonics affecting sensitive loads such as asynchronous motor drives. To address these aspects, this work develops a novel modulation technique to control the DC/AC part of the converter, configured via an Asymmetrical Cascaded H-Bridge Inverter.The second solution involves an Advanced Hybrid Control System Developed for Shunt Active Filter Based on a Multi-Level Inverter. This solution improves the performance of the shunt active filter, raises its apparent switching frequency, and reduces the size of its output coupling filter. The hybrid controller, implemented using Petri Nets (PNs), ensures high-performance tracking of the compensating current, in addition to stabilizing, controlling, and balancing the DC voltages across the MLI inputs. The practical stability of the DC voltage errors is analytically proved via the Lyapunov theorem. This solution is explored in detail for n H-Bridge modules per phase, with real measurement and simulation validations evaluated for 2 and 3 H-Bridge modules per phase within a real industrial environment to prove the structure's effectiveness.The third solution presents a Grid-Connected PV Structure Incorporated with a Shunt Active Filter Based on a Multi-Level Inverter. This configuration enhances power quality and provides renewable energy for both loads and the grid. The DC inputs of the multi-level inverter are connected directly to PV subsystems or via DC-DC converters. Linear controllers are employed to establish the control strategy for the shunt active filter based on (n) H-bridge modules, including injecting compensating current, maximizing the produced power of the PV system, and regulating DC voltages across capacitors. Multi-carrier PWM modulation ensures balanced power distribution among the modules. Maximum Power Point Tracking (MPPT) algorithms, such as Perturb &amp; Observe (P&amp;O), with three control strategies including Proportional Integral, Duty-cycle, and Model Predictive Controller, are employed to maximize PV subsystem power generation. Additionally, the DC-DC converter utilizes PWM modulation techniques across all three control strategies to maintain a consistent switching frequency.The performance of the three aforementioned solutions is validated, for finite HB modules, within a textile factory suffering from harmonic impact on the main textile machine, which represents a sensitive load of 50 kVA, driven by an asynchronous motor. This motor drive is highly sensitive to predominant torque and voltage harmonics, requiring appropriate control of the fundamental output voltage amplitude and the phase and amplitude of the harmonic voltage components. This control system is particularly designed to regulate motor speed variation and mitigate undesired fluctuations caused by harmonic torques. To ensure reliable results, on-site measurements using power quality analyzer devices are collected to create a numerical model of the entire factory's network. Finally, the performance of each solution is investigated on the sensitive load operating within this textile factory

Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée<br>This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis

Cette thèse traite des convertisseurs de puissance multi-niveaux destinés aux applications d’entraînements électriques, utilisés notamment dans le domaine de l’Oil &amp; Gas et de la propulsion marine, ou bien aux applications réseaux comme la compensation de l’énergie réactive. L’objectif est l’optimisation des commandes de ces convertisseurs de façon à réduire le contenu harmonique de la tension de sortie et donc du courant, paramètre très important pour le dimensionnement à la fois des filtres de sortie et des machines électriques qui y sont connectées. Dans la première partie de ce mémoire, les différentes topologies multi-niveaux sont analysées et trois topologies cinq niveaux retenues sont comparées en termes de nombre de composants semi-conducteurs, des pertes, du contenu harmonique et de l’énergie stockée dans les éléments passifs. Selon le type de l’application, l’une d’entre elles est préférée aux autres. En deuxième partie, nous avons proposé une méthode de réduction d’harmoniques basse fréquence qui consiste à maîtriser la phase des porteuses MLI pour des ratios entiers des fréquences de découpage et du fondamentale de la tension de référence. La minimisation des harmoniques basse fréquence de la tension de sortie du convertisseur par l’optimisation de la phase des porteuses est validée d’abord par des simulations numériques puis implémentée pratiquement et validée à l’aide d’un simulateur temps réel RT-Lab. Pour pallier aux problèmes de non-linéarités introduites par les méthodes classiques de ”clamping” des tensions de références des convertisseurs multi-niveaux, limitant l’amplitude de la tension de sortie maximale atteignable, nous proposons une nouvelle méthode de linéarisation en dernière partie de ce mémoire. Il s’agit d’ajouter une composante homopolaire optimisée aux tensions de références des convertisseurs multi-niveaux pour linéariser le fondamental de leurs tensions de sortie, ce qui permet d’accroître le maximum de leur amplitude. Cette méthode est testée par simulation numérique dans la commande d’un système d’entraînement électrique complet lui permettant de fonctionner sur toute la plage de vitesse, sans affecter l’équilibrage des tensions des capacités du bus continu principal<br>This thesis deals with multi-level power converters for electrical drive applications, used in particular in the field of Oil &amp; Gas and marine propulsion, or for network applications such as reactive energy compensation. The objective is to optimize the controls of these converters in order to reduce the harmonic content of the output voltage and therefore of the current, a very important parameter for the sizing of both the output filters and the electrical machines connected to them. In the first part of this thesis, the different multi-level topologies are analyzed and three selected five-level topologies are compared in terms of the number of semiconductor components, losses, harmonic content and the energy stored in the passive elements. Depending on the application type, one of them is preferred over the others. In the second part, we proposed a method for reducing low frequency harmonics of the multilevel converter output voltage, which consists in controlling the phase of the PWM carriers for integer ratios of the switching frequency and the fundamental frequency. The minimization of low-frequency harmonics of the converter output voltage by optimizing the carrier phase is first validated by numerical simulations and then practically implemented and validated using a real time simulator RT-Lab. To overcome the problems of non-linearities introduced by the classical clamping methods of the reference voltages of multi-level converters, limiting the amplitude of the maximum achievable output voltage, we propose a new linearization method in the last part of this thesis. This involves adding an optimized zero-sequence component to the reference voltages of multi-level converters to linearize the fundamental of their output voltages, which makes it possible to increase their amplitude to its maximum achievable value. This method is tested by numerical simulation in the control of a complete electric drive system allowing it to operate over the entire speed range, without affecting the voltage balancing of the main DC bus capacitors

Die vorliegende Arbeit behandelt den Modularen Mehrpunktstromrichter M2C, der eine aufstrebende Mehrpunktstromrichtertopologie im Mittelspannungs- und Hochspannungsbereich ist. Die modulare Struktur des Stromrichters enthält in einem Stromrichterzweig eine Reihenschaltung aus identischen Submodulen (Zellen) und einer Spule. Der gesamte Stromrichter ist aus sechs Zweigen aufgebaut. Somit hängt die Anzahl der Spannungsstufen in den Leiter-Leiter-Spannungen von der zunächst beliebigen Anzahl der Submodule ab. Zur Untersuchung dieser komplexen Stromrichtertopologie werden zwei Simulationsmodelle hergeleitet: das kontinuierliche Modell und das diskrete Modell. Dafür wird das elektrische Schaltbild durch ein gewöhnliches Differenzialgleichungssystem beschrieben, wobei die Schaltzustände der Leistungshalbleiter durch sogenannte Schaltfunktionen abgebildet werden. Das kontinuierliche Modell verwendet Schaltfunktionen, die Werte in einem kontinuierlichen Intervall annehmen können. Bei Vorgabe der Zweigströme und Sternpunktspannung können die Lösungen der anderen Systemgrößen analytisch berechnet werden. Für den allgemeinen Fall ist dies numerisch möglich. Im Gegensatz dazu verwendet das diskrete Modell diskrete Schaltfunktionen. Es wird durch numerische Integrationsverfahren mit dem Schaltungssimulator MATLAB/Plecs simuliert. Eine spezielle Eigenschaft dieses Stromrichters sind seine inneren, an den Ein- und Ausgangsklemmen nicht messbaren Ströme: die sogenannten Kreisströme. Diese Stromanteile werden erstmalig mathematisch im Zeitbereich definiert und die Harmonischen hergeleitet, die sich für einen symmetrischen Betrieb des Stromrichters ergeben. Für das diskrete Modell wird eine Zweigstromregelung implementiert. Die Anfangswerte der Spulen und Kondensatoren werden durch die analytischen Gleichungen des kontinuierlichen Modells so berechnet, dass sich der eingeschwungene Zustand ergibt. Der M2C besitzt keinen großen, sondern viele verteilte Energiespeicher: die Submodulkondensatoren. Die gespeicherte Energie sollte symmetrisch verteilt sein. Dafür werden drei Möglichkeiten der Energieänderung hergeleitet und deren Effektivität gezeigt. Eine andere Untersuchung betrifft die Stromaufteilung innerhalb der Submodule auf den jeweils oberen und unteren Leistungshalbleiter. Dabei wird die Stromaufteilung für verschiedene Phasenwinkel und Kreisströme gezeigt. Der Einfluss der schwankenden Kondensatorspannungen auf die Leiter-Leiter-Spannungen sowie die Anzahl der Spannungsstufen in den Leiter-Leiter-Spannungen werden mit dem diskreten Modell untersucht. Die Genauigkeit der Simulationsmodelle wird mit Hilfe eines Prototyps des M2Cs überprüft, der von der Fa. Siemens entwickelt wurde. Es werden charakteristische Strom- und Spannungsverläufe gemessen und den simulierten Verläufen der beiden Simulationsmodelle gegenübergestellt. Die Auslegung des Leistungsteils gliedert sich in die Auslegung der Submodulkondensatoren und die der Leistungshalbleiter. Zuerst wird die Kapazität der Submodulkondensatoren auf der Grundlage von drei verschiedenen Kondensatorspezifikationen mit Hilfe eines iterativen Algorithmus minimiert. Dies wird sowohl für kreisstromfreie als auch für optimierte kreisstrombehaftete Betriebsweisen mit dem kontinuierlichen Modell durchgeführt. Im nächsten Schritt werden die Leistungshalbleiter mit dem diskreten Modell dimensioniert. Dafür wird ein Stromfaktor definiert, der eine ideale Parallelschaltung von mehreren Leistungshalbleitern beschreibt. Die Verluste, die Verlustverteilung sowie die Sperrschichttemperaturen in den Leistungshalbleitern für verschiedene Phasenwinkel zeigen das Verhalten des Stromrichters in verschiedenen Arbeitspunkten<br>This thesis deals with the Modular Multilevel Converter M2C, an emerging and highly attractive multilevel converter topology for medium and high voltage applications. One of the most significant benefits of the M2C is its modular structure - the converter is composed of six converter arms, where each arm consists of a series connection of identical submodules (cells) and an inductor. Thus, the number of distinct voltage levels available for the line-to-line voltages is proportional to the number of submodules, which is in principle arbitrary. For the investigation of this complex converter topology, two simulation models - a continuous model and a discrete model - are derived. For this purpose, the electrical circuit is described by a system of ordinary differential equations where the switching states of the power semiconductors are represented by the so-called switching functions. The continuous model results from the analytical solution of the differential equations with a continuous interpretation of the switching functions. In contrast, the discrete model uses discrete switching functions and is computed using numeric integration methods with MATLAB/Plecs. One aspect of particular significance with the M2C is the topic of inner currents: the so-called circulating currents. In this thesis, these current components are defined mathematically in the time domain for the first time and the harmonics of the circulating currents for symmetrical operation of the converter are derived. For the discrete model, closed-loop control of the arm currents is implemented. Initial values for the inductors and capacitors are derived using the analytical equations of the continuous model. The M2C has several distributed energy storage elements: the submodule capacitors. The stored energy must be distributed evenly amongst these capacitors. To achieve this, three methods of energy distribution are presented. Another focus of this investigation is the current sharing between the upper and lower power semiconductor within the submodules. For different load phase angles and circulating currents, the current distribution is depicted. The influence of the floating capacitor voltages on the line-to-line voltages as well as the of number of discrete voltage levels in the line-to-line voltages are investigated with the discrete model. The accuracy of the simulation models is verified by experimentation with a prototype of the M2C from the company Siemens. The experimental results are compared with simulation results from the two simulation models. The dimensioning of the power components of the elecrical circuit is divided into two parts: the first for the submodule capacitors and the second for the power semiconductors. Initially, the capacitance of the submodule capacitors are minimized by an iterative algorithm on the basis of three different capacitor specifications. This computation is done using the continuous converter model for converter operation neglecting circulating currents and with optimized circulating currents. In the next step, the power semiconductors are dimensioned using the discrete model and assuming a defined current factor, which describes the ideal parallel connection of several semiconductors. The losses, the loss distribution, and the junction temperatures in the power semiconductors for different load phase angles describe the behavior of the converter for different operating points

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

Multi-level converters that provide more than two levels of voltage to achieve an output waveform closer to sinusoidal waveform with less distortion are very attractive to power applications. This thesis investigates several multi-level converter topologies and different modulation strategies such as pulse-width modulation and space vector modulation. Attention is paid in particular to SVM strategy. Although SVM strategy is applicable for N-level converter, this thesis only focuses on five-level and three-level diode clamped converter (DCC). Despite their appealing harmonic spectrum and low losses, multi-level converters are known to suffer from inherent voltage imbalance on their dc side. The thesis presents a method in order to balance the dc side capacitor voltages for an N-level converter. The presented balancing method is based on minimizing a cost function which is related to voltage divergence of the dc capacitors. This method is used for a three-level SVM to overcome the voltage drifting problem.

This thesis presents and investigates Space Vector Modulation (SVM) switching strategies for (i) a multi-level Diode-Clamped Converter (DCC) and (ii) a multi-module Voltage-Sourced Converter (VSC) system in which each module is a conventional two-level VSC. Although the SVM strategies are general and applicable for n-level DCC and n-module VSC systems, this text only concentrates on five-level DCC and four-module VSC systems. For a five-level DCC, a computationally efficient SVM algorithm is proposed. The algorithm, that is based on a classifier Neural Network (NN), reduces the computational time for the SVM realization. Therefore, adequate saving of processor execution time, in each sampling period of SVM, is provided to carry out other functions, e.g. the calculations required for DC-capacitor voltage balancing task. The thesis also proposes a DC-capacitor voltage balancing strategy to counteract the voltage drift phenomenon of (i) a passive-front-end five-level DCC, and (ii) a back-to-back connected five-level DCC system. The proposed balancing strategy, that is based on augmenting the proposed SVM algorithm, takes advantage of the redundant switching states to minimize a quadratic cost function associated with voltage deviations of the DC-capacitors. The salient features of the proposed balancing strategy are (i) online calculation of SVM to select the best switching states, (ii) minimization of switching frequency, (iii) minimization of the THD content of the AC-side voltage, and (iv) no requirement for additional power circuitry. For a four-module VSC system a sequential sampling SVM strategy is proposed. The proposed strategy (i) provides harmonic cancellation/minimization at the net AC-side voltage of the multi-module VSC system, and (ii) offers a low switching frequency for each VSC module. Technical feasibility of the proposed SVM strategies for a five-level DCC and a four-module VSC system, as a STATCOM and a back-to-back HVDC system, are investigated and presented. The studies are conducted in the time-domain, in the PSCAD/EMTDC software environment.

碩士<br>國立雲林科技大學<br>電機工程技術研究所<br>87<br>This paper presents a novel current control for the single-phase three-level converter. The control scheme is based on the hysteresis current control and look-up table to achieve high input power factor and balanced capacitor voltages. Software program based on Matlab/Simulink was used to simulate and analysis the proposed control method. A laboratory prototype was built to verify the characteristics of unity power factor and low harmonic current.

Among the multilevel (ML)-voltage source converters (VSCs) for medium voltage (MV) and high power (HP) applications, the most used power topology is the three level (3L)-neutral point clamped (NPC)-VSC, due to its features such as common direct current (DC)-bus capability with medium point, absence of switches in series-connection, low part count, and straightforward control. The use of MV-insulated gate bipolar transistor (IGBT) modules as power switches offers further advantages like inexpensive gate drivers and survival capability after short-circuit. However, the IGBT modules have a reduced life cycle due to thermal stress generated by load cycles. Despite the advantages of the 3L-NPC-VSC, its main drawback is the uneven power loss distribution among its power devices. To address this issue and to improve other characteristics, more advanced ML converters have been developed. The 3L-active neutral point clamped (ANPC)-VSC allows an improved power loss distribution thanks to its additional IGBTs, which increase the number of feasible zero-states, but needs a loss balancing scheme to choose the proper redundant zero-state and a more complex commutation sequence between states. The 3L-neutral point piloted (NPP)-VSC improves the power loss distribution thanks to the use of series-connected switches between the output terminal and the positive and negative DC-link terminals. Other advanced power topologies with higher amount of levels include the 5L-ANPC-VSC, which has a flying capacitor per phase to generate the additional levels; and the 5L-stacked multicell converter (SMC), which needs two flying capacitors per phase. The goal of this work is to is to evaluate the performance of the aforementioned NPC-type ML converters with common DC-link, included the ones with flying capacitors, in terms of the power loss distribution and the junction temperature of the most stressed devices, which define, along with the nominal output voltage, the maximum power the converter can deliver. A second objective of this work is to describe the commutations of a MV 3L-ANPC-VSC phase leg prototype with IGBT modules, including all the intermediate switching states to generate the desired commutations.:Figures and Tables V Glossary XIII 1. Introduction 1 2. State of the art of medium voltage source converters and power semiconductors 5 2.1. Overview of medium voltage source converters 5 2.1.1. Multilevel Voltage Source Converter topologies 6 2.1.2. Application oriented basic characteristic of IGCTs and IGBTs 10 2.1.3. Market overview of ML-VSCs 11 2.2. IGBT modules for MV applications 12 2.2.1. Structure and Function 12 2.2.2. Electrical characteristics of the IGBT modules 15 2.2.3. Power losses and junction temperatures estimation 17 2.2.4. Packaging 19 2.2.5. Reliability and Life cycle of IGBT modules 21 2.2.6. Market Overview 23 2.3. Summary of Chapter 2 23 3. Structure, function and characteristics of NPC-based VSCs 25 3.1. The 3L-NPC-VSC 25 3.1.1. Power Topology 25 3.1.2. Switching states, current paths and blocking voltage distribution 26 3.1.3. Modulation of three-level inverters 28 3.1.4. Power loss distribution 32 3.1.5. “Short” and “long” commutation paths 33 3.2. The 3L-NPP-VSC 34 3.2.1. Power Topology 34 3.2.2. Switching states, current paths and blocking voltage distribution 35 3.2.3. Power Loss distribution 36 3.3. The 3L-ANPC-VSC 37 3.3.1. Power Topology 37 3.3.2. Switching states, current paths and blocking voltage distribution 38 3.3.3. Commutations and power loss distribution 39 3.3.4. Loss balancing schemes 57 3.4. The 5L-ANPC-VSC 60 3.4.1. Power Topology 60 3.4.2. Switching states, current paths and blocking voltage distribution 61 3.4.3. Commutation sequences 62 3.4.4. Power Loss distribution 70 3.4.5. Modulation and balancing strategies of capacitor voltages 70 3.5. The 5L-SMC 74 3.5.1. Power Topology 74 3.5.2. Switching states, current paths and blocking voltage distribution 75 3.5.3. Commutations and power loss distribution 78 3.5.4. Modulation and balancing strategies of capacitor voltages 80 3.6. Summary of Chapter 3 81 4. Comparative evaluation and performance of NPC-based converters 83 4.1. Motivation and goal of the comparisons 83 4.2. Basis of the comparison 83 4.2.1. Simulation scheme 85 4.2.2. Losses and thermal models for (4.5 kV, 1.2 kA) IGBT modules 86 4.2.3. Operating points, modulation, controllers and general parameters 88 4.2.4. Life cycle estimation 94 4.3. Simulation results of the 3.3 kV 3L-VSCs 97 4.3.1. Loss distribution and temperature at equal phase current 97 4.3.2. Maximum phase current 109 4.3.3. Life cycle 111 4.4. Simulation results of the 6.6 kV 5L and 3L-VSCs 115 4.4.1. Loss distribution and temperature at equal phase current 115 4.4.2. Maximum phase current 120 4.4.3. Life cycle 128 4.5. Summary of Chapter 4 132 5. Experimental investigation of the 3L-ANPC-VSC with IGBT modules 135 5.1. Goal of the work 135 5.2. Description of the 3L-ANPC-VSC test bench 136 5.2.1. Medium voltage stage 136 5.2.2. Gate drivers and digital signal handling 138 5.2.3. Measurement equipment 139 5.3. Double-pulse test and commutation sequences 140 5.3.1. Description of the double-pulse test for the 3L-ANPC-VSC 140 5.3.2. Commutation sequences for the double-pulse test 142 5.4. Commutation measurements 142 5.4.1. Switching and transition times 144 5.4.2. Type I commutations 145 5.4.3. Type I-U commutations 150 5.4.4. Type II commutations 150 5.4.5. Type III commutations 157 5.4.6. Comparison of the commutation times 157 5.4.7. Stray inductances of the “short” and “long” commutations 163 5.5. Summary of Chapter 5 167 6. Conclusions 169 Appendices 173 A. Thermal model of IGBT modules 175 A.1. General “Y” model 175 A.2. “Foster” thermal circuit 177 A.3. “Cauer” thermal circuit 178 A.4. From “Foster” to “Cauer” 179 A.5. Temperature comparison using “Foster” and “Cauer” networks 181 B. The “Rainflow” cycle counting algorithm 183 C. Description of the wind generator example 187 C.1. Simulation models 188 C.1.1. Wind turbine 188 C.1.2. Synchronous generator, grid and choke filter 189 C.1.3. Converters 189 C.2. Controllers 190 C.2.1. MPPT scheme 190 C.2.2. Pitch angle controller 191 C.2.3. Generator side VSC 192 C.2.4. Grid side VSC 193 D. 3D-surfaces of the maximum load currents in NPC-based converters 195 Bibliography 201 Bibliography 201<br>Unter den Multilevel-Spannungsumrichtern für Mittelspannungs- und Hochleistungsanwendungen ist die am häufigsten verwendete Leistungstopologie der NPC-VSC, wegen seinen Merkmalen wie die Gleichstrom-Bus fähigkeit mit mittlerem Punkt, das Fehlen von Schaltern in Reihenschaltung, eine geringe Anzahl von Bauteilen und eine einfache Steuerung. Die Verwendung von Bipolartransistor Modulen mit isolierter Gate-Elektrode als Leistungsschalter bietet weitere Vorteile wie kostengünstige Gatetreiber und Überlebensfähigkeit nach einem Kurzschluss. Die IGBT-Module haben jedoch aufgrund der durch Lastzyklen erzeugten thermischen Belastung eine verkürzte Lebensdauer. Trotz der Vorteile des 3L-NPC-VSC ist der Hauptnachteil die ungleichmäßige Verteilung der Leistungsverluste zwischen den Leistungsgeräten. Um dieses Problem zu beheben und andere Eigenschaften zu verbessern, wurden fortgeschrittenere ML-Konverter entwickelt. Das 3L-ANPC-VSC ermöglicht dank seiner zusätzlichen IGBTs eine verbesserte Verlustleistungsverteilung, wodurch die Anzahl der möglichen Null-Zustände erhöht wird, es ist jedoch ein Verlustausgleichsschema erforderlich, um den richtigen redundanten Null-Zustand, und benötigt auszuwählende komplexere Kommutierungssequenz zwischen Zuständen. Das 3L-NPP-VSC verbessert die Verlustleistungsverteilung durch die Verwendung von in Reihe geschalteten Schaltern zwischen der Ausgangsklemme und den positiven und negativen Zwischenkreisklemmen. Andere fortgeschrittene Leistungstopologien mit einer höheren Anzahl von Stufen umfassen den 5L-ANPC-VSC, der pro Phase einen fliegenden Kondensator zur Erzeugung der zusätzlichen Stufen aufweist; und den 5L-SMC, der pro Phase zwei fliegende Kondensatoren benötigt. Das Ziel dieser Arbeit ist es, die Leistung der oben genannten NPC-VSC, einschließlich der mit fliegenden Kondensatoren, hinsichtlich der Verlustleistungsverteilung und der Sperrschichttemperatur der am stärksten beanspruchten Geräte zu bewerten. Diese definieren zusammen mit der Nennausgangsspannung die maximale Leistung, die der Umrichter liefern kann. Ein zweites Ziel dieser Arbeit ist die Beschreibung der Kommutierungen eines MV 3L-ANPC-VSC- Prototyps mit IGBT-Modulen einschließlich aller Zwischenschaltzustände, um die gewünschten Kommutierungen zu erzeugen.:Figures and Tables V Glossary XIII 1. Introduction 1 2. State of the art of medium voltage source converters and power semiconductors 5 2.1. Overview of medium voltage source converters 5 2.1.1. Multilevel Voltage Source Converter topologies 6 2.1.2. Application oriented basic characteristic of IGCTs and IGBTs 10 2.1.3. Market overview of ML-VSCs 11 2.2. IGBT modules for MV applications 12 2.2.1. Structure and Function 12 2.2.2. Electrical characteristics of the IGBT modules 15 2.2.3. Power losses and junction temperatures estimation 17 2.2.4. Packaging 19 2.2.5. Reliability and Life cycle of IGBT modules 21 2.2.6. Market Overview 23 2.3. Summary of Chapter 2 23 3. Structure, function and characteristics of NPC-based VSCs 25 3.1. The 3L-NPC-VSC 25 3.1.1. Power Topology 25 3.1.2. Switching states, current paths and blocking voltage distribution 26 3.1.3. Modulation of three-level inverters 28 3.1.4. Power loss distribution 32 3.1.5. “Short” and “long” commutation paths 33 3.2. The 3L-NPP-VSC 34 3.2.1. Power Topology 34 3.2.2. Switching states, current paths and blocking voltage distribution 35 3.2.3. Power Loss distribution 36 3.3. The 3L-ANPC-VSC 37 3.3.1. Power Topology 37 3.3.2. Switching states, current paths and blocking voltage distribution 38 3.3.3. Commutations and power loss distribution 39 3.3.4. Loss balancing schemes 57 3.4. The 5L-ANPC-VSC 60 3.4.1. Power Topology 60 3.4.2. Switching states, current paths and blocking voltage distribution 61 3.4.3. Commutation sequences 62 3.4.4. Power Loss distribution 70 3.4.5. Modulation and balancing strategies of capacitor voltages 70 3.5. The 5L-SMC 74 3.5.1. Power Topology 74 3.5.2. Switching states, current paths and blocking voltage distribution 75 3.5.3. Commutations and power loss distribution 78 3.5.4. Modulation and balancing strategies of capacitor voltages 80 3.6. Summary of Chapter 3 81 4. Comparative evaluation and performance of NPC-based converters 83 4.1. Motivation and goal of the comparisons 83 4.2. Basis of the comparison 83 4.2.1. Simulation scheme 85 4.2.2. Losses and thermal models for (4.5 kV, 1.2 kA) IGBT modules 86 4.2.3. Operating points, modulation, controllers and general parameters 88 4.2.4. Life cycle estimation 94 4.3. Simulation results of the 3.3 kV 3L-VSCs 97 4.3.1. Loss distribution and temperature at equal phase current 97 4.3.2. Maximum phase current 109 4.3.3. Life cycle 111 4.4. Simulation results of the 6.6 kV 5L and 3L-VSCs 115 4.4.1. Loss distribution and temperature at equal phase current 115 4.4.2. Maximum phase current 120 4.4.3. Life cycle 128 4.5. Summary of Chapter 4 132 5. Experimental investigation of the 3L-ANPC-VSC with IGBT modules 135 5.1. Goal of the work 135 5.2. Description of the 3L-ANPC-VSC test bench 136 5.2.1. Medium voltage stage 136 5.2.2. Gate drivers and digital signal handling 138 5.2.3. Measurement equipment 139 5.3. Double-pulse test and commutation sequences 140 5.3.1. Description of the double-pulse test for the 3L-ANPC-VSC 140 5.3.2. Commutation sequences for the double-pulse test 142 5.4. Commutation measurements 142 5.4.1. Switching and transition times 144 5.4.2. Type I commutations 145 5.4.3. Type I-U commutations 150 5.4.4. Type II commutations 150 5.4.5. Type III commutations 157 5.4.6. Comparison of the commutation times 157 5.4.7. Stray inductances of the “short” and “long” commutations 163 5.5. Summary of Chapter 5 167 6. Conclusions 169 Appendices 173 A. Thermal model of IGBT modules 175 A.1. General “Y” model 175 A.2. “Foster” thermal circuit 177 A.3. “Cauer” thermal circuit 178 A.4. From “Foster” to “Cauer” 179 A.5. Temperature comparison using “Foster” and “Cauer” networks 181 B. The “Rainflow” cycle counting algorithm 183 C. Description of the wind generator example 187 C.1. Simulation models 188 C.1.1. Wind turbine 188 C.1.2. Synchronous generator, grid and choke filter 189 C.1.3. Converters 189 C.2. Controllers 190 C.2.1. MPPT scheme 190 C.2.2. Pitch angle controller 191 C.2.3. Generator side VSC 192 C.2.4. Grid side VSC 193 D. 3D-surfaces of the maximum load currents in NPC-based converters 195 Bibliography 201 Bibliography 201

碩士<br>國立高雄應用科技大學<br>電機工程系博碩士班<br>106<br>This paper proposes two multi-level isolated DC-DC power converters based on two bridge rectifiers, which consists of a half-bridge DC-AC inverter, a high frequency transformer, two bridge rectifiers, a switching selection circuit, an output L-C filter and a digital signal processor(DSP) controller. Compared with the conventional isolated multi-level DC-DC power converters, the proposed power converters can reduce switching losses and output voltage ripple, and it can also reduce the capacity of output filter. Both symmetrical and asymmetrical high-frequency transformers are used in this paper, and it shows the topology using asymmetrical transformer can further reduce the output voltage ripple and the voltage stress in switches. The half-bridge rectifier are adopted in this paper, and it has the function of a voltage doubler. For the same output voltage, one of two output winding of three-winding transformer is half that of the other winding. It has advantage of reducing cost of winding cost of three-winding transformer. Both simulation and hardware tested of a 3.2kW prototype are used to verify that the performance of the proposed multi-level isolated DC-DC power converter based on two bridge rectifiers, Finally, the power devices of different materials were used for testing to understand which material had better efficiency in the circuit topology of this paper.

碩士<br>國立高雄科技大學<br>電機工程系<br>107<br>The renewable energy has the characteristics of unstable and intermittent, and it cause the fluctuation of voltage and frequency variation in the electric power feeder seriously affecting power quality. The energy storage system can improve the unstable and intermittent problems of renewable energy through the storage and release energy, and it can also adjust the power demand during the peak and off-peak periods. Therefore, the issue of energy storage gets more and more attention. This paper propose a low voltage battery energy storage system (BESS) based on new asymmetrical multi-level power converters. The low voltage BESS includes a bidirectional asymmetrical five-level DC-AC power converter and a new isolated bidirectional asymmetrical multi-level DC-DC power converter. Multi-level power converters have the advantages of lowing the switching voltage, reducing the switching loss and reducing the size of the filter. The DC-DC isolated power converter uses a transformer with the galvanic isolation, and it can match voltage level and avoid leakage current. Therefore, it is often used in applications where leakage current and voltage matching are needed. A prototype is developed to verify the performance of the developed energy storage system. The experimental results are as expected.

Multilevel converters are becoming more and more popular, overcoming some key limitations of conventional two-level structures in handling medium voltages and high voltage gradients. Today they provide the ground for the realization of high efficiency energy conversion systems for medium voltage applications, such as pumps, compressors, extruders, fans, grinding mills, rolling mills, conveyors, crushers, blast furnace blowers, gas turbine starters, mixers, mine hoists, reactive power compensation, marine propulsion, wind energy conversion, and railway traction. A detailed overview of multilevel converters is provided in Chapter 1, while, the state of the art of Open-end Winding Systems is described in Chapter 2. The last systems can be considered as special multilevel inverter structures, tailored around an electrical machine fed from both the ends of the stator, or primary, winding. Overvoltage phenomena generated in industrial motor drives at motor terminals by long feeding cables are investigated in Chapter 3 and an Open-end Winding configuration approach is presented to actively mitigate them. Moreover, an adaptive algorithm is described to make independent the active overvoltage mitigation from system parameters. The main contribution of this work is the development of a new multilevel inverter topology, the Asymmetrical Hybrid Multilevel Inverter (AHMLI), which is introduced in Chapter 4. According to the AHMLI structure, an open-end winding machine (motor, generator or transformer) is supplied on one end by a main multilevel converter, fully managing the active power stream, and, on the other end by an auxiliary two level inverter. This acts as an active power filter, suitably shaping the electrical machine phase current. A mathematical analysis of the proposed structure is first provided, followed by an exhaustive comparison between AHMLI and conventional multilevel structures, emphasizing advantages in terms of efficiency and output current THD. Voltage and current control systems, optimally coping with key characteristics of the AHMLI structure are carried out and an original input capacitors voltage equalization technique is also presented. The application of the AHMLI concept to industrial induction motor drives is then evaluated by simulation and experimental test. A possible exploitation of the AHMLI approach in the realization of photovoltaic and wind plants, as well as STATCOM devices is also assessed. Moreover, a high efficiency three phase rectifier for high speed generation systems exploiting the AHMLI configuration is carried out. Finally, the application of the AHMLI approach to Multiple Motor Drive systems is proposed in Chapter 5. Two new topologies are presented, namely: Open-end Winding Multi Motor Single Converter (MMSC) and Open-end Winding Multi Motor Multi Converter (MMMC). Both configurations exploit the AHMLI structure but the MMMC exploits a five-leg two level inverter to independently control the stator currents of two induction motors.

Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for the parallel MDFE. The differential current signals from the feedback equalizer are subtracted from the forward equalizer output at the summing node to cancel the non-causal ISI. A high-speed comparator with 6 bit resolution is used after the cancellation to detect the signal which contains no ISI. In this thesis, a description of the parallel MDFE structure and decision feedback equalization algorithm are presented. The design of a high-speed summing circuitry and a high-speed comparator are discussed. The same comparator design is used for the flash analog-to-digital converter (ADC) which generates error signals for adaptation.The circuits design and layout were carried out in an HP 1.2-��m n-well CMOS process.<br>Graduation date: 1998

碩士<br>國立暨南國際大學<br>電機工程學系<br>101<br>In this thesis, we implement two different audio amplifiers architecture, research target is purpose to improve better SNR and THD. This thesis can be divided two part： The first part, we use 0.18μm CMOS technology provided by TSMC, design a clock free class-D audio amplifier. In circuit architecture, we use a simple two-stage operation amplifier as a comparator, generating pulse width modulation. Make analog signal convert to digital signal, and reduce distortion situation, and through the power amplification circuit to increase the current, purpose to increase power of pulse width modulation. The last part is a low pass filter composition of inductance, capacitance and speaker. It can revert pulse width modulation to original analog signal, and drive to latter stage speaker load. The second part, this circuit is also use 0.18μm CMOS technology provided by TSMC, design a filterless class-D audio amplifier with multi-level converter. The basic architecture is multi-level signal. Multi-level architecture can roughly divided to five parts：1. Comparator 2.Shift registers 3.Combined full adder 4.Decoder 5.Multi-level converter. In this method, pulse width modulation signal is arrange too many time divisions and integrate into a binary form. Binary form is decoded to control signal for multi-level converter. Multi-level converter will convert multi-level signal to speaker, replace traditional two-stage signal. So improve THD and SNR without sacrificing power efficiency. Since, this work can be used in any class-D audio amplifier, designing by insert shift registers and adder behind modulator and replace output stage with multi-level converter.