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Relevant bibliographies by topics / Multichip modules (Microelectronics)

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Academic literature on the topic 'Multichip modules (Microelectronics)'

Author: Grafiati

Published: 4 June 2021

Last updated: 28 July 2024

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Journal articles on the topic "Multichip modules (Microelectronics)"

1

Wong, C. P., and M. M. Wong. "Recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics." IEEE Transactions on Components and Packaging Technologies 22, no. 1 (1999): 21–25. http://dx.doi.org/10.1109/6144.759349.

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Krueger, Daniel, John Porter, and Ken Peterson. "Stress and Strain Modeling of Low Temperature Cofired Ceramic (LTCC) Seal Frame and Lid." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, CICMT (2015): 000157–63. http://dx.doi.org/10.4071/cicmt-wa21.

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Low temperature cofired ceramic (LTCC) is established as an excellent packaging technology for high reliability, high density microelectronics. LTCC multichip modules (MCMs) comprising both ‘surface mount’ and ‘chip and wire’ technologies provide additional customization for performance. Long term robustness of the packages is impacted by the selection of seal frame and lid materials used to enclose the components inside distinct rooms in LTCC MCMs. An LTCC seal frame and lid combination has been developed that is capable of meeting the sealing and electromagnetic shielding requirements of MCMs. This work analyzes the stress and strain performance of various seal frame and lid materials, sealing materials, and configurations. The application for the MCM will impact selection of the seal frame, lid, and sealing materials based on this analysis.

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Goeke, R. S., R. K. Grubbs, D. Yazzie, A. L. Casias, and K. A. Peterson. "Gas Permeation Measurements on Low Temperature Cofired Ceramics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (2012): 000323–27. http://dx.doi.org/10.4071/cicmt-2012-wa25.

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Commercial low temperature cofired ceramic (LTCC) technology is established in microelectronics and microsystems packaging, multichip and radio frequency (RF) modules, and sensors. The ability to combine structural considerations with embedded traces and components using laminated glass-ceramic tapes has created solutions to unconventional packaging requirements of micro-electro-mechanical systems (MEMS) devices. Many MEMS devices such as resonators are very sensitive to pressure and require packaging in a vacuum environment. Attaining and maintaining desirable pressure levels in sealed vacuum packages requires knowledge of the permeation characteristics of the vacuum envelope and the sealing materials. An experimental system to measure the time dependent gas permeation through LTCC at temperatures from room temperature to 500°C has been developed. This system utilizes a membrane technique in which a gas is allowed to permeate through a test sample, held at a constant temperature, into a high vacuum chamber where it is detected using mass spectrometry. The gas permeation value is determined from the steady state gas flux through the sample. The gas diffusivity and solubility in the material were calculated using data from the time dependent approach to the steady state condition. The gas-solid permeation data for helium through DuPont 951 LTCC is presented and compared to the permeation through other common vacuum envelope materials such as glasses and high-purity alumina ceramics. Application of the permeation data to the prediction of vacuum levels inside typical LTCC packaging is discussed. This data can further be utilized in designs to create LTCC packages that meet specific pressure/time operating requirements.

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Link, Doug. "SIP with TSV for Class 1 Medical Devices." International Symposium on Microelectronics 2014, no. 1 (2014): 000313–18. http://dx.doi.org/10.4071/isom-tp51.

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The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. Reported here is how TSV technology was used to shrink the size of a conventional DSP-based system in package (SIP) used in the smallest In-The-Ear (ITE) hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire bonded EEPROM die mounted atop a DSP flip chip die along with 10 passive components built upon a high density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP IC wafer using the via last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This paper describes the design approach, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

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Link, Doug, and Michael Kollar. "Improved Design of a High Density 3D Multichip Module for Class I Medical Devices." International Symposium on Microelectronics 2010, no. 1 (2010): 000119–26. http://dx.doi.org/10.4071/isom-2010-ta4-paper3.

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Today's powerful DSP based hearing instruments demand both high density and low cost microelectronic packaging solutions. In turn, this demand drives innovation and substantial collaboration among design and manufacturing personnel and suppliers. Conventional design and process envelopes are challenged and new problems arise. Rapid failure analysis and root cause identification are essential in this global, fast-paced development arena. Here we introduce a novel high density multichip module designed for placement onto a flexible, folded hearing aid SMD assembly and discuss the challenges faced by the design team. Delamination, electrochemical migration, and thermal stress failure mechanisms identified during design verification testing are examined, along with the techniques and tools of failure analysis and problem solutions.

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6

Marsh, William J., and Issam Mudawar. "Sensible Heating and Boiling Incipience in Free-Falling Dielectric Liquid Films." Journal of Electronic Packaging 111, no. 1 (1989): 46–53. http://dx.doi.org/10.1115/1.3226508.

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Controlling boiling incipience is of paramount importance for reliable operation of liquid-cooled microelectronic heat sources during power transients. This study focuses on heat transfer from a simulated multichip module to a falling film. Experiments have been performed to develop an understanding of the influence of surface tension and wetting characteristics on sensible heat transfer and boiling incipience in free-falling dielectric (FC-72) liquid films. The boiling results reveal that the vanishingly small contact angle of FC-72 precludes the application of correlations currently employed to predict incipience. Also, the temperature excursion commonly encountered upon boiling incipience in wetting fluids was nonexistent in all the experimental runs.

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Lee, Youngtak, and Doug Link. "SIP with TSV for Class 1 Medical Devices." Journal of Microelectronics and Electronic Packaging 13, no. 1 (2016): 1–5. http://dx.doi.org/10.4071/imaps.497.

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The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. This article reports how through-silicon-via (TSV) technology was used to shrink the size of a conventional digital signal process (DSP)-based system in package (SIP) used in the smallest in-the-ear hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire-bonded electrically erasable programmable read-only memory (EEPROM) die mounted atop a DSP flip-chip die along with 10 passive components built upon a high-density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP integrated circuit (IC) wafer using the via-last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This article describes the design approaches, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

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8

Peterson, K. A., K. D. Patel, C. K. Ho, et al. "LTCC Microsystems and Microsystem Packaging and Integration Applications." Journal of Microelectronics and Electronic Packaging 3, no. 3 (2006): 109–20. http://dx.doi.org/10.4071/1551-4897-3.3.109.

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Low Temperature Cofired Ceramic (LTCC) has proven to be an enabling medium for microsystem technologies, because of its desirable electrical, physical, and chemical properties coupled with its capability for rapid prototyping and scalable manufacturing of components. LTCC is viewed as an extension of hybrid microcircuits, and in that function it enables development, testing, and deployment of silicon microsystems. However, its versatility has allowed it to succeed as a microsystem medium in its own right, with applications in non-microelectronic meso-scale devices and in a range of sensor devices. Applications include silicon microfluidic ‘chip-and-wire’ systems and fluid grid array (FGA)/microfluidic multichip modules using embedded channels in LTCC, and cofired electro-mechanical systems with moving parts. Both the microfluidic and mechanical system applications are enabled by sacrificial volume materials (SVM), which serve to create and maintain cavities and separation gaps during the lamination and cofiring process. SVMs consisting of thermally fugitive or partially inert materials are easily incorporated. Screeding is an incorporation technique we describe that improves uniformity and eliminates processing steps. Recognizing the premium on devices that are cofired rather than assembled, we report on functional-as-released and functional-as-fired moving parts, including an impeller that has been exercised over thirty million cycles, and a cofired pressure sensor that requires only pressure source and electrical connections. Additional applications for cofired transparent windows, some as small as an optical fiber, are also described. The applications described help pave the way for widespread application of LTCC to biomedical, control, analysis, characterization, and radio frequency (RF) functions for macro-meso-microsystems.

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9

Shaffer, E. O., P. H. Townsend, M. J. Radler, and C. J. Carriere. "Finite Element Analysis of the Mechanical Performance of Benzocyclobutene Structures in Multichip Modules." MRS Proceedings 239 (1991). http://dx.doi.org/10.1557/proc-239-163.

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ABSTRACTPolymeric materials are used as interlayer dielectrics for multichip modules. One of the central challenges for these structures is management of the large stresses induced by the differences in the thermal properties of the inorganic component structures and the organic film during processing.Finite clement analysis has been used to model the stresses in the dielectric material in practical structures used in multilayer microelectronic architecture, such as interlayer vias and the associated internal metal patterns. Calculations have been performed on the stress field at the corner of square vias in benzocyclobutcne based interlayer dielectrics and related polymeric materials. The effects of the thermal and mechanical properties of the polymeric coating on the stress fields in metal patterns have been calculated and provide insight for design and process optimization.

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10

Ramm, Peter, Armin Klumpp, Reinhard Merkel, et al. "3D System Integration Technologies." MRS Proceedings 766 (2003). http://dx.doi.org/10.1557/proc-766-e5.6.

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AbstractIn the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.

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Dissertations / Theses on the topic "Multichip modules (Microelectronics)"

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Nazareth, Mathew B. "Design and simulation of a multichip module /." Online version of thesis, 1994. http://hdl.handle.net/1850/12181.

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Saiyed, Mohammed Shafi. "System-in-package a system level investigation for package reliability /." Diss., Online access via UMI:, 2005.

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Chheda, Mahesh. "Automatic visual inspection of placement of bare dies in multichip modules /." Online version of thesis, 1994. http://hdl.handle.net/1850/11704.

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4

Dasalla, Kathryn Anne. "Capacity requirements planning of multichip modules through simulation." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.

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5

Wright-Williams, Lorna M. "New organic materials for microelectronics applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/26251.

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6

Hayth-Perdue, Wendy. "Design and fabrication of an underwater digital signal processor multichip module on low temperature cofired ceramic." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-03042009-040331/.

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7

Nagarkar, Kaustubh Ravindra. "A systems approach to ultra-fine pitch flip chip interconnect packaging." Diss., Online access via UMI:, 2005.

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8

Hon, Chi Kwong. "3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?MECH%202006%20HON.

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9

Sasidhar, Koppolu. "Parallel test techniques for multi-chip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13863.

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10

Barton, Cecil Edward. "Electrical characterization of a multilayer low temperature co-fireable ceramic multichip module." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-09052009-040727/.

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Books on the topic "Multichip modules (Microelectronics)"

1

S, Kuh Ernest, ed. Multichip modules. World Scientific, 1992.

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Kear, Fred W. Hybrid assemblies and multichip modules. M. Dekker, 1993.

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1943-, Brown William D., ed. Advanced electronic packaging: With emphasis on multichip modules. IEEE Press, 1999.

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Kinzy, Jones W., and Harsányi Gábor, eds. Multichip modules with integrated sensors. Kluwer Academic Publishers, 1996.

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Garrou, Philip E. Multichip module technology handbook. McGraw-Hill, 1998.

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International, Conference on Multichip Modules and High Density Packaging (1998 Denver Colo ). Proceedings. Institute of Electrical and Electronics Engineers, 1998.

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International Conference and Exhibition on Multichip Modules (6th 1997 Denver, Colo.). Proceedings: 1997 International Conference on Multichip Modules, April 2-4, 1997, The Adam's Mark Hotel, Denver, Colorado. Institute of Electrical and Electronics Engineers, 1997.

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International Conference and Exhibition on Multichip Modules (5th 1996 Denver, Colo.). 1996 International Conference on Multichip Modules: Proceedings, April 17-19, 1996, Denver, Colorado. ISHM, 1996.

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Knipfer, Brent J. Multichip packaging and bare chip systems. Business Communications Co., 1994.

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Sandborn, Peter A. Conceptual Design of Multichip Modules and Systems. Springer US, 1994.

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Book chapters on the topic "Multichip modules (Microelectronics)"

1

Illyefalvi-Vitéz, Zsolt, János Pinkola, László Gál, and Endre Tóth. "Low Cost Interconnection Technology for Fast Prototyping of Multichip Modules." In Microelectronic Interconnections and Assembly. Springer Netherlands, 1998. http://dx.doi.org/10.1007/978-94-011-5135-1_14.

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Franzon, Paul D. "Multichip Module Technology." In Microelectronics. CRC Press, 2018. http://dx.doi.org/10.1201/9781315220482-13.

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Franzon, Paul. "Multichip Module Technology." In Microelectronics 2nd Edition. CRC Press, 2005. http://dx.doi.org/10.1201/9781420037593.ch13.

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Franzon, Paul. "Multichip Module Technology." In Microelectronics 2nd Edition. CRC Press, 2005. http://dx.doi.org/10.1201/9780849333910.ch13.

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Krongelb, Sol, Lubomyr Romankiw, Eric Perfecto, and Keith Wong. "Electrochemical processes in the fabrication of multichip modules." In Microelectronic Packaging. CRC Press, 2004. http://dx.doi.org/10.1201/9780203473689.ch11.

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"Multichip Module and Microwave Hybrid Circuits." In Handbook of Thick- and Thin-Film Hybrid Microelectronics. John Wiley & Sons, Inc., 2004. http://dx.doi.org/10.1002/0471723673.ch11.

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Conference papers on the topic "Multichip modules (Microelectronics)"

1

Mennerat, Sophie, and Sylvain Paineau. "A novel design of diffractive optical interconnects for multichip clock distribution." In The European Conference on Lasers and Electro-Optics. Optica Publishing Group, 1998. http://dx.doi.org/10.1364/cleo_europe.1998.cpd2.3.

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We report a novel system of diffractive optical interconnects for very high speed clock distribution among multichip modules. Our system distributes two clock signals, each from one separate Vertical Cavity Surface Emitting Laser (VCSEL) over four PIN diodes positioned within a radius of 9 mm along a light-guiding glass plate. The incoming optical gaussian beams from VCSEL are splitted by diffractive optical elements into four output beams and the glass plate propagates the light through multiple reflections onto the golden metallized faces towards the detectors. The overall alignment and chromatic acceptance is highly improved by the use of SELFOC micro-lenses that collimate the laser beam onto the diffractive optical element and that focus the output beam onto the active area of the detectors. The proposed architecture allows tolerance on the light source wavelength as high as Δλ = 10 nm and global tolerances of assembly of the glass plate of 1.5 degrees in rotation and 10 µm in translation making it compatible with the processes of hybridization in microelectronics.

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Miracky, Robert F., Seyed H. Hashemi, Tom J. Hirsch, et al. "Laser processing for multichip module customization." In Microelectronic Processing '92, edited by Dim-Lee Kwong and Heinrich G. Mueller. SPIE, 1993. http://dx.doi.org/10.1117/12.142087.

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Jog, Anagha G., Ian R. Grosse, and Daniel D. Corkill. "Intelligent Automatic Mesh Generation for Multichip Modules." In ASME 1993 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1993. http://dx.doi.org/10.1115/cie1993-0034.

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Abstract Currently, the pre-processing stage of finite element analysis is a major stumbling block towards automation of the entire finite element modeling and analysis (FEMA) process. The lack of complete automation of FEMA greatly limits its impact as a design tool. This paper presents a blackboard-based, object-oriented modeling system for intelligent a-priori automatic three dimensional mesh generation. The modeling system enables the user to define the physical system at a natural domain-specific high level of abstraction and automatically derives lower-level finite element model representations. Knowledge sources interact with the blackboard to make modeling idealizations and select optimal meshing strategies. An example application in the domain of finite element modeling of multi-chip module microelectronic devices is presented.

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Ang, Simon S., D. A. Arnn, D. J. Meyer, L. W. Schaper, and William D. Brown. "Low-cost flexible ball-grid-array multichip module technology." In ISMA '97 International Symposium on Microelectronics and Assembly, edited by Yong Khim Swee, HongYu Zheng, and Ray T. Chen. SPIE, 1997. http://dx.doi.org/10.1117/12.280574.

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Grosse, Ian R., and Daniel D. Corkill. "A Blackboard Based Approach to Intelligent Finite Element Modeling and Analysis." In ASME 1992 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1992. http://dx.doi.org/10.1115/cie1992-0091.

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Abstract In this paper a methodology and associated system architecture is proposed for the development of an intelligent finite element modeling assistant. The technique is ideally suited for specific application domains in which the physical system to be modeled can be constructed from a limited and well defined set of features. The development of knowledges sources needed to support automatic finite element modeling and analysis is discussed. A computational framework is proposed for interfacing the various knowledge sources and controlling the execution of the knowledge sources in an opportunistic manner based on the multiple expert blackboard paradigm. An example application in the domain of finite element modeling and analysis of multichip module microelectronic devices is presented and discussed.

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