Relevant bibliographies by topics / Multichip modules (Microelectronics) Testing

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Multichip modules (Microelectronics) Testing'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Multichip modules (Microelectronics) Testing"

1

Peterson, K. A., K. D. Patel, C. K. Ho, et al. "LTCC Microsystems and Microsystem Packaging and Integration Applications." Journal of Microelectronics and Electronic Packaging 3, no. 3 (2006): 109–20. http://dx.doi.org/10.4071/1551-4897-3.3.109.

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Low Temperature Cofired Ceramic (LTCC) has proven to be an enabling medium for microsystem technologies, because of its desirable electrical, physical, and chemical properties coupled with its capability for rapid prototyping and scalable manufacturing of components. LTCC is viewed as an extension of hybrid microcircuits, and in that function it enables development, testing, and deployment of silicon microsystems. However, its versatility has allowed it to succeed as a microsystem medium in its own right, with applications in non-microelectronic meso-scale devices and in a range of sensor devices. Applications include silicon microfluidic ‘chip-and-wire’ systems and fluid grid array (FGA)/microfluidic multichip modules using embedded channels in LTCC, and cofired electro-mechanical systems with moving parts. Both the microfluidic and mechanical system applications are enabled by sacrificial volume materials (SVM), which serve to create and maintain cavities and separation gaps during the lamination and cofiring process. SVMs consisting of thermally fugitive or partially inert materials are easily incorporated. Screeding is an incorporation technique we describe that improves uniformity and eliminates processing steps. Recognizing the premium on devices that are cofired rather than assembled, we report on functional-as-released and functional-as-fired moving parts, including an impeller that has been exercised over thirty million cycles, and a cofired pressure sensor that requires only pressure source and electrical connections. Additional applications for cofired transparent windows, some as small as an optical fiber, are also described. The applications described help pave the way for widespread application of LTCC to biomedical, control, analysis, characterization, and radio frequency (RF) functions for macro-meso-microsystems.
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Flint, A. "Testing multichip modules." IEEE Spectrum 31, no. 3 (1994): 59–62. http://dx.doi.org/10.1109/6.265412.

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Link, Doug, and Michael Kollar. "Improved Design of a High Density 3D Multichip Module for Class I Medical Devices." International Symposium on Microelectronics 2010, no. 1 (2010): 000119–26. http://dx.doi.org/10.4071/isom-2010-ta4-paper3.

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Today's powerful DSP based hearing instruments demand both high density and low cost microelectronic packaging solutions. In turn, this demand drives innovation and substantial collaboration among design and manufacturing personnel and suppliers. Conventional design and process envelopes are challenged and new problems arise. Rapid failure analysis and root cause identification are essential in this global, fast-paced development arena. Here we introduce a novel high density multichip module designed for placement onto a flexible, folded hearing aid SMD assembly and discuss the challenges faced by the design team. Delamination, electrochemical migration, and thermal stress failure mechanisms identified during design verification testing are examined, along with the techniques and tools of failure analysis and problem solutions.
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Abadir, Magdy. "Economics modeling of multichip modules testing strategies." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 21, no. 4 (1998): 360–70. http://dx.doi.org/10.1109/96.730420.

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Manzer, D. G., J. P. Karidis, K. M. Wiley, et al. "High-speed electrical testing of multichip ceramic modules." IBM Journal of Research and Development 49, no. 4.5 (2005): 687–97. http://dx.doi.org/10.1147/rd.494.0687.

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Wong, C. P., and M. M. Wong. "Recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics." IEEE Transactions on Components and Packaging Technologies 22, no. 1 (1999): 21–25. http://dx.doi.org/10.1109/6144.759349.

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Krueger, Daniel, John Porter, and Ken Peterson. "Stress and Strain Modeling of Low Temperature Cofired Ceramic (LTCC) Seal Frame and Lid." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, CICMT (2015): 000157–63. http://dx.doi.org/10.4071/cicmt-wa21.

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Low temperature cofired ceramic (LTCC) is established as an excellent packaging technology for high reliability, high density microelectronics. LTCC multichip modules (MCMs) comprising both ‘surface mount’ and ‘chip and wire’ technologies provide additional customization for performance. Long term robustness of the packages is impacted by the selection of seal frame and lid materials used to enclose the components inside distinct rooms in LTCC MCMs. An LTCC seal frame and lid combination has been developed that is capable of meeting the sealing and electromagnetic shielding requirements of MCMs. This work analyzes the stress and strain performance of various seal frame and lid materials, sealing materials, and configurations. The application for the MCM will impact selection of the seal frame, lid, and sealing materials based on this analysis.
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Goeke, R. S., R. K. Grubbs, D. Yazzie, A. L. Casias, and K. A. Peterson. "Gas Permeation Measurements on Low Temperature Cofired Ceramics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (2012): 000323–27. http://dx.doi.org/10.4071/cicmt-2012-wa25.

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Commercial low temperature cofired ceramic (LTCC) technology is established in microelectronics and microsystems packaging, multichip and radio frequency (RF) modules, and sensors. The ability to combine structural considerations with embedded traces and components using laminated glass-ceramic tapes has created solutions to unconventional packaging requirements of micro-electro-mechanical systems (MEMS) devices. Many MEMS devices such as resonators are very sensitive to pressure and require packaging in a vacuum environment. Attaining and maintaining desirable pressure levels in sealed vacuum packages requires knowledge of the permeation characteristics of the vacuum envelope and the sealing materials. An experimental system to measure the time dependent gas permeation through LTCC at temperatures from room temperature to 500°C has been developed. This system utilizes a membrane technique in which a gas is allowed to permeate through a test sample, held at a constant temperature, into a high vacuum chamber where it is detected using mass spectrometry. The gas permeation value is determined from the steady state gas flux through the sample. The gas diffusivity and solubility in the material were calculated using data from the time dependent approach to the steady state condition. The gas-solid permeation data for helium through DuPont 951 LTCC is presented and compared to the permeation through other common vacuum envelope materials such as glasses and high-purity alumina ceramics. Application of the permeation data to the prediction of vacuum levels inside typical LTCC packaging is discussed. This data can further be utilized in designs to create LTCC packages that meet specific pressure/time operating requirements.
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"Design and Implementation of Jtag Compatible 4-Bit Multiplier." International Journal of Recent Technology and Engineering 9, no. 1 (2020): 1317–20. http://dx.doi.org/10.35940/ijrte.f8830.059120.

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The novel scan- based methodology was developed and resulted in system designers agreeing on it due to the rising complication of boards and also enhancement of technologies like multichip modules. It is called as boundary scan testing for the board level chips. This method was established by the Joint Test Access Group. It was named as JTAG. JTAG was developed for verifying designs and testing printed circuit boards after manufacture. A JTAG interface is a special interface added to a chip. Traditional test technologies require very large and expensive equipment. The most aim of this paper is to style and implement 4-bit multiplier using this standard. The designs were being verified and the circuit boards were being tested after the manufacture by using the industry standard JTAG. It is employed because of accessing sub-blocks of chips. It's a very important mechanism for debugging embedded systems. Boundary-scan cells created exploitation electronic device and latch circuits square measure hooked up to each pin on the device. These cells, embedded among the device, will capture knowledge from pin or core logic signals conjointly as force knowledge onto pins. Captured knowledge is serially shifted out through the JTAG take a look at Access Port (TAP) and will be compared to expected values to figure out a pass or fail result. Forced take a look at knowledge is serially shifted into the boundary-scan cells.
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Townsend, P. H., D. Schmidt, T. M. Stokich, et al. "Adhesion of Cyclotene™ (BCB) Coatings on Silicon Substrates." MRS Proceedings 323 (1993). http://dx.doi.org/10.1557/proc-323-365.

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AbstractThis work examines the adhesion of coatings derived from divinylsiloxane bisbenzocyclobutene, mixed stereo and positional isomers of 1,3-bis(2-bicyclo[4.2.0]octa-1,3,5-trien-3-ylethenyl)-1,1,3,3-tetramethyl disiloxane (CAS 117732–87–3), on oxidized silicon substrates treated with silane coupling agents.This material, commercially available as Cyclotene™ 3022, can be used in the construction of high performance electronic circuits, such as multichip modules. Silane coupling agents examined in this study were 3-aminopropyltriethoxysilane (CAS 01760-24-3)(APTES)(, vinyltriethoxysilane (CAS 00078–08–0)(VTES), and 3-methacryloxypropyl trimethoxysilane (CAS 02530–85–0) (MOP-TMS).Measurement of the interfacial adhesion was performed using microindentation. Bond strengths obtained by this method exceed 200 MPa for the most effective coupling agents. However, these high bond strengths were not found to correlate with acceptable adhesive performance in all cases. In addition to the choice and preparation of the coupling agent, process related chemical exposure has been found to be a key element in the observed adhesive performance. The effect of the cure schedule for the thermoset coating has also been found to be a controlling factor. A short cycle test vehicle was developed consisting of a single 20 gIm polymer layer etched with anisotropic sidewalls. This test vehicle was used to evaluate the efficacy of the coupling agents during process exposures and subsequent thermal shock testing. A solution of MOP-TMS pre-hydrolyzed in methanol was found to produce the most reliable interface with high bond strength.
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Dissertations / Theses on the topic "Multichip modules (Microelectronics) Testing"

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Sasidhar, Koppolu. "Parallel test techniques for multi-chip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13863.

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Pendurkar, Rajesh. "Design for testability techniques and optimization algorithms for performance and functional testing of mult-chip module interconnections." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16635.

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Kim, Bruce Chang-Shik. "A fault detection and diagnosis technique for multi-chip module interconnects." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/13736.

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Pike, Randy T. "Reworkable high temperature adhesives for Multichip Module (MCM-D) and Chip-on-Board (COB) applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19506.

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Newman, Kimberly Eileen. "A parallel digital interconnect test methodology for multi-chip module substrate networks." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13847.

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McGovern, Lawrence P. "Analysis of interconnect yield for a high throughput flip chip assembly process." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/16605.

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Chheda, Mahesh. "Automatic visual inspection of placement of bare dies in multichip modules /." Online version of thesis, 1994. http://hdl.handle.net/1850/11704.

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Nazareth, Mathew B. "Design and simulation of a multichip module /." Online version of thesis, 1994. http://hdl.handle.net/1850/12181.

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Saiyed, Mohammed Shafi. "System-in-package a system level investigation for package reliability /." Diss., Online access via UMI:, 2005.

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Hayth-Perdue, Wendy. "Design and fabrication of an underwater digital signal processor multichip module on low temperature cofired ceramic." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-03042009-040331/.

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Books on the topic "Multichip modules (Microelectronics) Testing"

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Multichip module design, fabrication, and testing. McGraw-Hill, 1995.

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Lau, John H. Solder joint reliability of BGA, CSP, flip chip, and fine pitch SMT assemblies. McGraw-Hill, 1997.

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Qiong, Yu, and Babida Sandeep 1965-, eds. Introduction to multichip modules. Wiley, 1995.

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1945-, Kang Sung-Mo, ed. Physical design for multichip modules. Kluwer Academic Publishers, 1994.

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Kear, Fred W. Hybrid assemblies and multichip modules. M. Dekker, 1993.

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IEEE Multi-Chip Module Conference (1993 Santa Cruz, Calif.). 1993 IEEE Multi-Chip Module Conference, MCMC-93, March 15-18, 1993, Santa Cruz, California: Proceedings. IEEE Computer Society Press, 1993.

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IEEE, Multi-Chip Module Conference (1992 Santa Cruz Calif ). Proceedings, 1992 IEEE Multi-Chip Module Conference, MCMC-92: March 18-20, 1992, Santa Cruz, California. IEEE Computer Society Press, 1992.

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IEEE Multi-Chip Module Conference (1992 Santa Cruz, Calif.). Proceedings, 1992 IEEE Multi-Chip Module Conference, MCMC-92: March 18-20, 1992, Santa Cruz, California. IEEE Computer Society Press, 1992.

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IEEE Multi-Chip Module Conference (1994 Santa Cruz, Calif.). 1994 IEEE Multi-Chip Module Conference: MCMC-94, March 15-17, 1994, Santa Cruz, California : proceedings. IEEE Computer Society Press, 1994.

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IEEE Multi-Chip Module Conference (1996 Santa Cruz, Calif.). Proceedings: 1996 IEEE Multi-Chip Module Conference, February 6-7, 1996, Santa Cruz, California. IEEE Computer Society Press, 1996.

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Book chapters on the topic "Multichip modules (Microelectronics) Testing"

1

Russell, Thomas C., and Yenting Wen. "Electrical Testing of Multichip Modules." In Multichip Module Technologies and Alternatives: The Basics. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3100-5_13.

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Murphy, Cynthia F., Magdy S. Abadir, Peter A. Sandborn, and Y. Zorian. "Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die." In Frontiers in Electronic Testing. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6107-1_14.

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Posse, Ken, and Y. Zorian. "A Formalization of the IEEE 1149.1–1990 Diagnostic Methodology as Applied to Multichip Modules." In Frontiers in Electronic Testing. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6107-1_11.

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Kear, Fred W. "Testing Methods." In Hybrid Assemblies and Multichip Modules. CRC Press, 2020. http://dx.doi.org/10.1201/9781003066668-9.

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Conference papers on the topic "Multichip modules (Microelectronics) Testing"

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Hilla, S. C. "Boundary scan testing for multichip modules." In Proceedings International Test Conference 1992. IEEE, 1992. http://dx.doi.org/10.1109/test.1992.527823.

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Sridhar, Aravind, Sarah Styslinger, Christopher Duron, et al. "Cooling of High-Performance Server Modules Using Direct Immersion." In ASME 2012 Heat Transfer Summer Conference collocated with the ASME 2012 Fluids Engineering Division Summer Meeting and the ASME 2012 10th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/ht2012-58433.

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An alternative to air-cooling of high performance computing equipment is presented. Heat removal via pool boiling in FC-72 was tested. Tests were conducted on a multichip module using 1.8 cm × 1.8 cm test die with multiple thermal test cells with temperature sensing capability. Measurements with the bare silicon die in direct contact with the fluid are reported. Additional testing included the test die directly indium-attached to copper heat spreaders having surface treatments. A screen-printed sintered boiling-enhanced surface (4 cm × 4 cm) was evaluated. Tests were conducted on an array of five die. Parameters tested include heat flux levels, dielectric liquid pool conditions (saturated or subcooled), and effect of neighboring die. Information was gathered on surface temperatures for a range of heat flux values up to 12 W/cm2. The highest heat dissipated from a circuit board with five bare die was 195 W (39 W per die). Addition of the heat spreader allowed heat dissipation of up to 740 W (from a five-die array). High-speed imaging was also acquired to help examine detailed information on the boiling process. Numerical modeling indicated that placing multiple boards in close proximity to each other did not degrade performance until board spacing was reduced to 3 mm.
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Mendaros, Raymond G., Bernardino D. Mazon, Eugene Capito, and Romeo S. Soriano. "Re-Packaging Solution of Bare Dice From Customer Packages To Open-Cavity Ceramic Packages." In ISTFA 2019. ASM International, 2019. http://dx.doi.org/10.31399/asm.cp.istfa2019p0135.

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Abstract The advent of bare die form in the semiconductor industry driven by the high-performance multichip modules’ (MCM) requirement posed electrical access and testing challenges on customer returned units (CRUs) for failure analysis (FA). In this technical literature, the developed die extraction processes and re-packaging solution on molded MCM and flex package types were discussed.
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Springborn, M., B. Wunderle, D. May, et al. "Thermal management of electrical overload cases using thermo-electric modules and phase change buffer techniques: Simulation, technology and testing." In 2014 15th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE). IEEE, 2014. http://dx.doi.org/10.1109/eurosime.2014.6813857.

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Ramesh, Prashanth, Gregory N. Washington, Sriram Krishnamoorthy, and Siddharth Rajan. "Fabrication and Characterization of Gallium Nitride Unimorphs for Optical MEMS Applications." In ASME 2011 Conference on Smart Materials, Adaptive Structures and Intelligent Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/smasis2011-5213.

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The research outlined in this paper describes part of a larger effort to develop a novel branch of next-generation materials systems called Distributed Intelligent Materials Systems (DIMS) which incorporate actuation, sensing, electronics and communications modules as inherent parts of the material structure. Newer semiconductor materials that are under active research in the field of microelectronics are very well suited for such material systems. Gallium Nitride (GaN), a smart material, is pursued as a candidate material for such a system with a piezoelectrically actuated, optical microswitch being developed as the first prototypical device. This paper covers the unique electromechanical properties of GaN highlighting its differences from other piezoelectrics, the device configuration used to realize the switching device, followed by a description of and the progress made in using a nascent fabrication technology (PhotoElectroChemical Etching) used to realize the 3-dimensional device structure. Finally a low-cost, laser-based, non-contact approach to testing and characterizing the microscale device is described.
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