Log in

Relevant bibliographies by topics / Multichip modules (Microelectronics) Testing / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Multichip modules (Microelectronics) Testing.

Dissertations / Theses on the topic 'Multichip modules (Microelectronics) Testing'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 47 dissertations / theses for your research on the topic 'Multichip modules (Microelectronics) Testing.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Sasidhar, Koppolu. "Parallel test techniques for multi-chip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13863.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Pendurkar, Rajesh. "Design for testability techniques and optimization algorithms for performance and functional testing of mult-chip module interconnections." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16635.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Kim, Bruce Chang-Shik. "A fault detection and diagnosis technique for multi-chip module interconnects." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/13736.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Pike, Randy T. "Reworkable high temperature adhesives for Multichip Module (MCM-D) and Chip-on-Board (COB) applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19506.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Newman, Kimberly Eileen. "A parallel digital interconnect test methodology for multi-chip module substrate networks." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13847.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

McGovern, Lawrence P. "Analysis of interconnect yield for a high throughput flip chip assembly process." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/16605.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Chheda, Mahesh. "Automatic visual inspection of placement of bare dies in multichip modules /." Online version of thesis, 1994. http://hdl.handle.net/1850/11704.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Nazareth, Mathew B. "Design and simulation of a multichip module /." Online version of thesis, 1994. http://hdl.handle.net/1850/12181.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Saiyed, Mohammed Shafi. "System-in-package a system level investigation for package reliability /." Diss., Online access via UMI:, 2005.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

10

Hayth-Perdue, Wendy. "Design and fabrication of an underwater digital signal processor multichip module on low temperature cofired ceramic." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-03042009-040331/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Wright-Williams, Lorna M. "New organic materials for microelectronics applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/26251.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Barton, Cecil Edward. "Electrical characterization of a multilayer low temperature co-fireable ceramic multichip module." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-09052009-040727/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Dasalla, Kathryn Anne. "Capacity requirements planning of multichip modules through simulation." Diss., Online access via UMI:, 2007.

Find full text

Abstract:

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

14

Hodge, Thomas C. "Substrate-film interaction in noble metal/polymer multichip modules." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/10972.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Lee, Jeong-Bong. "Strategies for realization of integrated microelectromechanical systems : on-board power, silicon circuitry, multichip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/14997.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Pierce, Daniel W. "Toward a comprehensive cost model for multichip module (MCM) manufacturing." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/11113.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Nagarkar, Kaustubh Ravindra. "A systems approach to ultra-fine pitch flip chip interconnect packaging." Diss., Online access via UMI:, 2005.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

18

Hon, Chi Kwong. "3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?MECH%202006%20HON.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Grau, Peter F. "Analysis of high density interconnect alternatives in multichip module packaging using the analytic hierarchy process." Master's thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-03172010-020042/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Kokan, Julie Runyan. "Processing of low permittivity silica thin films." Thesis, Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/20032.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Dang, Anh Xuan-Hung. "Study of warpage of base substrates and materials for large-area MCM-D packaging." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/17804.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Jones, Mark Lehi. "Design of normal-incidence waveguide-imbedded phase gratings for optical interconnects in multi-chip modules." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15676.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Khan, Shoab Ahmad. "Logic and algorithm partitioning." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13738.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Kim, Tae Seon. "Modeling, optimization, and control of via formation by photosensitive polymers for MCM-D applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15017.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Keung, Chi Wing. "Matrix-addressable III-nitride light emitting diode arrays on silicon substrates by flip-chip technology /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECE%202007%20KEUNG.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Tang, Chi Wang. "Properties and selection of materials for flip chip packages with low-K die /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?MECH%202007%20TANG.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Desai, Anand Hasmukh. "Thermal management of small scale electronic systems." Diss., Online access via UMI:, 2006.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

28

Tsui, Yat Kit. "Design and fabrication of a flip-chip-on-chip multi-chip module with 3D packaging structure and through-silicon-via for underfill dispensing /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?MECH%202004%20TSUI.

Full text

Abstract:

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 116-127). Also available in electronic version. Access restricted to campus users.

APA, Harvard, Vancouver, ISO, and other styles

29

Roy, Kalapi. "A timing-driven multi-way partiioning system for integrated circuits and multi-chip systems /." Thesis, Connect to this title online; UW restricted, 1994. http://hdl.handle.net/1773/6089.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Pham, Anh-Vu Huynh. "Microwave/millimeter wave multi-layer organic based interconnects." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13543.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Pascarella, Nathan William. "Advanced encapsulation processing for low cost electronics assembly." Thesis, Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/19031.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Lai, Yin Hing. "High power flip-chip light emitting diode /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20LAI.

Full text

Abstract:

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 60-68). Also available in electronic version. Access restricted to campus users.

APA, Harvard, Vancouver, ISO, and other styles

33

Venton, Jennifer Lynne. "Flip chip on flex for low cost electronics assembly." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17285.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Hanna, Carlton Eissey. "Study of thermo-mechanical reliability of area-array packages." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16841.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Koeneman, Paul Bryant. "Viscoelastic stress analysis and fatigue life prediction of a flip-chip-on-board electronic package /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.

Find full text

Abstract:

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

37

Iyer, Satyanarayan Shivkumar. "Assembly, reliability, and rework of stacked CSP components." Diss., Online access via UMI:, 2008.

Find full text

Abstract:

Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.<br>Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

38

Han, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.

Full text

Abstract:

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.

APA, Harvard, Vancouver, ISO, and other styles

39

Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

Full text

Abstract:

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked.

APA, Harvard, Vancouver, ISO, and other styles

40

Lee, Dong Gun. "Strain measurement of flip-chip solder bumps using digital image correlation with optical microscopy." Diss., Online access via UMI:, 2009.

Find full text

Abstract:

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.<br>Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

41

Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.

Find full text

Abstract:

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

42

Miller, Ross Alan. "Thermo-Mechanical Selective Laser Assisted Die Transfer." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29859.

Full text

Abstract:

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of

APA, Harvard, Vancouver, ISO, and other styles

43

Altunyurt, Nevin. "Integration and miniaturization of antennas for system-on-package applications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33903.

Full text

Abstract:

Wireless communications have been an indispensable aspect of everyday life, and there is an increasing consumer demand for accessing several wireless communication technologies from a single, compact, mobile device. System-on-package (SOP) technology is an advanced packaging technology that has been proven to realize the convergence of multiple functions into miniaturized, high-performance systems to meet this demand. With the advancements in the SOP technology, the miniaturization of the front-end module has been achieved using embedded passives in multilayer packages. However, the integratio

APA, Harvard, Vancouver, ISO, and other styles

44

Yoon, Sangwoong. "LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4887.

Full text

Abstract:

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si

APA, Harvard, Vancouver, ISO, and other styles

45

Ho, Chen-Shie, and 何丞世. "Interconnect testing schemes for multichip modules." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/37542280343357356003.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Wang, Daijiao Panton Ronald L. "Experimental study of void formation in solder joints of flip-chip assemblies." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1754/wangd48141.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Wang, Daijiao 1970. "Experimental study of void formation in solder joints of flip-chip assemblies." Thesis, 2005. http://hdl.handle.net/2152/1754.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!