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Dissertations / Theses on the topic 'Multichip modules (Microelectronics)'

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Published: 4 June 2021
Last updated: 28 July 2024

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1

Nazareth, Mathew B. "Design and simulation of a multichip module /." Online version of thesis, 1994. http://hdl.handle.net/1850/12181.

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2

Saiyed, Mohammed Shafi. "System-in-package a system level investigation for package reliability /." Diss., Online access via UMI:, 2005.

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3

Chheda, Mahesh. "Automatic visual inspection of placement of bare dies in multichip modules /." Online version of thesis, 1994. http://hdl.handle.net/1850/11704.

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4

Dasalla, Kathryn Anne. "Capacity requirements planning of multichip modules through simulation." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.
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5

Wright-Williams, Lorna M. "New organic materials for microelectronics applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/26251.

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6

Hayth-Perdue, Wendy. "Design and fabrication of an underwater digital signal processor multichip module on low temperature cofired ceramic." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-03042009-040331/.

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7

Nagarkar, Kaustubh Ravindra. "A systems approach to ultra-fine pitch flip chip interconnect packaging." Diss., Online access via UMI:, 2005.

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8

Hon, Chi Kwong. "3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?MECH%202006%20HON.

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9

Sasidhar, Koppolu. "Parallel test techniques for multi-chip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13863.

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10

Barton, Cecil Edward. "Electrical characterization of a multilayer low temperature co-fireable ceramic multichip module." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-09052009-040727/.

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11

Dang, Anh Xuan-Hung. "Study of warpage of base substrates and materials for large-area MCM-D packaging." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/17804.

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12

Hodge, Thomas C. "Substrate-film interaction in noble metal/polymer multichip modules." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/10972.

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13

Desai, Anand Hasmukh. "Thermal management of small scale electronic systems." Diss., Online access via UMI:, 2006.

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14

Tsui, Yat Kit. "Design and fabrication of a flip-chip-on-chip multi-chip module with 3D packaging structure and through-silicon-via for underfill dispensing /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?MECH%202004%20TSUI.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 116-127). Also available in electronic version. Access restricted to campus users.
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15

Pendurkar, Rajesh. "Design for testability techniques and optimization algorithms for performance and functional testing of mult-chip module interconnections." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16635.

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16

Kim, Bruce Chang-Shik. "A fault detection and diagnosis technique for multi-chip module interconnects." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/13736.

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17

Pierce, Daniel W. "Toward a comprehensive cost model for multichip module (MCM) manufacturing." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/11113.

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18

Lee, Jeong-Bong. "Strategies for realization of integrated microelectromechanical systems : on-board power, silicon circuitry, multichip modules." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/14997.

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19

Lai, Yin Hing. "High power flip-chip light emitting diode /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20LAI.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 60-68). Also available in electronic version. Access restricted to campus users.
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20

Grau, Peter F. "Analysis of high density interconnect alternatives in multichip module packaging using the analytic hierarchy process." Master's thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-03172010-020042/.

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21

Kokan, Julie Runyan. "Processing of low permittivity silica thin films." Thesis, Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/20032.

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22

Pike, Randy T. "Reworkable high temperature adhesives for Multichip Module (MCM-D) and Chip-on-Board (COB) applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19506.

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23

Jones, Mark Lehi. "Design of normal-incidence waveguide-imbedded phase gratings for optical interconnects in multi-chip modules." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15676.

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24

Keung, Chi Wing. "Matrix-addressable III-nitride light emitting diode arrays on silicon substrates by flip-chip technology /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECE%202007%20KEUNG.

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25

Tang, Chi Wang. "Properties and selection of materials for flip chip packages with low-K die /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?MECH%202007%20TANG.

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26

Khan, Shoab Ahmad. "Logic and algorithm partitioning." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13738.

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27

Kim, Tae Seon. "Modeling, optimization, and control of via formation by photosensitive polymers for MCM-D applications." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15017.

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28

Roy, Kalapi. "A timing-driven multi-way partiioning system for integrated circuits and multi-chip systems /." Thesis, Connect to this title online; UW restricted, 1994. http://hdl.handle.net/1773/6089.

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29

Pham, Anh-Vu Huynh. "Microwave/millimeter wave multi-layer organic based interconnects." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13543.

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30

Newman, Kimberly Eileen. "A parallel digital interconnect test methodology for multi-chip module substrate networks." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13847.

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31

Pascarella, Nathan William. "Advanced encapsulation processing for low cost electronics assembly." Thesis, Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/19031.

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32

Hanna, Carlton Eissey. "Study of thermo-mechanical reliability of area-array packages." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16841.

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33

Koeneman, Paul Bryant. "Viscoelastic stress analysis and fatigue life prediction of a flip-chip-on-board electronic package /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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34

McGovern, Lawrence P. "Analysis of interconnect yield for a high throughput flip chip assembly process." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/16605.

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35

Venton, Jennifer Lynne. "Flip chip on flex for low cost electronics assembly." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17285.

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36

Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.
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37

Iyer, Satyanarayan Shivkumar. "Assembly, reliability, and rework of stacked CSP components." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.<br>Includes bibliographical references.
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38

Lee, Dong Gun. "Strain measurement of flip-chip solder bumps using digital image correlation with optical microscopy." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.<br>Includes bibliographical references.
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39

Han, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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40

Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.
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41

Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

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For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
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42

Miller, Ross Alan. "Thermo-Mechanical Selective Laser Assisted Die Transfer." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29859.

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Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 ?m thick silicon tiles between two substrates spaced 195 ?m apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques.<br>Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905
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43

Yoon, Sangwoong. "LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4887.

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This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.
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44

Altunyurt, Nevin. "Integration and miniaturization of antennas for system-on-package applications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33903.

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Wireless communications have been an indispensable aspect of everyday life, and there is an increasing consumer demand for accessing several wireless communication technologies from a single, compact, mobile device. System-on-package (SOP) technology is an advanced packaging technology that has been proven to realize the convergence of multiple functions into miniaturized, high-performance systems to meet this demand. With the advancements in the SOP technology, the miniaturization of the front-end module has been achieved using embedded passives in multilayer packages. However, the integration of the antenna directly on the module package is still the barrier to achieve a fully-integrated, high-performance RF SOP system. The main reason for this missing link is that integrating the antenna on the package requires miniaturizing the antenna, which is a difficult task. The focus of this dissertation is to design high-performance antennas along with developing techniques for miniaturization and system-on-package (SOP) integration of these antennas to achieve fully-integrated SOP systems using advanced multilayer organic substrates and thin-film magneto-dielectric materials. The targeted spectrum for the antenna designs are 2.4/5 GHz WLAN/WiMAX and 60 GHz WPAN bands. Several novel antenna designs and configurations to integrate the antenna on the package along with the module are discussed in this dissertation. The advanced polymers used in this research are Liquid Crystalline Polymer (LCP), RXP, and thin-film magneto-dielectrics.
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45

Wang, Daijiao Panton Ronald L. "Experimental study of void formation in solder joints of flip-chip assemblies." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1754/wangd48141.pdf.

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46

Wang, Daijiao 1970. "Experimental study of void formation in solder joints of flip-chip assemblies." Thesis, 2005. http://hdl.handle.net/2152/1754.

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