Relevant bibliographies by topics / Multigate transistor

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Multigate transistor'

Author: Grafiati
Published: 25 May 2024
Last updated: 31 July 2025

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Journal articles on the topic "Multigate transistor"

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Lee, Chi-Woo, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge. "Junctionless multigate field-effect transistor." Applied Physics Letters 94, no. 5 (2009): 053511. http://dx.doi.org/10.1063/1.3079411.

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Martins, Rodrigo, Diana Gaspar, Manuel J. Mendes, et al. "Papertronics: Multigate paper transistor for multifunction applications." Applied Materials Today 12 (September 2018): 402–14. http://dx.doi.org/10.1016/j.apmt.2018.07.002.

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Jayachandran, Remya, Dhanaraj Jagalchandran, and Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load." Facta universitatis - series: Electronics and Energetics 35, no. 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to
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Selvi, K. Kalai, K. S. Dhanalakshmi, and Kalaivani Kanagarajan. "Performance Estimation of Recessed Modified Junctionless Multigate Transistor." Journal of Nano- and Electronic Physics 14, no. 1 (2022): 01008–1. http://dx.doi.org/10.21272/jnep.14(1).01008.

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Kohda, S., K. Masuda, K. Matsuzawa, and Y. Kitano. "A giant chip multigate transistor ROM circuit design." IEEE Journal of Solid-State Circuits 21, no. 5 (1986): 713–19. http://dx.doi.org/10.1109/jssc.1986.1052599.

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Delgado-Notario, Juan A., Wojciech Knap, Vito Clericò, et al. "Enhanced terahertz detection of multigate graphene nanostructures." Nanophotonics 11, no. 3 (2022): 519–29. http://dx.doi.org/10.1515/nanoph-2021-0573.

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Abstract Terahertz (THz) waves have revealed a great potential for use in various fields and for a wide range of challenging applications. High-performance detectors are, however, vital for exploitation of THz technology. Graphene plasmonic THz detectors have proven to be promising optoelectronic devices, but improving their performance is still necessary. In this work, an asymmetric-dual-grating-gate graphene-terahertz-field-effect-transistor with a graphite back-gate was fabricated and characterized under illumination of 0.3 THz radiation in the temperature range from 4.5 K up to the room te
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Ono, Y., H. Inokawa, and Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic." IEEE Transactions on Nanotechnology 1, no. 2 (2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.

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Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)." Jurnal Qua Teknika 7, no. 1 (2017): 53–64. http://dx.doi.org/10.35457/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.
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Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)." JURNAL QUA TEKNIKA 7, no. 1 (2017): 53–64. http://dx.doi.org/10.30957/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.
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Н.А., Агафонов, Масальский Н.В., Осипов В.В. та Родителев А.В. "Проблемы моделирования переноса в квазипланарных КНИ КМОП нанотранзисторах". Труды НИИСИ РАН 8, № 5 (2018): 139–47. http://dx.doi.org/10.25682/niisi.2018.5.0021.

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Обсуждается возможность эффективного моделирования переноса носителей в квазипланарных КНИ МОП транзисторах. Выполнен анализ разнообразных конструкций транзисторов - от классической планарной схемы до трехмерных мультизатворных структур (двух-, трех- и четырех затворные) с учетом возможной асимметрии затвора и канала транзистора. По результатам исследования сформулированы требования к модели для реализации методики численного расчета переноса носителей в таких устройствах The possibility of effective simulation of transfer of carriers in quasiplanar SOI CMOS transistors is discussed. The analy
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Dissertations / Theses on the topic "Multigate transistor"

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Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture
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Chevillon, Nicolas. "Etude et modélisation compacte du transistor FinFET ultime." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00750928.

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Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs
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Lu, Wenjie. "Antimonide-based III-V multigate transistors." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/117833.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged student-submitted from PDF version of thesis.<br>Includes bibliographical references (pages 159-171).<br>As Si CMOS technology advances, alternative channel materials are under extensive investigation to replace or augment Si in future generations of nanoelectronics. III-V compound semiconductors, such as InGaAs and
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Chang, Kai-Hsiang, and 張凱翔. "The study of multigate Poly-Si Thin-Film Transistors." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/30168709489216678656.

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碩士<br>逢甲大學<br>電子工程所<br>99<br>Polycrystalline silicon thin-film transistors (Poly-Si) are used widely in various field, such as active-matrix liquid crystal displays (AMLCDs), solar cell, active matrix organic light emitting diode (AMOLED) and flash memories because of their high mobility and driving current. In recent year, the device is promising candidate to be used in display system-on-panel (SOP) as memory and controller. Then the conventional poly – Si TFT is not enough in term of the speed and the current drive capability. To increase the speed and the current of the poly-Si TFT, a do
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Books on the topic "Multigate transistor"

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Sivasankaran, K., and Partha Sharathi Mallick. Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9.

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Multigate Transistors for High Frequency Applications. Springer, 2023.

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Book chapters on the topic "Multigate transistor"

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Transistor Stability and Design Challenges." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_2.

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of Silicon Nanowire Transistor." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_6.

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of SELBOX Inverted-T Junctionless FET." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_7.

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of DG MOSFET." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_3.

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of FinFET." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_5.

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of Double-Gate Tunnel FET." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_4.

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Sivasankaran, K., and Partha Sharathi Mallick. "Introduction." In Multigate Transistors for High Frequency Applications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_1.

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Rathinam, Ramesh, Adhithan Pon, and Arkaprava Bhattacharyya. "Phosphorene Multigate Field-Effect Transistors for High-Frequency Applications." In Sub-Micron Semiconductor Devices. CRC Press, 2022. http://dx.doi.org/10.1201/9781003126393-21.

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Madhulika Sharma, Savitesh, and Avtar Singh. "FinFETs and their Applications." In Nanoscale Field Effect Transistors: Emerging Applications. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010006.

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Researchers are motivated to develop novel electronic switches with improved low power properties and reduced short channel effects due to the downscaling of conventional MOSFETs (SCE). Using multi-gate FinFET technology could improve control of the gate over the channel charge. We have discussed FinFETs, or multigate transistors, in this chapter. The chapter will include the classification and detailed physics inside the device. The Fabrication section will explain the steps involved in manufacturing the device. The difficulties with FinFET technologies have also been discussed in order to ex
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Conference papers on the topic "Multigate transistor"

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Li, Nayu, Botao Yang, Hang Lu, Yiwei Liu, Chunyi Song, and Zhiwei Xu. "A C-Band Four-Channel Receiver with Current-Sharing and Large-Signal Multigated-Transistor Techniques in 65-nm CMOS." In 2024 IEEE MTT-S International Wireless Symposium (IWS). IEEE, 2024. http://dx.doi.org/10.1109/iws61525.2024.10713543.

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Lou, Haijun, Binghua Li, Xinnan Lin, Jin He, and Mansun Chan. "Investigations of fin vertical nonuniformity effects on junctionless multigate transistor." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6467617.

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Gang Wu, Li Cai, Qiang Kang, Sen Wang, and Qin Li. "A 8-bit parity code generator based on multigate single electron transistor." In 2008 3rd IEEE International Conference on Nano/Micro Engineered and Molecular Systems. IEEE, 2008. http://dx.doi.org/10.1109/nems.2008.4484314.

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Wu, Gang, and Li Cai. "Ternary multiplier of multigate single electron transistor: Design using 3-T gate." In 2010 8th IEEE International Conference on Control and Automation (ICCA). IEEE, 2010. http://dx.doi.org/10.1109/icca.2010.5524397.

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He, Chenlin, Fei You, Yi Wang, Zehua Xiao, Yaojia Fan, and Songbai He. "A 22-32.7 GHz Linearized LNA in 65-nm CMOS Using Multigate Transistor Technique." In 2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT). IEEE, 2023. http://dx.doi.org/10.1109/icmmt58241.2023.10276839.

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Singh, Dipak Kumar, Priyanka Mondal, and M. W. Akram. "Bulk multigate junctionless transistor (BMGJLT) with non-uniform doping profile: An attractive device for scaling." In PROCEEDINGS OF INTERNATIONAL CONFERENCE ON RECENT TRENDS IN MECHANICAL AND MATERIALS ENGINEERING: ICRTMME 2019. AIP Publishing, 2020. http://dx.doi.org/10.1063/5.0025667.

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Young, Chadwin D. "Assessing the reliability and performance impact on the three-dimensional structure of multigate field effect transistor (MugFET)." In 2013 IEEE International Integrated Reliability Workshop (IIRW). IEEE, 2013. http://dx.doi.org/10.1109/iirw.2013.6804145.

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Dehdashti, Nima, Abhinav Kranti, Isabelle Ferain, et al. "Dissipative transport in Multigate silicon nanowire transistors." In 2010 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010). IEEE, 2010. http://dx.doi.org/10.1109/sispad.2010.5604559.

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Snelgrove, Ashton, and Pierre-Emmanuel Gaillardon. "Programmable logic elements using multigate ambipolar transistors." In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE, 2022. http://dx.doi.org/10.1109/ddecs54261.2022.9770137.

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Razavi, P., G. Fagas, I. Ferain, N. D. Akhavan, R. Yu, and J. P. Colinge. "Performance investigation of short-channel junctionless multigate transistors." In 2011 12th International Conference on Ultimate Integration on Silicon (ULIS 2011). IEEE, 2011. http://dx.doi.org/10.1109/ulis.2011.5758005.

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Journal articles
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