Log in

Relevant bibliographies by topics / Multiplexer/De- Multiplexer (MUX/DEMUX) / Journal articles

To see the other types of publications on this topic, follow the link: Multiplexer/De- Multiplexer (MUX/DEMUX).

Journal articles on the topic 'Multiplexer/De- Multiplexer (MUX/DEMUX)'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Multiplexer/De- Multiplexer (MUX/DEMUX).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (January 5, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.1.

Full text

Abstract:

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a de

APA, Harvard, Vancouver, ISO, and other styles

2

Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (November 14, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.2.

Full text

Abstract:

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a de

APA, Harvard, Vancouver, ISO, and other styles

3

SOOLE, J. B. D., H. P. LeBLANC, N. C. ANDREADAKIS, R. BHAT, C. CANEAU, and M. A. KOZA. "MONOLITHIC InP REFLECTION-GRATING MULTIPLEXER/DEMULTIPLEXERS FOR WDM COMPONENTS OPERATING IN THE LONG WAVELENGTH FIBER BAND." International Journal of High Speed Electronics and Systems 05, no. 01 (1994): 111–33. http://dx.doi.org/10.1142/s0129156494000061.

Full text

Abstract:

We discuss an emerging monolithic “photonic integrated circuit” technology for application in future wavelength division multiplexed (WDM) networks. Based on a planar reflection-grating wavelength multiplexer/demultiplexer, and realized in InP-matched material for the long wavelength fiber band, the WDM optical cavity may be integrated with different active elements to provide a variety of spectrally-matched WDM functional components. We consider the design and performance of the basic mux/demux, and review the current status of both the passive device and integrated active components. We also

APA, Harvard, Vancouver, ISO, and other styles

4

Wang, Manzhuo, Xiaoqiang Sun, Tingyu Liu, et al. "Silica Waveguide Four-Mode Multiplexer Based on Cascaded Directional Couplers." Photonics 10, no. 9 (2023): 983. http://dx.doi.org/10.3390/photonics10090983.

Full text

Abstract:

Mode multiplexers/demultiplexers (MUX/deMUX) are key components in mode division multiplexing. A silica waveguide mode MUX consisting of four cascaded directional couplers is experimentally demonstrated. The beam propagation method is used in the device design and optimization. Thermal oxidation, plasma-enhanced chemical vapor deposition, and ultraviolet photolithography are adopted in the silica waveguide mode MUX fabrication. The measurement results prove that the input E00 mode can be selectively converted to E10 mode, E20 mode, and E30 mode. Within the wavelength range of 1500 to 1620 nm,

APA, Harvard, Vancouver, ISO, and other styles

5

ISHII, Kiyoshi, Hideyuki NOSAKA, Kimikazu SANO, et al. "RECENT PROGRESS IN 40- TO 100-GBIT/S-CLASS OPTICAL COMMUNICATIONS ICS USING INP-BASED HBT TECHNOLOGIES." International Journal of High Speed Electronics and Systems 15, no. 03 (2005): 615–41. http://dx.doi.org/10.1142/s0129156405003363.

Full text

Abstract:

This paper describes our InP-based heterojunction bipolar transistor (HBT) technologies and circuit design techniques for small-scale-integration (SSI) and medium-scale-integration (MSI) circuits for 40- to 100-Gbit/s-class optical communications systems. The circuits include a sub-4-ps emitter-coupled logic (ECL) gate, 100-Gbit/s selector circuit, 90-Gbit/s decision circuit, 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs, aver-40-Gbit/s 16:1 MUX IC, and 40-Gbit/s full-clock-rate DEMUX with a clock and data recovery (CDR) circuit. This paper demonstrates that InP-based HBT t

APA, Harvard, Vancouver, ISO, and other styles

6

Henry Naiho and Seleman Ngwira. "NEW INSIGHTS ON SURVIVABILITY IN MULTIPLE LINK AND NODE FAILURES OF OPTICAL NETWORKS." Computer Science & IT Research Journal 4, no. 1 (2023): 20–35. http://dx.doi.org/10.51594/csitrj.v4i1.591.

Full text

Abstract:

Survivability becomes increasingly critical in managing high-speed networks as data traffic continues to grow in both size and importance. In addition, the impact of failures is exacerbated by the higher data rates available in optical networks. The purpose of this study is to optimize the survivability approach to address the problem of capacity efficiency and fast recovery time of multiple link and node failures in one technique. Most research works done had only addressed either of these constraints in a single failure. This research intends to develop and implement a new integrated approac

APA, Harvard, Vancouver, ISO, and other styles

7

Yasui, Tadahiko, and Yoshiaki Nakano. "Variable mux/demux time division photonic switching network using optical time jumper." Electronics and Communications in Japan (Part I: Communications) 84, no. 9 (2001): 1–15. http://dx.doi.org/10.1002/ecja.1036.

Full text

Abstract:

AbstractA pulse can be viewed as a kind of memory with faster processing elements, because the information carried by the pulse can be read out at any time by the faster processing elements. Taking this into consideration, one of the authors proposed a TDM switching system which in principle requires no random access memories, but rather only logical gates. This is very much suited to the photonic TDM switching system, as optical RAMs are not as yet available.This paper newly proposes a photonic TDM switching system in which a time jumper is placed on a highway link connecting multistage varia

APA, Harvard, Vancouver, ISO, and other styles

8

Kim, Jungho, Jaehyoung Park, Seunghwan Chung, Namkyoo Park, Byoungho Lee, and Kitae Jeong. "Bidirectional wavelength add/drop multiplexer using two separate MUX and DEMUX pairs and reflection-type comb filters." Optics Communications 205, no. 4-6 (2002): 321–27. http://dx.doi.org/10.1016/s0030-4018(02)01387-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Lv, Zhixiao, Jiangbing Du, and Zuyuan He. "On-Chip Multichannel Dispersion Compensation and Wavelength Division MUX/DeMUX Using Chirped-Multimode-Grating-Assisted Counter-Directional Coupler." Photonics 11, no. 2 (2024): 110. http://dx.doi.org/10.3390/photonics11020110.

Full text

Abstract:

On-chip optical dispersion compensation and wavelength division multiplexing/demultiplexing (WDM) are highly demanded functions for optical communications. In this work, we proposed a multichannel dispersion compensation structure based on chirped multimode grating within a counter-directional coupler (CMG-CDC). Simultaneous wavelength division multiplexing and demultiplexing can be realized within a compact footprint. A device design for four-channel CMG-CDC at the C/L (1530–1565 nm) band is presented with a channel spacing of 20 nm assisted by a grooved multimode waveguide structure. The ave

APA, Harvard, Vancouver, ISO, and other styles

10

Ren, Fang, Tianwen Zhangsun, Xiang Lu, et al. "Spatial-mode switchable, multi-wavelength all-fiber erbium-doped fiber (EDF) laser based on low modal crosstalk mode multiplexer/demultiplexer (MUX/DEMUX)." Laser Physics 29, no. 7 (2019): 075105. http://dx.doi.org/10.1088/1555-6611/ab1839.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

REIN, H. M. "Si AND SiGe BIPOLAR ICs FOR 10 TO 40 Gb/s OPTICAL-FIBER TDM LINKS." International Journal of High Speed Electronics and Systems 09, no. 02 (1998): 347–83. http://dx.doi.org/10.1142/s0129156498000178.

Full text

Abstract:

This paper gives an overview on very-high-speed ICs for optical-fiber systems with restriction to Si-based technologies. As a main aim, the circuit and system designer shall get an impression what operating speeds have already been achieved and, moreover, get a feeling for potential limitations. It is shown that all ICs in 10 Gb/s TDM systems can be fabricated in Si-bipolar production technologies, while for the speed-critical ICs in 20 Gb/s systems, present SiGe laboratory technologies are required if the circuit specifications, apart from the data rate, must remain unchanged. With uncritical

APA, Harvard, Vancouver, ISO, and other styles

12

Charles, Ipshitha, Sandip Swarnakar, Geetha Rani Nalubolu, Venkatrao Palacharla, and Santosh Kumar. "An All Optical 2 × 1 Multiplexer Using a Metal-Insulator-Metal based Plasmonic Waveguide for Processing at a Rapid Pace." Photonics 10, no. 1 (2023): 74. http://dx.doi.org/10.3390/photonics10010074.

Full text

Abstract:

This study proposes, designs, and simulates a unique plasmonic Y-shaped MIM waveguide based 2 × 1 multiplexer (MUX) structure utilising opti-FDTD software. Two plasmonic Y-shaped waveguides are positioned facing one another inside a minimum wafer size of 6 µm × 3.5 µm in the 2 × 1 MUX configurations that is being described. The design parameters are adjusted until the plasmonic multiplexer performs as required under optimal conditions. Extinction ratio and insertion loss are two performance metrics that are calculated for performance analysis of the design, which indicate the potential to be a

APA, Harvard, Vancouver, ISO, and other styles

13

Anjum, Nikhat, Anil Kumar Shukla, and Vijay Nath. "Design and Analysis of all Optical Multiplexers using 2D Photonic Crystal." International Journal of Microsystems and IoT 2, no. 3 (2024): 663–69. https://doi.org/10.5281/zenodo.11107841.

Full text

Abstract:

 The development of an all-optical, two-dimensional photonic crystal waveguide multiplexer (MUX) for optical signal processing and networking is the focus of this study. The paper proposes the design of 4<strong>×</strong>1 all optical multiplexer based on 2-D photonic crystal. The architecture, which has an air-filled background, uses two silicon square lattice rod T-shaped waveguides and one silicon square lattice rod Y-shaped waveguide. All-optical MUX developed the use of nonlinear materials, such as Kerr, to address challenges of less profit and nonlinearity. The beam-interfere

APA, Harvard, Vancouver, ISO, and other styles

14

Sherif, Noora H., Mohammed Hussien Ali, and Najim Abdallah Jazea. "Design and implementation reversible multiplexer using quantum-dot cellular automata approach." Bulletin of Electrical Engineering and Informatics 11, no. 6 (2022): 3383–91. http://dx.doi.org/10.11591/eei.v11i6.4307.

Full text

Abstract:

Rapid progress in the field of nanotechnology includes using quantum dot-cellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using

APA, Harvard, Vancouver, ISO, and other styles

15

Noora, H. Sherif, Hussien Ali Mohammed, and Abdallah Jazea Najim. "Design and implementation reversible multiplexer using quantum-dot cellular automata approach." Bulletin of Electrical Engineering and Informatics 11, no. 6 (2022): 3383~3391. https://doi.org/10.11591/eei.v11i6.4307.

Full text

Abstract:

Rapid progress in the field of nanotechnology includes using quantum dotcellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX struct

APA, Harvard, Vancouver, ISO, and other styles

16

Almatrood, Amjad, Aby K. George, and Harpreet Singh. "Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs." Electronics 10, no. 16 (2021): 1885. http://dx.doi.org/10.3390/electronics10161885.

Full text

Abstract:

Quantum-dot cellular automata (QCA) technology is considered to be a possible alternative for circuit implementation in terms of energy efficiency, integration density and switching frequency. Multiplexer (MUX) can be considered to be a suitable candidate for designing QCA circuits. In this paper, two different structures of energy-efficient 2×1 MUX designs are proposed. These MUXes outperform the best existing design in terms of power consumption with approximate reductions of 26% and 35%. Moreover, similar or better performance factors such as area and latency are achieved compared to the av

APA, Harvard, Vancouver, ISO, and other styles

17

Mustafa, Sajjad Mohanad, Gholamreza Karimi, Mazdak Rad Malek Shahi, and Saif Hasan Abdulnabi. "Nanomaterials in Nanophotonics Structure for Performing All-Optical 2 × 1 Multiplexer Based on Elliptical IMI-Plasmonic Waveguides." Nanomaterials and Nanotechnology 2023 (November 8, 2023): 1–13. http://dx.doi.org/10.1155/2023/7790674.

Full text

Abstract:

In this study, an all-optical multiplexer (Mux) based on elliptical insulator-metal-insulator (IMI) plasmonic waveguides is designed. The area of the proposed structure is very small (400 nm × 400 nm) which operates at a wavelength of 1,550 nm. The developed device utilizes constructive and destructive interferences between the input signals and the selector signal. This structure is less complex and has lower loss compared to the previous works. Transmission (T), contrast ratio (CR), modulation depth (MD), insertion loss (IL), and contrast loss (CL) are the five parameters that describe the p

APA, Harvard, Vancouver, ISO, and other styles

18

Zeeshan A, Mohammed, and Dr Kiran V. "Design and Comparison of Full Adder Using TG Based 4:1 MUX." International Journal of Research and Review 9, no. 11 (2022): 91–95. http://dx.doi.org/10.52403/ijrr.20221115.

Full text

Abstract:

The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder. Keywords: Mux, Full

APA, Harvard, Vancouver, ISO, and other styles

19

Seo, Hyun-Sik, Cheng Gong, Zhihui Cai, et al. "16.1: Characteristics of Ln‐doped IZO TFT according to the Change of Indium concentration for DeMUX Applications." SID Symposium Digest of Technical Papers 54, S1 (2023): 125–27. http://dx.doi.org/10.1002/sdtp.16241.

Full text

Abstract:

In order to narrow the bezel in high‐end IT and tablets, using switching circuit de‐multiplexer (DeMUX) reduces the number of source D/IC, making small LCD module available. In this study, new oxide TFT material, Ln‐doped InZnO (Ln‐IZO), has been developed. To achieve mobility of > 25cm2 /V.s, study focused on the effect of Indium (In) concentration on the fabrication of Ln‐IZO sputtering target, and fabricated the DeMUX‐equipped 14 inch FHD driven by gate on array (GOA).

APA, Harvard, Vancouver, ISO, and other styles

20

Hsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.

Full text

Abstract:

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserte

APA, Harvard, Vancouver, ISO, and other styles

21

Sohan, kumar Dahana, and Hajari Aastha. "Efficient Design of 2 1 MUX Multiplexer using Nanotechnology Based on QCA." International Journal of Trend in Scientific Research and Development 2, no. 6 (2018): 1211–14. https://doi.org/10.31142/ijtsrd18858.

Full text

Abstract:

Quantum Dot Cellular Automata is a new technology which overcomes of the of CMOS limitations. It is an novel advanced nano technology that revolves around the single electron position control. It is one of the most efficient and emerging nano technology which mainly deals with the effect of electrons inside the quantum dots in QCA cell, and it is the best alternative technology in the nano electronics level architectural field. In this paper, we designed a 2 1 Multiplexer, which is more efficient in the term of area and cells to the other designs. Sohan kumar Dahana | Aastha Hajari "Effic

APA, Harvard, Vancouver, ISO, and other styles

22

Jiang, Chuanpeng, Jinhao Li, Hongchao Zhang, et al. "Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications." Journal of Semiconductors 44, no. 12 (2023): 122501. http://dx.doi.org/10.1088/1674-4926/44/12/122501.

Full text

Abstract:

Abstract We have successfully demonstrated a 1 Kb spin-orbit torque (SOT) magnetic random-access memory (MRAM) multiplexer (MUX) array with remarkable performance. The 1 Kb MUX array exhibits an in-die function yield of over 99.6%. Additionally, it provides a sufficient readout window, with a TMR/R P_sigma% value of 21.4. Moreover, the SOT magnetic tunnel junctions (MTJs) in the array show write error rates as low as 10−6 without any ballooning effects or back-hopping behaviors, ensuring the write stability and reliability. This array achieves write operations in 20 ns and 1.2 V for an industr

APA, Harvard, Vancouver, ISO, and other styles

23

Baker, Timothy J., and John P. Hayes. "CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design." ACM Transactions on Design Automation of Electronic Systems 27, no. 3 (2022): 1–26. http://dx.doi.org/10.1145/3491213.

Full text

Abstract:

Stochastic computing (SC) is a low-cost computational paradigm that has promising applications in digital filter design, image processing, and neural networks. Fundamental to these applications is the weighted addition operation, which is most often implemented by a multiplexer (mux) tree. Mux-based adders have very low area but typically require long bitstreams to reach practical accuracy thresholds when the number of summands is large. In this work, we first identify the main contributors to mux adder error. We then demonstrate with analysis and experiment that two new techniques, precise sa

APA, Harvard, Vancouver, ISO, and other styles

24

Kotb, Amer, Kyriakos E. Zoiros, and Wei Chen. "High-Speed 2x1 Multiplexer with Carrier-Reservoir Semiconductor Optical Amplifiers." Photonics 11, no. 7 (2024): 648. http://dx.doi.org/10.3390/photonics11070648.

Full text

Abstract:

Leveraging the rapid carrier recovery times and minimal polarization sensitivity of carrier-reservoir semiconductor optical amplifiers (CR-SOAs), this study embeds them in a Mach–Zehnder interferometer (MZI) setup to emulate a 2x1 multiplexer (MUX) operating at 120 Gb/s. The focus is on incorporating AND logic gate functionalities into the CR-SOAs-based MZI structure to facilitate high-quality multiplexing. The proposed methodology utilizes the intrinsic gain and phase modulation capabilities of CR-SOAs-based MZI to effectively manipulate data streams. This innovative approach capitalizes on t

APA, Harvard, Vancouver, ISO, and other styles

25

MISHRA, KHUSHBOO, and SHYAM AKASHE. "DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES." International Journal of Nanoscience 12, no. 04 (2013): 1350026. http://dx.doi.org/10.1142/s0219581x13500269.

Full text

Abstract:

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We h

APA, Harvard, Vancouver, ISO, and other styles

26

Musala, Sarada, P. Durga Vasavi, Avireni Srinivasulu, and Cristian Ravariu. "A Novel Quaternary Half Subtractor Using 2:1 Multiplexer." International Journal of Applied Sciences & Development 4 (January 29, 2025): 1–7. https://doi.org/10.37394/232029.2025.4.1.

Full text

Abstract:

Multiple-valued logic (MVL) is a logic in which there are more than two truth values. MVL is used due to difficulty in interconnection problems in binary system. Carbon nanotube field-effect transistors (CNTFET) is used to design the Quaternary Half Subtractor (QHS) circuit. Sub blocks of Module (0210), Module (1021), Module (2102), Module (3210) using three supply voltage devices and Quaternary Multiplexer 2:1 using pass transistor have designed in this paper. Therefore, compared to existing designs, less no. of transistors are needed. Comparing proposed Half subtractor using 4:1 MUX modules

APA, Harvard, Vancouver, ISO, and other styles

27

Chen, Pao-Lung, and Chun-Chien Tsai. "An Interpolated Flying-Adder-Based Frequency Synthesizer." Journal of Electrical and Computer Engineering 2011 (2011): 1–11. http://dx.doi.org/10.1155/2011/871385.

Full text

Abstract:

This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are deriv

APA, Harvard, Vancouver, ISO, and other styles

28

Majeed, Ali H., Esam Alkaldy, Mohd Shamian Zainal, Keivan Navi, and Danial Nor. "Optimal design of RAM cell using novel 2:1 multiplexer in QCA technology." Circuit World 46, no. 2 (2019): 147–58. http://dx.doi.org/10.1108/cw-06-2019-0062.

Full text

Abstract:

Purpose Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms

APA, Harvard, Vancouver, ISO, and other styles

29

Ying, Yong Jie, and Zaharah Johari. "Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties." Journal of Physics: Conference Series 2622, no. 1 (2023): 012023. http://dx.doi.org/10.1088/1742-6596/2622/1/012023.

Full text

Abstract:

Abstract This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulat

APA, Harvard, Vancouver, ISO, and other styles

30

Dahana, Sohan kumar, and Aastha Hajari. "Efficient Design of 2:1 MUX Multiplexer using Nanotechnology Based on QCA." International Journal of Trend in Scientific Research and Development Volume-2, Issue-6 (2018): 1211–14. http://dx.doi.org/10.31142/ijtsrd18858.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Jeong, Ju Young, and Moon‐Pyo Hong. "Design of LTPS TFT Current Mode Multiplexer and MUX‐based Logic Gates." Journal of Information Display 9, no. 3 (2008): 1–7. http://dx.doi.org/10.1080/15980316.2008.9652055.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Prabhakar, Deepika, Shylashree Nagaraja, S. Pranava Koundinya, and Meghana R. "Design and Implementation of D-Flip Flop For Computation in Memory." WSEAS TRANSACTIONS ON ELECTRONICS 16 (February 4, 2025): 46–50. https://doi.org/10.37394/232017.2025.16.5.

Full text

Abstract:

As the number of data-intensive applications has grown, the traditional Von Neumann computer architecture has become constrained. To address the issue, the new technology platform "computation-in-memory" was established. A new design of the D Flip flop implemented in a memory array employing 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed in this study. To implement the D Flip Flop, this design employs a master-slave multiplexer (MUX) architecture. It has a setup time of 94.887ps and a hold time of 97.22ps.

APA, Harvard, Vancouver, ISO, and other styles

33

Prakash, Jogi, Biroju Ravi Kiran, and Parvatham Sathish. "THE EFFICIENT IMPLEMENTATION TO OPTIMIZE POWER AND DELAY USING DATA SELECTOR." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1159–65. https://doi.org/10.21917/ijme.2021.0200.

Full text

Abstract:

The objective of this paper is designing a 16:1 multiplexer using logic gates and CMOS logic. In this research, we have investigated the delay and power modulations of 16:1MUX. This demonstrates that the CMOS technique takes lead as it uses decreased number of transistors, have less capacitances and faster than others. In this research a comparative work is done and made the simulated results and it illustrates the superior nature of CMOS logic design and it dissipates very decreased power and delay. The simulations for the proposed model are done by using Synopsys tool HSPICE under 32 nm BSIM

APA, Harvard, Vancouver, ISO, and other styles

34

Widmann, Daniel, Markus Grözing, and Manfred Berroth. "High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology." Advances in Radio Science 16 (September 4, 2018): 99–108. http://dx.doi.org/10.5194/ars-16-99-2018.

Full text

Abstract:

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in st

APA, Harvard, Vancouver, ISO, and other styles

35

Yang, Jingfu, Xiaoping Yu, and Rikun Wei. "A low resource consumption Arbiter PUF improved switch component design for FPGA." Journal of Physics: Conference Series 2221, no. 1 (2022): 012011. http://dx.doi.org/10.1088/1742-6596/2221/1/012011.

Full text

Abstract:

Abstract Aiming at the problems of poor uniqueness and high resource consumption of slice after the implementation of Arbiter physical unclonable function (Arbiter PUF) on field programmable gate array (FPGA), a new improved scheme of switch component structure is proposed. The switch component structure of the improved scheme adopts the parallel-connected mode to improve the uniqueness of the circuit, which avoids the cross-connected mode unable to achieve symmetrical layout on FPGA. At the same time, the improved scheme uses lookup tables to construct the structure of programmable delay line

APA, Harvard, Vancouver, ISO, and other styles

36

Verma, Nidhi, and Sanjoy Mandal. "Performance analysis of optical micro-ring resonator as all-optical reconfigurable logic and multiplexer in Z-domain." Journal of Nonlinear Optical Physics & Materials 25, no. 01 (2016): 1650013. http://dx.doi.org/10.1142/s0218863516500132.

Full text

Abstract:

Performance and design methodology of [Formula: see text] multiplexer (MUX) and all-optical reconfigurable logic circuit using GaAs–AlGaAs-based optical micro-ring resonator (OMRR) are presented in current paper. Proposed design of reconfigurable logic circuit is capable to perform eight different logic operations. Performances of the logic circuits have been theoretically analyzed using Z-domain modeling. Numerical simulation results confirming the method are explained in the present paper. Proposed circuit is simple, compact, efficient as it have minimum number of OMRR, low operating power,

APA, Harvard, Vancouver, ISO, and other styles

37

Okawa, Kodai, Minju Kim, Kyungyuk Chae та ін. "Direct measurement of the ²⁶Si(α, p)²⁹P reaction at CRIB for the nucleosynthesis in the X-ray bursts". EPJ Web of Conferences 275 (2023): 02009. http://dx.doi.org/10.1051/epjconf/202327502009.

Full text

Abstract:

Several (α, p) reactions with radioactive-ions (RI) in the αp-process are important to characterize X-ray bursts. However, some of them do not have sufficient experimental data, and the 26Si(α, p)29P reaction is one of such reactions. We performed a direct measurement of the reaction in inverse kinematics with a thick target at the CNS RI beam separator (CRIB).We used a multiplexer circuit, Mesytec MUX, to acquire data from many channels of silicon detectors. In this experimental setup, a resonant elastic scattering was measured simultaneously. The details of the experimental conditions and th

APA, Harvard, Vancouver, ISO, and other styles

38

PRAJAKTA, RAVINDRA MORE, and DR. G.M.PHADE PROF. "HIGH SPEED AND LOW POWER FLASH ADC DESIGN." JournalNX - a Multidisciplinary Peer Reviewed Journal 3, no. 9 (2017): 77–79. https://doi.org/10.5281/zenodo.1420628.

Full text

Abstract:

The Analog to Digital converters play an imperative role in todays electronic systems world. Current applications need High Speed and Low Power ADC. Flash ADC is most prevalent not only for its highest transformation rate but also for its use in other ADC types and its varied applications. Traditional N-bit flash ADC necessitates 2N-1 comparator and same number of preamplifier. if we use multiplexer to design FLASH ADC number of Comparator and Preamplifier get reduced also use of mux in Thermometer to binary code encoder will reduce delay which will ultimately reduce overall power consumption

APA, Harvard, Vancouver, ISO, and other styles

39

Thamatam, Venkata Chalama Reddy, and Karunakar Aliginti. "Enhancing Digital Circuit Performance Using Memristor-Inspired Amplifiers." International Journal of Computational Learning & Intelligence 4, no. 1 (2025): 343–58. https://doi.org/10.5281/zenodo.15123613.

Full text

Abstract:

In this paper, we present the design, implementation, and evaluation of digital logic circuits using Memristor-based technology. The focus is on basic gates, a 2 × 1 multiplexer (MUX), a full adder, a full subtractor, and an amplifier, all implemented using the Cadence Virtuoso platform. The Memristor model employed here shows significant improvements in power efficiency, area reduction, and speed compared to traditional 45-nm CMOS technologies. Our results demonstrate that Memristor-based circuits can achieve up to 71.4% reduction in area, 40% reduction in power consumption, and 54% red

APA, Harvard, Vancouver, ISO, and other styles

40

Tamilarasan, Esther, Gracia Nirmala Rani Duraisamy, Muthu Kumaran Elangovan, and Arun Samuel Thankmony Sarasam. "A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques." Micromachines 14, no. 10 (2023): 1816. http://dx.doi.org/10.3390/mi14101816.

Full text

Abstract:

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area

APA, Harvard, Vancouver, ISO, and other styles

41

Cui, Yijun, Chongyan Gu, Qingqing Ma, et al. "Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA." Electronics 9, no. 5 (2020): 815. http://dx.doi.org/10.3390/electronics9050815.

Full text

Abstract:

Physical unclonable function (PUF) is a primary hardware security primitive that is suitable for lightweight applications. However, it is found to be vulnerable to modeling attacks using machine learning algorithms. In this paper, multiplexer (MUX)-based Multi-PUF (MMPUF) design is proposed to thwart modeling attacks. The proposed design uses a weak PUF to obfuscate the challenge of a strong PUF. A mathematical model of the proposed design is presented and analyzed. The three most widely used modeling attack techniques are used to evaluate the resistance of the proposed design. Experimental re

APA, Harvard, Vancouver, ISO, and other styles

42

S, Mohan Das, Ganesh Kumar M, and Shireesha G. "Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 7 (2020): 8–13. http://dx.doi.org/10.46647/ijetms.2020.v04i07.002.

Full text

Abstract:

In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and G

APA, Harvard, Vancouver, ISO, and other styles

43

Divya, Sharma, N. Shylashree, Prasad Ramjee, and Nath Vijay. "Analysis of Programmable Gain Instrumentation Amplifier." International Journal of Microsystems and IoT 1, no. 1 (2023): 41–47. https://doi.org/10.5281/zenodo.8191366.

Full text

Abstract:

This paper presents an analysis of the design of a programmable gain amplifier (PGA) based on an instrumentation amplifier. The instrumentation amplifier can be implemented in different ways, including the Single Op amp IA, 2 Op-amp INA, 3 Op-amp INA, Switched Capacitor Instrumentation amplifier (SCIA), Current Feedback Instrumentation amplifier (CFIA), Current Mirror Instrumentation amplifier (CMIA), and others. By adding switches or a multiplexer (Mux) to the amplifier, a precision programmable gain instrumentation amplifier (PG-IA) can be created. The literature suggests various approaches

APA, Harvard, Vancouver, ISO, and other styles

44

Ijjada, Sreenivasa Rao, Ajaykumar Dharmireddy, M. Sushanth Babu, and Lavanya Kotha. "Design and Implementation of Multiplier Accumulator Unit Using Rounding Based Approximation." International Journal of Microsystems and IoT 2, no. 1 (2024): 529–37. https://doi.org/10.5281/zenodo.10715039.

Full text

Abstract:

This paper presents an analysis of the design of a programmable gain amplifier (PGA) based on an instrumentation amplifier. The instrumentation amplifier can be implemented in different ways, including the Single Op amp IA, 2 Op-amp INA, 3 Op-amp INA, Switched Capacitor Instrumentation amplifier (SCIA), Current Feedback Instrumentation amplifier (CFIA), Current Mirror Instrumentation amplifier (CMIA), and others. By adding switches or a multiplexer (Mux) to the amplifier, a precision programmable gain instrumentation amplifier (PG-IA) can be created. The literature suggests various approaches

APA, Harvard, Vancouver, ISO, and other styles

45

Hussain Shah, Syed Khawar, Ali Hellany, Mahmood Nagrial, and Jamal Rizk. "Novel Approach to Monitoring and Mitigating Power Quality Disturbances in Hybrid Renewable Energy System." Renewable Energy and Power Quality Journal 20 (September 2022): 481–87. http://dx.doi.org/10.24084/repqj20.345.

Full text

Abstract:

Renewable energy sources are continually increasing their share in the energy system. The introduction of Hybrid Renewable Energy Sources (H.R.E.S.) in the electrical power system has gained momentum. The increased share of Renewable sources has resulted in an increase in Power Quality (P.Q.) disturbances at the user and consumer levels. This research will engineers dedicate the P.Q. disturbances produced in the electrical system due to Hybrid Renewable energy sources, especially solar and wind. The research will predict what type of P.Q. disturbances are introduced during power production. Th

APA, Harvard, Vancouver, ISO, and other styles

46

Djellab, H., N. Doghmane, A. Bouarfa, and M. Kandouci. "Study of the Different Optical Filters in SAC-OCDMA System." Journal of Optical Communications 39, no. 4 (2018): 381–86. http://dx.doi.org/10.1515/joc-2017-0223.

Full text

Abstract:

Abstract Spectral amplitude coding for optical code division multiple access (SAC-OCDMA) networks has received much attention over the last two decades. This article aims to explore the impact of encoder change on different types of optical filters, such as the Gaussian optical filter and the Bessel optical filter, for high data rates and to give an overview on importance of choosing the optimal type of optical filter according to the frequency range selected by the user is 25 and 50 GHz. SAC-OCDMA transmitter utilizes Wavelength Division Multiplexing multiplexer (WDM MUX) as an encoder, to ge

APA, Harvard, Vancouver, ISO, and other styles

47

Majeed, Ali H. "An ultra-low complexity of 2:1 multiplexer block in QCA technology." Indonesian Journal of Electrical Engineering and Computer Science 21, no. 3 (2021): 1341–46. https://doi.org/10.11591/ijeecs.v21.i3.pp1341-1346.

Full text

Abstract:

The limitations related to CMOS such as power consumption and parasitic capacitance lead scientists to search for new technologies. Quantum-dot cellular automata (QCA) is a CMOS alternative technology that uses charges instead of voltage level for binary representation. In QCA, many metrics are used for circuit differentiation such as delay, complexity and area. In this work, a new simple block of 2:1 QCA-Multiplexer is proposed. The proposed block is more efficient than previous designs by 43%, 53%, 50% and 72% in terms of area, complexity, delay and cost. QCADesigner software is used to desi

APA, Harvard, Vancouver, ISO, and other styles

48

Ahn, Choi, Lim, and Yu. "Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory." Micromachines 10, no. 10 (2019): 637. http://dx.doi.org/10.3390/mi10100637.

Full text

Abstract:

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode a

APA, Harvard, Vancouver, ISO, and other styles

49

Sun, Lili, Zhongxu Jin, Yanchao Liu, Xiaohua Yu, and Ronghua Ni. "A 50 Gb/s 0.42 pJ/b Non-Return-to-Zero Transmitter for Extra-Short-Reach SerDes." Electronics 14, no. 10 (2025): 1955. https://doi.org/10.3390/electronics14101955.

Full text

Abstract:

An energy- and area-efficient non-return-to-zero (NRZ) transmitter with feedforward equalization (FFE) is proposed for an extra-short-reach (XSR) data interface in chiplet-based system in packages (SiPs) and multi-chip modules (MCMs). At the system level, the final-stage 2:1 multiplexer (MUX) in the transmitter is combined with the driver to reduce the hardware and power consumption; at the circuit level, charge-steering-based moderate-swing signal processing further reduces the circuit power consumption and inter-symbol interference. Fabricated in a 28 nm CMOS process with a core area of 0.03

APA, Harvard, Vancouver, ISO, and other styles

50

Zou, Zongjun. "P‐18.5: A Study of TP‐MUX Technology of LTPS Automotive In‐cell Display." SID Symposium Digest of Technical Papers 56, S1 (2025): 1825–29. https://doi.org/10.1002/sdtp.19227.

Full text

Abstract:

LTPS In‐cell technology has its unique advantages and adaptability in the field of vehicle display. It escapes the limitation of traditional out‐cell touch, and has good plasticity and reliability in special‐shaped and curved structures, so it is especially suitable for application in vehicle in the cockpit environment. However, with the increase in the size of on‐board displays, the traditional In‐cell technology has a gap in balancing Display and Touch resources, which makes it impossible to achieve a high cost‐effective driving solution. The TP‐MUX technology (Touch Panel Multiplexer Techno

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!