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Journal articles on the topic 'Multiplexer/De- Multiplexer (MUX/DEMUX)'

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Published: 3 June 2025

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Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (January 5, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.1.

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (November 14, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.2.

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SOOLE, J. B. D., H. P. LeBLANC, N. C. ANDREADAKIS, R. BHAT, C. CANEAU, and M. A. KOZA. "MONOLITHIC InP REFLECTION-GRATING MULTIPLEXER/DEMULTIPLEXERS FOR WDM COMPONENTS OPERATING IN THE LONG WAVELENGTH FIBER BAND." International Journal of High Speed Electronics and Systems 05, no. 01 (1994): 111–33. http://dx.doi.org/10.1142/s0129156494000061.

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We discuss an emerging monolithic “photonic integrated circuit” technology for application in future wavelength division multiplexed (WDM) networks. Based on a planar reflection-grating wavelength multiplexer/demultiplexer, and realized in InP-matched material for the long wavelength fiber band, the WDM optical cavity may be integrated with different active elements to provide a variety of spectrally-matched WDM functional components. We consider the design and performance of the basic mux/demux, and review the current status of both the passive device and integrated active components. We also look to the future and assess prospective near-term advancements.

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Wang, Manzhuo, Xiaoqiang Sun, Tingyu Liu, et al. "Silica Waveguide Four-Mode Multiplexer Based on Cascaded Directional Couplers." Photonics 10, no. 9 (2023): 983. http://dx.doi.org/10.3390/photonics10090983.

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Mode multiplexers/demultiplexers (MUX/deMUX) are key components in mode division multiplexing. A silica waveguide mode MUX consisting of four cascaded directional couplers is experimentally demonstrated. The beam propagation method is used in the device design and optimization. Thermal oxidation, plasma-enhanced chemical vapor deposition, and ultraviolet photolithography are adopted in the silica waveguide mode MUX fabrication. The measurement results prove that the input E00 mode can be selectively converted to E10 mode, E20 mode, and E30 mode. Within the wavelength range of 1500 to 1620 nm, the insertion loss is less than 12.2 dB. The proposed mode MUX has good potential in on-chip MDM applications.

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ISHII, Kiyoshi, Hideyuki NOSAKA, Kimikazu SANO, et al. "RECENT PROGRESS IN 40- TO 100-GBIT/S-CLASS OPTICAL COMMUNICATIONS ICS USING INP-BASED HBT TECHNOLOGIES." International Journal of High Speed Electronics and Systems 15, no. 03 (2005): 615–41. http://dx.doi.org/10.1142/s0129156405003363.

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This paper describes our InP-based heterojunction bipolar transistor (HBT) technologies and circuit design techniques for small-scale-integration (SSI) and medium-scale-integration (MSI) circuits for 40- to 100-Gbit/s-class optical communications systems. The circuits include a sub-4-ps emitter-coupled logic (ECL) gate, 100-Gbit/s selector circuit, 90-Gbit/s decision circuit, 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs, aver-40-Gbit/s 16:1 MUX IC, and 40-Gbit/s full-clock-rate DEMUX with a clock and data recovery (CDR) circuit. This paper demonstrates that InP-based HBT technologies and our circuit design techniques are attractive for fabricating ultrahigh-speed SSI circuits with data rates approaching 100 Gbit/s and low-power MSI circuits with data rates of over 40 Gbit/s.

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Henry Naiho and Seleman Ngwira. "NEW INSIGHTS ON SURVIVABILITY IN MULTIPLE LINK AND NODE FAILURES OF OPTICAL NETWORKS." Computer Science & IT Research Journal 4, no. 1 (2023): 20–35. http://dx.doi.org/10.51594/csitrj.v4i1.591.

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Survivability becomes increasingly critical in managing high-speed networks as data traffic continues to grow in both size and importance. In addition, the impact of failures is exacerbated by the higher data rates available in optical networks. The purpose of this study is to optimize the survivability approach to address the problem of capacity efficiency and fast recovery time of multiple link and node failures in one technique. Most research works done had only addressed either of these constraints in a single failure. This research intends to develop and implement a new integrated approach called Multi-Suv system model to address multiple failures in links and nodes of an optical network. Experiments was conducted to demonstrate the ability of the system model to identify the nature of failure based on the intensity of importance as defined in the fundamental scale of absolute numbers (Saaty, 1980); thus, inform on the path of restoration or protection to address the link and node failures. Following experimental simulations done on the model, the results shows that there are benefits amongst are reduced network resource usage, speedy recovery time, guaranteed availability and quality of reliability. The socio-economic value of this research will reduce the CAPEX capital investment of network infrastructures and facilities and OPEX the operational costs of service delivery of the ICT industry thereby increasing the profitability of the network and service providers.  Keywords: WDM (Wavelength Division Multiplex), OXADM (Optical cross Add & Drop Multiplexer), Intelli-MUX (Intelligent Multiplexer), DeMux (De-multiplexer, OPSS (Optical Switching System), OPXC (Optical Cross Connect), CAPEX (Capital expenditures), OPEX (Operations expenditures, OPM (Opinion Performance Matrix).

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Yasui, Tadahiko, and Yoshiaki Nakano. "Variable mux/demux time division photonic switching network using optical time jumper." Electronics and Communications in Japan (Part I: Communications) 84, no. 9 (2001): 1–15. http://dx.doi.org/10.1002/ecja.1036.

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AbstractA pulse can be viewed as a kind of memory with faster processing elements, because the information carried by the pulse can be read out at any time by the faster processing elements. Taking this into consideration, one of the authors proposed a TDM switching system which in principle requires no random access memories, but rather only logical gates. This is very much suited to the photonic TDM switching system, as optical RAMs are not as yet available.This paper newly proposes a photonic TDM switching system in which a time jumper is placed on a highway link connecting multistage variable multiplexer and multistage variable demultiplexer. It discusses the system concept, jumpering algorithm, jumper configuration, traffic characterization of the system, optimal system configuration, and finally applications of the system. The characteristics in terms of cost/erl are better than those of the system proposed before. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(9): 1–15, 2001

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Kim, Jungho, Jaehyoung Park, Seunghwan Chung, Namkyoo Park, Byoungho Lee, and Kitae Jeong. "Bidirectional wavelength add/drop multiplexer using two separate MUX and DEMUX pairs and reflection-type comb filters." Optics Communications 205, no. 4-6 (2002): 321–27. http://dx.doi.org/10.1016/s0030-4018(02)01387-1.

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Lv, Zhixiao, Jiangbing Du, and Zuyuan He. "On-Chip Multichannel Dispersion Compensation and Wavelength Division MUX/DeMUX Using Chirped-Multimode-Grating-Assisted Counter-Directional Coupler." Photonics 11, no. 2 (2024): 110. http://dx.doi.org/10.3390/photonics11020110.

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On-chip optical dispersion compensation and wavelength division multiplexing/demultiplexing (WDM) are highly demanded functions for optical communications. In this work, we proposed a multichannel dispersion compensation structure based on chirped multimode grating within a counter-directional coupler (CMG-CDC). Simultaneous wavelength division multiplexing and demultiplexing can be realized within a compact footprint. A device design for four-channel CMG-CDC at the C/L (1530–1565 nm) band is presented with a channel spacing of 20 nm assisted by a grooved multimode waveguide structure. The average dispersion for all channels is about −2.25 ps/nm with a channel bandwidth of about 3.1 nm. The device is highly compact and highly scalable, which makes it rather convenient for increasing the group velocity dispersion (GVD) and channel number, indicating flexible applications for versatile systems, including typically coarse wavelength division multiplexer four-lane (CWDM4) transceivers.

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Ren, Fang, Tianwen Zhangsun, Xiang Lu, et al. "Spatial-mode switchable, multi-wavelength all-fiber erbium-doped fiber (EDF) laser based on low modal crosstalk mode multiplexer/demultiplexer (MUX/DEMUX)." Laser Physics 29, no. 7 (2019): 075105. http://dx.doi.org/10.1088/1555-6611/ab1839.

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REIN, H. M. "Si AND SiGe BIPOLAR ICs FOR 10 TO 40 Gb/s OPTICAL-FIBER TDM LINKS." International Journal of High Speed Electronics and Systems 09, no. 02 (1998): 347–83. http://dx.doi.org/10.1142/s0129156498000178.

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This paper gives an overview on very-high-speed ICs for optical-fiber systems with restriction to Si-based technologies. As a main aim, the circuit and system designer shall get an impression what operating speeds have already been achieved and, moreover, get a feeling for potential limitations. It is shown that all ICs in 10 Gb/s TDM systems can be fabricated in Si-bipolar production technologies, while for the speed-critical ICs in 20 Gb/s systems, present SiGe laboratory technologies are required if the circuit specifications, apart from the data rate, must remain unchanged. With uncritical circuits like time-division multiplexer (MUX) and demultiplexer (DEMUX), record data rates of 60 Gb/s systems were achieved with a SiGe laboratory technology, using an adequate mounting and measuring technique. Recent measuring results even showed that all ICs in a 40 Gb/s TDM system (i.e., also the speed-critical ones) can be realized in advanced SiGe technologies. However, compared to ICs in 10 and 20 Gb/s systems, some circuit specifications must be relaxed. This is possible by the use of optical amplifiers and improved opto-electronic components as well as by system modifications, which further make possible the elimination of some of the speed-critical circuits. It should be noted that all the experimental results presented are measured on mounted chips, using conventional wire bonding, and that most of the circuits have been used in experimental TDM links.

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Charles, Ipshitha, Sandip Swarnakar, Geetha Rani Nalubolu, Venkatrao Palacharla, and Santosh Kumar. "An All Optical 2 × 1 Multiplexer Using a Metal-Insulator-Metal based Plasmonic Waveguide for Processing at a Rapid Pace." Photonics 10, no. 1 (2023): 74. http://dx.doi.org/10.3390/photonics10010074.

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This study proposes, designs, and simulates a unique plasmonic Y-shaped MIM waveguide based 2 × 1 multiplexer (MUX) structure utilising opti-FDTD software. Two plasmonic Y-shaped waveguides are positioned facing one another inside a minimum wafer size of 6 µm × 3.5 µm in the 2 × 1 MUX configurations that is being described. The design parameters are adjusted until the plasmonic multiplexer performs as required under optimal conditions. Extinction ratio and insertion loss are two performance metrics that are calculated for performance analysis of the design, which indicate the potential to be applied in plasmonic integrated circuits.

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Anjum, Nikhat, Anil Kumar Shukla, and Vijay Nath. "Design and Analysis of all Optical Multiplexers using 2D Photonic Crystal." International Journal of Microsystems and IoT 2, no. 3 (2024): 663–69. https://doi.org/10.5281/zenodo.11107841.

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 The development of an all-optical, two-dimensional photonic crystal waveguide multiplexer (MUX) for optical signal processing and networking is the focus of this study. The paper proposes the design of 4<strong>×</strong>1 all optical multiplexer based on 2-D photonic crystal. The architecture, which has an air-filled background, uses two silicon square lattice rod T-shaped waveguides and one silicon square lattice rod Y-shaped waveguide. All-optical MUX developed the use of nonlinear materials, such as Kerr, to address challenges of less profit and nonlinearity. The beam-interference phenomena serve as the inspiration for this design. The performance of the optical MUX is modelled using a finite-difference time-domain method, and the results are then verified to employ the 1.55 m wavelength optical field distribution.

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Sherif, Noora H., Mohammed Hussien Ali, and Najim Abdallah Jazea. "Design and implementation reversible multiplexer using quantum-dot cellular automata approach." Bulletin of Electrical Engineering and Informatics 11, no. 6 (2022): 3383–91. http://dx.doi.org/10.11591/eei.v11i6.4307.

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Rapid progress in the field of nanotechnology includes using quantum dot-cellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using QCA technology. The suggested architectural designs are constructed using the Fredkin and controlled-NOT (CNOT) gates. These constructions were designed to simulate using tool QCA designer 2.0.3. The 591 and 1,615 cells would be used by the 4×1 and 8×1 QCA MUX architectures, respectively. The simulation results demonstrate that, when compared to the previous QCA MUX structures, the suggested QCA MUX designs have the best clock latency performance and use of different gate types.

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Noora, H. Sherif, Hussien Ali Mohammed, and Abdallah Jazea Najim. "Design and implementation reversible multiplexer using quantum-dot cellular automata approach." Bulletin of Electrical Engineering and Informatics 11, no. 6 (2022): 3383~3391. https://doi.org/10.11591/eei.v11i6.4307.

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Rapid progress in the field of nanotechnology includes using quantum dotcellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using QCA technology. The suggested architectural designs are constructed using the Fredkin and controlled-NOT (CNOT) gates. These constructions were designed to simulate using tool QCA designer 2.0.3. The 591 and 1,615 cells would be used by the 4×1 and 8×1 QCA MUX architectures, respectively. The simulation results demonstrate that, when compared to the previous QCA MUX structures, the suggested QCA MUX designs have the best clock latency performance and use of different gate types.

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Almatrood, Amjad, Aby K. George, and Harpreet Singh. "Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs." Electronics 10, no. 16 (2021): 1885. http://dx.doi.org/10.3390/electronics10161885.

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Quantum-dot cellular automata (QCA) technology is considered to be a possible alternative for circuit implementation in terms of energy efficiency, integration density and switching frequency. Multiplexer (MUX) can be considered to be a suitable candidate for designing QCA circuits. In this paper, two different structures of energy-efficient 2×1 MUX designs are proposed. These MUXes outperform the best existing design in terms of power consumption with approximate reductions of 26% and 35%. Moreover, similar or better performance factors such as area and latency are achieved compared to the available designs. These MUX structures can be used as fundamental energy-efficient building blocks for replacing the majority-based structures in QCA. The scalability property of the proposed MUXes is excellent and can be used for energy-efficient complex QCA circuit designs.

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Mustafa, Sajjad Mohanad, Gholamreza Karimi, Mazdak Rad Malek Shahi, and Saif Hasan Abdulnabi. "Nanomaterials in Nanophotonics Structure for Performing All-Optical 2 × 1 Multiplexer Based on Elliptical IMI-Plasmonic Waveguides." Nanomaterials and Nanotechnology 2023 (November 8, 2023): 1–13. http://dx.doi.org/10.1155/2023/7790674.

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In this study, an all-optical multiplexer (Mux) based on elliptical insulator-metal-insulator (IMI) plasmonic waveguides is designed. The area of the proposed structure is very small (400 nm × 400 nm) which operates at a wavelength of 1,550 nm. The developed device utilizes constructive and destructive interferences between the input signals and the selector signal. This structure is less complex and has lower loss compared to the previous works. Transmission (T), contrast ratio (CR), modulation depth (MD), insertion loss (IL), and contrast loss (CL) are the five parameters that describe the performance of the plasmonic Mux. The transmission threshold between logic 0 and logic 1 is 0.5. Moreover, the maximum transmission efficiency of the device is 163%. Moreover, based on the MD value of 95.09%, the dimensions of the proposed structure are excellent and optimal. The proposed plasmonic Mux structure contributes substantially to developing an all-optical arithmetic logic unit (ALU) and all-optical signal processing nanocircuits. The finite element method (FEM) simulates the proposed plasmonic multiplexer with COMSOL Multiphysics 5.4 software.

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Zeeshan A, Mohammed, and Dr Kiran V. "Design and Comparison of Full Adder Using TG Based 4:1 MUX." International Journal of Research and Review 9, no. 11 (2022): 91–95. http://dx.doi.org/10.52403/ijrr.20221115.

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The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder. Keywords: Mux, Full Adder, Transmission Gate, CMOS.

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Seo, Hyun-Sik, Cheng Gong, Zhihui Cai, et al. "16.1: Characteristics of Ln‐doped IZO TFT according to the Change of Indium concentration for DeMUX Applications." SID Symposium Digest of Technical Papers 54, S1 (2023): 125–27. http://dx.doi.org/10.1002/sdtp.16241.

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In order to narrow the bezel in high‐end IT and tablets, using switching circuit de‐multiplexer (DeMUX) reduces the number of source D/IC, making small LCD module available. In this study, new oxide TFT material, Ln‐doped InZnO (Ln‐IZO), has been developed. To achieve mobility of > 25cm2 /V.s, study focused on the effect of Indium (In) concentration on the fabrication of Ln‐IZO sputtering target, and fabricated the DeMUX‐equipped 14 inch FHD driven by gate on array (GOA).

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Hsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.

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An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

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Sohan, kumar Dahana, and Hajari Aastha. "Efficient Design of 2 1 MUX Multiplexer using Nanotechnology Based on QCA." International Journal of Trend in Scientific Research and Development 2, no. 6 (2018): 1211–14. https://doi.org/10.31142/ijtsrd18858.

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Quantum Dot Cellular Automata is a new technology which overcomes of the of CMOS limitations. It is an novel advanced nano technology that revolves around the single electron position control. It is one of the most efficient and emerging nano technology which mainly deals with the effect of electrons inside the quantum dots in QCA cell, and it is the best alternative technology in the nano electronics level architectural field. In this paper, we designed a 2 1 Multiplexer, which is more efficient in the term of area and cells to the other designs. Sohan kumar Dahana | Aastha Hajari "Efficient Design of 2:1 MUX (Multiplexer) using Nanotechnology Based on QCA" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-6 , October 2018, URL: https://www.ijtsrd.com/papers/ijtsrd18858.pdf

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Jiang, Chuanpeng, Jinhao Li, Hongchao Zhang, et al. "Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications." Journal of Semiconductors 44, no. 12 (2023): 122501. http://dx.doi.org/10.1088/1674-4926/44/12/122501.

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Abstract We have successfully demonstrated a 1 Kb spin-orbit torque (SOT) magnetic random-access memory (MRAM) multiplexer (MUX) array with remarkable performance. The 1 Kb MUX array exhibits an in-die function yield of over 99.6%. Additionally, it provides a sufficient readout window, with a TMR/R P_sigma% value of 21.4. Moreover, the SOT magnetic tunnel junctions (MTJs) in the array show write error rates as low as 10−6 without any ballooning effects or back-hopping behaviors, ensuring the write stability and reliability. This array achieves write operations in 20 ns and 1.2 V for an industrial-level temperature range from −40 to 125 °C. Overall, the demonstrated array shows competitive specifications compared to the state-of-the-art works. Our work paves the way for the industrial-scale production of SOT-MRAM, moving this technology beyond R&D and towards widespread adoption.

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Baker, Timothy J., and John P. Hayes. "CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design." ACM Transactions on Design Automation of Electronic Systems 27, no. 3 (2022): 1–26. http://dx.doi.org/10.1145/3491213.

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Stochastic computing (SC) is a low-cost computational paradigm that has promising applications in digital filter design, image processing, and neural networks. Fundamental to these applications is the weighted addition operation, which is most often implemented by a multiplexer (mux) tree. Mux-based adders have very low area but typically require long bitstreams to reach practical accuracy thresholds when the number of summands is large. In this work, we first identify the main contributors to mux adder error. We then demonstrate with analysis and experiment that two new techniques, precise sampling and full correlation, can target and mitigate these error sources. Implementing these techniques in hardware leads to the design of CeMux (Correlation-enhanced Multiplexer), a stochastic mux adder that is significantly more accurate and uses much less area than traditional weighted adders. We compare CeMux to other SC and hybrid designs for an electrocardiogram filtering case study that employs a large digital filter. One major result is that CeMux is shown to be accurate even for large input sizes. CeMux's higher accuracy leads to a latency reduction of 4× to 16× over other designs. Furthermore, CeMux uses about 35% less area than existing designs, and we demonstrate that a small amount of accuracy can be traded for a further 50% reduction in area. Finally, we compare CeMux to a conventional binary design and we show that CeMux can achieve a 50% to 73% area reduction for similar power and latency as the conventional design but at a slightly higher level of error.

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Kotb, Amer, Kyriakos E. Zoiros, and Wei Chen. "High-Speed 2x1 Multiplexer with Carrier-Reservoir Semiconductor Optical Amplifiers." Photonics 11, no. 7 (2024): 648. http://dx.doi.org/10.3390/photonics11070648.

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Leveraging the rapid carrier recovery times and minimal polarization sensitivity of carrier-reservoir semiconductor optical amplifiers (CR-SOAs), this study embeds them in a Mach–Zehnder interferometer (MZI) setup to emulate a 2x1 multiplexer (MUX) operating at 120 Gb/s. The focus is on incorporating AND logic gate functionalities into the CR-SOAs-based MZI structure to facilitate high-quality multiplexing. The proposed methodology utilizes the intrinsic gain and phase modulation capabilities of CR-SOAs-based MZI to effectively manipulate data streams. This innovative approach capitalizes on the unique properties of CR-SOAs, such as fast response times and low polarization sensitivity, to achieve optimal signal transmission quality and efficient multiplexing. To assess MUX performance, a quality factor metric is introduced as a comprehensive measure of signal integrity. Through exhaustive simulations and meticulous analysis, the study demonstrates the feasibility of achieving the desired data rate while maintaining superior signal transmission quality. The results underscore the efficacy of CR-SOAs-based MZI as versatile modules for high-speed multiplexing applications, offering unparalleled performance and efficiency. This research represents a significant advancement in understanding optical communication systems and provides valuable insights for optimizing signal quality and mitigating interference in practical real-world scenarios.

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MISHRA, KHUSHBOO, and SHYAM AKASHE. "DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES." International Journal of Nanoscience 12, no. 04 (2013): 1350026. http://dx.doi.org/10.1142/s0219581x13500269.

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The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET.

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Musala, Sarada, P. Durga Vasavi, Avireni Srinivasulu, and Cristian Ravariu. "A Novel Quaternary Half Subtractor Using 2:1 Multiplexer." International Journal of Applied Sciences & Development 4 (January 29, 2025): 1–7. https://doi.org/10.37394/232029.2025.4.1.

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Multiple-valued logic (MVL) is a logic in which there are more than two truth values. MVL is used due to difficulty in interconnection problems in binary system. Carbon nanotube field-effect transistors (CNTFET) is used to design the Quaternary Half Subtractor (QHS) circuit. Sub blocks of Module (0210), Module (1021), Module (2102), Module (3210) using three supply voltage devices and Quaternary Multiplexer 2:1 using pass transistor have designed in this paper. Therefore, compared to existing designs, less no. of transistors are needed. Comparing proposed Half subtractor using 4:1 MUX modules to current one’s reveals that the 2:1 multiplexer-based method leads in lower power usage. These proposed designs have proven to work satisfactorily under a variety of operating situations, including power, delay, and power delay product (PDP).

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Chen, Pao-Lung, and Chun-Chien Tsai. "An Interpolated Flying-Adder-Based Frequency Synthesizer." Journal of Electrical and Computer Engineering 2011 (2011): 1–11. http://dx.doi.org/10.1155/2011/871385.

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This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are derived. A test chip for the proposed interpolated FA-based frequency synthesizer was fabricated in a standard 0.18 μm CMOS technology, and the core area was 0.143 mm2. The output frequency had a range of 33 MHz ~ 286 MHz at 1.8 V with peak-to-peak (Pk-Pk) jitter 215.2 ps at 286 MHz/1.8 V.

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Majeed, Ali H., Esam Alkaldy, Mohd Shamian Zainal, Keivan Navi, and Danial Nor. "Optimal design of RAM cell using novel 2:1 multiplexer in QCA technology." Circuit World 46, no. 2 (2019): 147–58. http://dx.doi.org/10.1108/cw-06-2019-0062.

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Purpose Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay. Design/methodology/approach In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools. Findings The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits. Originality/value A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

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Ying, Yong Jie, and Zaharah Johari. "Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties." Journal of Physics: Conference Series 2622, no. 1 (2023): 012023. http://dx.doi.org/10.1088/1742-6596/2622/1/012023.

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Abstract This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulation, it is found that the GDI approach used the least number of transistors followed by PTL and CMOS. The calculation of the propagation delay exhibits a substantial improvement of more than 95% using the GDI approach. The average power consumption shows a 55.30% and 35.16% reduction when compared to CMOS and PTL respectively. The PDP demonstrates an improvement of more than 95% when compared with conventional CMOS and PTL approaches. The same trend of observation is also achieved for EDP. The variation of the VDD and chirality has a markable effect on the propagation delay and average power consumption. This is a preliminary attempt to evaluate the performance of CNT implementation in MUX. The outcome can become the guideline for engineers working in circuit design using emerging materials for future nanoelectronics applications.

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Dahana, Sohan kumar, and Aastha Hajari. "Efficient Design of 2:1 MUX Multiplexer using Nanotechnology Based on QCA." International Journal of Trend in Scientific Research and Development Volume-2, Issue-6 (2018): 1211–14. http://dx.doi.org/10.31142/ijtsrd18858.

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Jeong, Ju Young, and Moon‐Pyo Hong. "Design of LTPS TFT Current Mode Multiplexer and MUX‐based Logic Gates." Journal of Information Display 9, no. 3 (2008): 1–7. http://dx.doi.org/10.1080/15980316.2008.9652055.

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Prabhakar, Deepika, Shylashree Nagaraja, S. Pranava Koundinya, and Meghana R. "Design and Implementation of D-Flip Flop For Computation in Memory." WSEAS TRANSACTIONS ON ELECTRONICS 16 (February 4, 2025): 46–50. https://doi.org/10.37394/232017.2025.16.5.

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As the number of data-intensive applications has grown, the traditional Von Neumann computer architecture has become constrained. To address the issue, the new technology platform "computation-in-memory" was established. A new design of the D Flip flop implemented in a memory array employing 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed in this study. To implement the D Flip Flop, this design employs a master-slave multiplexer (MUX) architecture. It has a setup time of 94.887ps and a hold time of 97.22ps.

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Prakash, Jogi, Biroju Ravi Kiran, and Parvatham Sathish. "THE EFFICIENT IMPLEMENTATION TO OPTIMIZE POWER AND DELAY USING DATA SELECTOR." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1159–65. https://doi.org/10.21917/ijme.2021.0200.

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The objective of this paper is designing a 16:1 multiplexer using logic gates and CMOS logic. In this research, we have investigated the delay and power modulations of 16:1MUX. This demonstrates that the CMOS technique takes lead as it uses decreased number of transistors, have less capacitances and faster than others. In this research a comparative work is done and made the simulated results and it illustrates the superior nature of CMOS logic design and it dissipates very decreased power and delay. The simulations for the proposed model are done by using Synopsys tool HSPICE under 32 nm BSIM 4 model card for bulk CMOS technology of PTM model and examined the results with varying voltages. The minimum and maximum delay and power dissipation results are 68.82ps, 92.16ps and 103.96µW, 1471.4µW respectively. The overall transistor count we got in the Multiplexer is 282 and this is simulated and we got output waveforms of the MUX by using the advanced tool called HSPICE and they are represented in the results section.

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Widmann, Daniel, Markus Grözing, and Manfred Berroth. "High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology." Advances in Radio Science 16 (September 4, 2018): 99–108. http://dx.doi.org/10.5194/ars-16-99-2018.

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Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

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Yang, Jingfu, Xiaoping Yu, and Rikun Wei. "A low resource consumption Arbiter PUF improved switch component design for FPGA." Journal of Physics: Conference Series 2221, no. 1 (2022): 012011. http://dx.doi.org/10.1088/1742-6596/2221/1/012011.

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Abstract Aiming at the problems of poor uniqueness and high resource consumption of slice after the implementation of Arbiter physical unclonable function (Arbiter PUF) on field programmable gate array (FPGA), a new improved scheme of switch component structure is proposed. The switch component structure of the improved scheme adopts the parallel-connected mode to improve the uniqueness of the circuit, which avoids the cross-connected mode unable to achieve symmetrical layout on FPGA. At the same time, the improved scheme uses lookup tables to construct the structure of programmable delay line (PDL) with a multiplexer (MUX), which can reduce the internal resource consumption of slice while receiving the same 64-bit challenges. The improved scheme was tested on FPGA boards, the uniqueness and steadiness of different switch component schemes are compared and analyzed, and the feasibility of the improved scheme is verified. The results show that in the generation of Arbiter PUF, compared with the conventional scheme, the improved scheme reduces the resource consumption and improves the uniqueness by 22.2%; Compared with the MUX + MUX scheme, the improved scheme saves 50% of resource consumption while maintaining good uniqueness.

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Verma, Nidhi, and Sanjoy Mandal. "Performance analysis of optical micro-ring resonator as all-optical reconfigurable logic and multiplexer in Z-domain." Journal of Nonlinear Optical Physics & Materials 25, no. 01 (2016): 1650013. http://dx.doi.org/10.1142/s0218863516500132.

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Performance and design methodology of [Formula: see text] multiplexer (MUX) and all-optical reconfigurable logic circuit using GaAs–AlGaAs-based optical micro-ring resonator (OMRR) are presented in current paper. Proposed design of reconfigurable logic circuit is capable to perform eight different logic operations. Performances of the logic circuits have been theoretically analyzed using Z-domain modeling. Numerical simulation results confirming the method are explained in the present paper. Proposed circuit is simple, compact, efficient as it have minimum number of OMRR, low operating power, high operating speed and high Q-factor. Different ‘figure of merits’ of the purposed model are calculated from the simulation results.

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Okawa, Kodai, Minju Kim, Kyungyuk Chae та ін. "Direct measurement of the ²⁶Si(α, p)²⁹P reaction at CRIB for the nucleosynthesis in the X-ray bursts". EPJ Web of Conferences 275 (2023): 02009. http://dx.doi.org/10.1051/epjconf/202327502009.

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Several (α, p) reactions with radioactive-ions (RI) in the αp-process are important to characterize X-ray bursts. However, some of them do not have sufficient experimental data, and the 26Si(α, p)29P reaction is one of such reactions. We performed a direct measurement of the reaction in inverse kinematics with a thick target at the CNS RI beam separator (CRIB).We used a multiplexer circuit, Mesytec MUX, to acquire data from many channels of silicon detectors. In this experimental setup, a resonant elastic scattering was measured simultaneously. The details of the experimental conditions and the preliminary results of the analysis are discussed.

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PRAJAKTA, RAVINDRA MORE, and DR. G.M.PHADE PROF. "HIGH SPEED AND LOW POWER FLASH ADC DESIGN." JournalNX - a Multidisciplinary Peer Reviewed Journal 3, no. 9 (2017): 77–79. https://doi.org/10.5281/zenodo.1420628.

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The Analog to Digital converters play an imperative role in todays electronic systems world. Current applications need High Speed and Low Power ADC. Flash ADC is most prevalent not only for its highest transformation rate but also for its use in other ADC types and its varied applications. Traditional N-bit flash ADC necessitates 2N-1 comparator and same number of preamplifier. if we use multiplexer to design FLASH ADC number of Comparator and Preamplifier get reduced also use of mux in Thermometer to binary code encoder will reduce delay which will ultimately reduce overall power consumption ,area and will rise the speed of operation. https://journalnx.com/journal-article/20150447

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Thamatam, Venkata Chalama Reddy, and Karunakar Aliginti. "Enhancing Digital Circuit Performance Using Memristor-Inspired Amplifiers." International Journal of Computational Learning & Intelligence 4, no. 1 (2025): 343–58. https://doi.org/10.5281/zenodo.15123613.

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In this paper, we present the design, implementation, and evaluation of digital logic circuits using Memristor-based technology. The focus is on basic gates, a 2 × 1 multiplexer (MUX), a full adder, a full subtractor, and an amplifier, all implemented using the Cadence Virtuoso platform. The Memristor model employed here shows significant improvements in power efficiency, area reduction, and speed compared to traditional 45-nm CMOS technologies. Our results demonstrate that Memristor-based circuits can achieve up to 71.4% reduction in area, 40% reduction in power consumption, and 54% reduction in delay, highlighting the potential of Memristor technology for future low-power, high-performance digital systems.

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Tamilarasan, Esther, Gracia Nirmala Rani Duraisamy, Muthu Kumaran Elangovan, and Arun Samuel Thankmony Sarasam. "A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques." Micromachines 14, no. 10 (2023): 1816. http://dx.doi.org/10.3390/mi14101816.

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Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of −68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of −5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

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Cui, Yijun, Chongyan Gu, Qingqing Ma, et al. "Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA." Electronics 9, no. 5 (2020): 815. http://dx.doi.org/10.3390/electronics9050815.

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Physical unclonable function (PUF) is a primary hardware security primitive that is suitable for lightweight applications. However, it is found to be vulnerable to modeling attacks using machine learning algorithms. In this paper, multiplexer (MUX)-based Multi-PUF (MMPUF) design is proposed to thwart modeling attacks. The proposed design uses a weak PUF to obfuscate the challenge of a strong PUF. A mathematical model of the proposed design is presented and analyzed. The three most widely used modeling attack techniques are used to evaluate the resistance of the proposed design. Experimental results show that the proposed MMPUF design is more resistant to the machine learning attack than the previously proposed XOR-based Multi-PUF (XMPUF) design. For a large sample size, the prediction rate of the proposed MMPUF is less than the conventional Arbiter PUF (APUF). Compared with existing attack-resistant PUF designs, the proposed MMPUF design demonstrates high resistance. To verify the proposed design, a hardware implementation on Xilinx 7 Series FPGAs is presented. The hardware experimental results show that the proposed MMPUF designs present good results of uniqueness and reliability.

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S, Mohan Das, Ganesh Kumar M, and Shireesha G. "Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 7 (2020): 8–13. http://dx.doi.org/10.46647/ijetms.2020.v04i07.002.

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In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and GDIMUX design is 85.72 nW, 62.53 pS and 5.36 aJ respectively

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Ijjada, Sreenivasa Rao, Ajaykumar Dharmireddy, M. Sushanth Babu, and Lavanya Kotha. "Design and Implementation of Multiplier Accumulator Unit Using Rounding Based Approximation." International Journal of Microsystems and IoT 2, no. 1 (2024): 529–37. https://doi.org/10.5281/zenodo.10715039.

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This paper presents an analysis of the design of a programmable gain amplifier (PGA) based on an instrumentation amplifier. The instrumentation amplifier can be implemented in different ways, including the Single Op amp IA, 2 Op-amp INA, 3 Op-amp INA, Switched Capacitor Instrumentation amplifier (SCIA), Current Feedback Instrumentation amplifier (CFIA), Current Mirror Instrumentation amplifier (CMIA), and others. By adding switches or a multiplexer (Mux) to the amplifier, a precision programmable gain instrumentation amplifier (PG-IA) can be created. The literature suggests various approaches for enhancing the performance parameters of a PGINA, and this study aims to bring together and evaluate these approaches on a unified platform. In this research, an extensive examination of multiple instrumentation amplifier topologies has been carried out, and these topologies have been categorized based on their distinctive characteristics.

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Divya, Sharma, N. Shylashree, Prasad Ramjee, and Nath Vijay. "Analysis of Programmable Gain Instrumentation Amplifier." International Journal of Microsystems and IoT 1, no. 1 (2023): 41–47. https://doi.org/10.5281/zenodo.8191366.

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This paper presents an analysis of the design of a programmable gain amplifier (PGA) based on an instrumentation amplifier. The instrumentation amplifier can be implemented in different ways, including the Single Op amp IA, 2 Op-amp INA, 3 Op-amp INA, Switched Capacitor Instrumentation amplifier (SCIA), Current Feedback Instrumentation amplifier (CFIA), Current Mirror Instrumentation amplifier (CMIA), and others. By adding switches or a multiplexer (Mux) to the amplifier, a precision programmable gain instrumentation amplifier (PG-IA) can be created. The literature suggests various approaches for enhancing the performance parameters of a PGINA, and this study aims to bring together and evaluate these approaches on a unified platform. In this research, an extensive examination of multiple instrumentational amplifier topologies has been carried out, and these topologies have been categorized based on their distinctive characteristics.

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Hussain Shah, Syed Khawar, Ali Hellany, Mahmood Nagrial, and Jamal Rizk. "Novel Approach to Monitoring and Mitigating Power Quality Disturbances in Hybrid Renewable Energy System." Renewable Energy and Power Quality Journal 20 (September 2022): 481–87. http://dx.doi.org/10.24084/repqj20.345.

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Renewable energy sources are continually increasing their share in the energy system. The introduction of Hybrid Renewable Energy Sources (H.R.E.S.) in the electrical power system has gained momentum. The increased share of Renewable sources has resulted in an increase in Power Quality (P.Q.) disturbances at the user and consumer levels. This research will engineers dedicate the P.Q. disturbances produced in the electrical system due to Hybrid Renewable energy sources, especially solar and wind. The research will predict what type of P.Q. disturbances are introduced during power production. The study will focus on a stand-alone Hybrid Renewable Energy System (H.R.E.S.). The energy system data will be collected and used to produce a Fuzzy Logic (F.L.) algorithm to improve the mitigating techniques to reduce P.Q. disturbances. The suggested algorithm analyzes the stored and continuous data from different sources. The data will be collected and used to drive the hardware to take appropriate actions at the mitigation level. The hardware used in the system consists of a Multiplexer (MUX) and different types of filters. The output of the multiplexer chooses the filters. The algorithm will improve the system's efficiency and help the designers improve the system's design capabilities. The monitoring system will help predict what type of P.Q. disturbances are produced when different energy sources are used to produce power. The proposed system monitors these P.Q. disturbances and classifies them according to their severity.

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Djellab, H., N. Doghmane, A. Bouarfa, and M. Kandouci. "Study of the Different Optical Filters in SAC-OCDMA System." Journal of Optical Communications 39, no. 4 (2018): 381–86. http://dx.doi.org/10.1515/joc-2017-0223.

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Abstract Spectral amplitude coding for optical code division multiple access (SAC-OCDMA) networks has received much attention over the last two decades. This article aims to explore the impact of encoder change on different types of optical filters, such as the Gaussian optical filter and the Bessel optical filter, for high data rates and to give an overview on importance of choosing the optimal type of optical filter according to the frequency range selected by the user is 25 and 50 GHz. SAC-OCDMA transmitter utilizes Wavelength Division Multiplexing multiplexer (WDM MUX) as an encoder, to generate a code having low cross-correlation called Random Diagonal code, and spectral direct detection as a detection technique. The change of optical filter, in WDM MUX, directly affects the performance of the system. The results show that the system for 50 GHz, with a WDM MUX, using a Gaussian optical filter has better performance compared to the optical Bessel filter and can reach a bit error rate (BER) of 10−25. SAC-OCDMA system, using a WDM MUX based on Bessel filters with a bit rate of 300Mb/s, achieves a BER of 10−28 which leads us to recommend it for second norm 25 GHz. Moreover, the power received increases by 4 dBm every 20 Km with the increase in the length of the fibre for both filters Bessel and Gaussian. Our work focuses on the two 25 and 50 GHz bands, after a study on the impact of the change of the bandwidth and the order of the different optical filters used according to the BER applied to the different networks of access, such as local area network (LAN).

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Majeed, Ali H. "An ultra-low complexity of 2:1 multiplexer block in QCA technology." Indonesian Journal of Electrical Engineering and Computer Science 21, no. 3 (2021): 1341–46. https://doi.org/10.11591/ijeecs.v21.i3.pp1341-1346.

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The limitations related to CMOS such as power consumption and parasitic capacitance lead scientists to search for new technologies. Quantum-dot cellular automata (QCA) is a CMOS alternative technology that uses charges instead of voltage level for binary representation. In QCA, many metrics are used for circuit differentiation such as delay, complexity and area. In this work, a new simple block of 2:1 QCA-Multiplexer is proposed. The proposed block is more efficient than previous designs by 43%, 53%, 50% and 72% in terms of area, complexity, delay and cost. QCADesigner software is used to design and verify the proposed circuit.

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Ahn, Choi, Lim, and Yu. "Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory." Micromachines 10, no. 10 (2019): 637. http://dx.doi.org/10.3390/mi10100637.

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In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

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Sun, Lili, Zhongxu Jin, Yanchao Liu, Xiaohua Yu, and Ronghua Ni. "A 50 Gb/s 0.42 pJ/b Non-Return-to-Zero Transmitter for Extra-Short-Reach SerDes." Electronics 14, no. 10 (2025): 1955. https://doi.org/10.3390/electronics14101955.

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An energy- and area-efficient non-return-to-zero (NRZ) transmitter with feedforward equalization (FFE) is proposed for an extra-short-reach (XSR) data interface in chiplet-based system in packages (SiPs) and multi-chip modules (MCMs). At the system level, the final-stage 2:1 multiplexer (MUX) in the transmitter is combined with the driver to reduce the hardware and power consumption; at the circuit level, charge-steering-based moderate-swing signal processing further reduces the circuit power consumption and inter-symbol interference. Fabricated in a 28 nm CMOS process with a core area of 0.032 mm2, the prototype NRZ transmitter demonstrates an energy efficiency of 0.42 pJ/b at a data rate of 50 Gb/s with an insertion loss of 10 dB, which makes it a promising candidate for XSR die-to-die (D2D) interfaces.

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Vasantha Rayudu, Kurada Veera Bhoga, Jahagirdar Jahagirdar, and P. Rao. "Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (2020): 158. http://dx.doi.org/10.11591/ijres.v9.i2.pp158-168.

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In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo &amp; Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

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