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Relevant bibliographies by topics / Multiplierless Filter

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Academic literature on the topic 'Multiplierless Filter'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Multiplierless Filter"

1

Yagain, Deepa, and A. Vijaya Krishna. "Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool." VLSI Design 2014 (July 24, 2014): 1–18. http://dx.doi.org/10.1155/2014/280701.

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPG

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Pavlovic, Vlastimir, Dejan Milic, and Jelena Djordjevic-Kozarov. "Shape of impulse response characteristics of linear-phase nonrecursive 2D FIR filter function." Facta universitatis - series: Electronics and Energetics 26, no. 2 (2013): 133–43. http://dx.doi.org/10.2298/fuee1302133p.

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An analytical method for the new class of linear-phase multiplierless 2D FIR filter functions generated by applying the Christoffel-Darboux formula for classical Chebyshev polynomials of the first and the second kind, proposed in [6] was used for designing of linear-phase multiplierless 2D FIR filter described in this paper. Correct transformation from continuous two-dimensional domain into the z domains without residuum and without errors is described. The proposed solution high selectivity is a filter function in the z1 domain, and the Hilbert transformer in the z2 domain. The impulse respon

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Macleod, M. D., and A. G. Dempster. "Multiplierless FIR filter design algorithms." IEEE Signal Processing Letters 12, no. 3 (2005): 186–89. http://dx.doi.org/10.1109/lsp.2004.842270.

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LIAN, YONG. "A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (2003): 643–54. http://dx.doi.org/10.1142/s0218126603001069.

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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that

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Ye, Wenbin. "Multiplierless Multiple-Stage Cascaded FIR Filter Design." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550011. http://dx.doi.org/10.1142/s0218126615500115.

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It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing al

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Aparna, A., and T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.

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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirem

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Pan, Shing-Tai. "CSD-Coded Genetic Algorithm on Robustly Stable Multiplierless IIR Filter Design." Mathematical Problems in Engineering 2012 (2012): 1–15. http://dx.doi.org/10.1155/2012/560650.

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A Canonic-Signed-Digit-(CSD-) coded genetic algorithm (GA) is proposed to find the optimal design of robustly stable infinite impulse response digital filter (IIR). Under the characteristics of the CSD structure, the circuit of the filter can be simplified and also the calculation speed can be raised to increase the hardware’s efficiency. However, the design of CSD has a big challenge: the CSD structure of the system parameters will be destroyed by an optimal design procedure. To solve this problem, in this research a CSD-coded GA is proposed so that the CSD structure can be maintained. Moreov

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Huang, Q., and G. S. Moschytz. "Analog multiplierless LMS adaptive FIR filter structures." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40, no. 12 (1993): 790–94. http://dx.doi.org/10.1109/82.260244.

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Lutovac, M. D., and L. D. Milic. "Approximate linear phase multiplierless IIR halfband filter." IEEE Signal Processing Letters 7, no. 3 (2000): 52–53. http://dx.doi.org/10.1109/97.823523.

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Ye, Wen Bin, and Ya Jun Yu. "Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 11 (2014): 3206–15. http://dx.doi.org/10.1109/tcsi.2014.2327287.

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Dissertations / Theses on the topic "Multiplierless Filter"

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Landy, A. "The design and implementation of multiplierless fir image filters." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383241.

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Birkeland, Guri Kristine. "COMPARING BINARY, CSD AND CSD4 APPROACHES ON THE ASPECT OF POWER CONSUMPTION IN FIR FILTERS USING MULTIPLIERLESS ARCHITECTURES ON FPGAS." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9269.

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<p>The aim of this thesis is to compare several different algorithms of FIR-filter design on the aspect of the amount of power they consume. Three different approaches are presented: One based on binary, two's complement representation of the coefficients in the filter. The second approach is based on CSD representation, and the third approach is based on CSD4 representation of the coefficients. The three approaches are compared due to their overall power consumption when implemented on an FPGA. In theory, representing coefficients in CSD number representation, yields a reduction of non-zero

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Lin, Woei Harng, and 林葦杭. "High Speed Multiplierless Filter Design and Its VLSI Implementation." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/49384509321277101034.

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碩士<br>國立中正大學<br>電機工程學系<br>85<br>FIR濾波器廣泛的使用在信號處理的領域，其中包含有語音處理，陣列處理以及通信方面的應用。在許多FIR的應用中，由於高取樣頻率和及時處理的趨勢，使得一般的信號處理器無法快速處理如此大量的資料，因此高速濾波器的研發是必要的。濾波器中的乘法器可以利用將濾波器的係數轉換成二的次方表示再以移位器來達成，如此高速平行處理的高速無乘法濾波器便可以實現。這種具有以二的冪次方組合而成為係數的濾波器，我們稱之為2PFIR濾波器或者無乘法濾波器。我們發展一套完整的高速數位濾波器設計的流程，此流程可分成三個階層的步驟：1. 理論階層，2. 架構階層，3. 電路階層及積體電路之實現。經由此一流程我們設計出一顆晶片，其具有21個係數，20個輸出/輸入接腳，整塊晶片面積共4.5mm x 4.5mm，利用0.6umCOMPASS SPDM cell library 組合而成。 FIR filters hve

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Cheng, Kai-Yuan, and 鄭凱元. "Multiplierless Multirate FIR Digital Filter / Decimator / Interpolator Module Generator." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/88803277314312304987.

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碩士<br>國立中央大學<br>電機工程研究所<br>91<br>A module generator, which can automate the process of designing high-speed low-complexity multirate FIR digital filters, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. The generator is designed for ma

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Guo, Meng-Xin, and 郭孟鑫. "The Realization of modified comb filter by using Multiplierless FPGAs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/18523948210419750927.

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碩士<br>清雲科技大學<br>電機工程研究所<br>95<br>In general, digital signal Processing systems are implemented by using digital signal processors which execute programmed instructions that define the signal-processing application. This paper presents an efficient and inexpensive technique for implementing comb filter and its related low-pass, high-pass and band-pass filters based on multiplierless FPGA(Field Programmable Gate Array). In the numerical processing, the unsigned number from analog-to-digital converter is transferred to signed number, the multiply operation is replaced by shifting the register an

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Ahmad, Sabbir U. "Design of digital filters using genetic algorithms." Thesis, 2008. http://hdl.handle.net/1828/1294.

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In recent years, genetic algorithms (GAs) began to be used in many disciplines such as pattern recognition, robotics, biology, and medicine to name just a few. GAs are based on Darwin's principle of natural selection which happens to be a slow process and, as a result, these algorithms tend to require a large amount of computation. However, they offer certain advantages as well over classical gradient-based optimization algorithms such as steepest-descent and Newton-type algorithms. For example, having located local suboptimal solutions they can discard them in favor of more promising local so

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Huei-Shan, Lin. "Novel Design of Minimum-Phase and Multiplierless Maximally-Flat FIR Filters." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200517534500.

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Lin, Huei-Shan, and 林慧珊. "Novel Design of Minimum-Phase and Multiplierless Maximally-Flat FIR Filters." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/41072655078034542682.

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碩士<br>國立臺灣大學<br>電信工程學研究所<br>93<br>In part I of this dissertation, a structure is proposed to acquire the maximally flat lowpass FIR filter. The advantage is that the multiplication elements are not included. Only the addition and delay elements are required. Afterward, the 1-dimensional multiplierless maximally flat designs are extended to the 2-dimensional cases to acquire the quasi-circular-shaped or quasi-ellipse-shaped maximally flat FIR filters. Moreover, the spectrum-shifted and spectrum-rotated versions of the basic 2-dimensional maximally flat prototypes have been designed. In part II

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Cardoso, Artur Agostinho dos Santos Capelo. "Design and hardware implementation of multiplierless unit element wave digital filters." Doctoral thesis, 1987. http://hdl.handle.net/10216/11853.

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Cardoso, Artur Agostinho dos Santos Capelo. "Design and hardware implementation of multiplierless unit element wave digital filters." Tese, 1987. http://hdl.handle.net/10216/11853.

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Book chapters on the topic "Multiplierless Filter"

1

Lee, Pter. "An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/3-540-60294-1_124.

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Yli-Kaakinen, Juha, and Tapio Saramki. "A Systematic Algorithm for the Synthesis of Multiplierless Lattice Wave Digital Filters." In Digital Filters. InTech, 2011. http://dx.doi.org/10.5772/16090.

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Conference papers on the topic "Multiplierless Filter"

1

Chatelain, Benoit, and Francois Gagnon. "Multiplierless Evolutionary Filter Design." In 2007 International Symposium on Signals, Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/isscs.2007.4292680.

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Lesnikov, Vladislav, Tatiana Naumovich, and Alexander Chastikov. "Multiplierless IIR Filter Design Technique." In 2021 10th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2021. http://dx.doi.org/10.1109/meco52532.2021.9460199.

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Fang Jie, Yi Ting, and Hong Zhiliang. "Optimal design of multiplierless FIR filter." In 2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03. IEEE, 2003. http://dx.doi.org/10.1109/icasic.2003.1277343.

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Dolecek, Gordana Jovanovic, and Naina Rao Nagrale. "On a Multiplierless FIR Decimation Filter Design." In 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07). IEEE, 2007. http://dx.doi.org/10.1109/icecs.2007.4511153.

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Ranjithkumar S and Thilagam S. "Optimization design approach for multiplierless FIR filter." In 2016 Online International Conference on Green Engineering and Technologies (IC-GET). IEEE, 2016. http://dx.doi.org/10.1109/get.2016.7916784.

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Britto, P. J., J. V. S. P. Rani, A. Selestin Soundarya, B. Vineeth, and P. Vijayakumar. "FPGA realisation of multiplierless FIR filter architectures." In 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN). IEEE, 2015. http://dx.doi.org/10.1109/icscn.2015.7219881.

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Nair, A. R., P. K. Nath, S. Chakrabartty, and C. S. Thakur. "Multiplierless In-filter Computing for tinyML Platforms." In 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID). IEEE, 2024. http://dx.doi.org/10.1109/vlsid60093.2024.00038.

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Saberi, Nezam, Arash Ahmadi, Shahpour Alirezaee, and Majid Ahmadi. "A multiplierless implementation of cascade integrator comb filter." In 2015 International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2015. http://dx.doi.org/10.1109/isscs.2015.7203938.

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Tecpanecatl-Xihuit, J. Luis, Ruth M. Aguilar-Ponce, and Magdy Bayoumi. "Hybrid multiplierless FIR filter architecture based on NEDA." In 2007 IFIP International Conference on Very Large Scale Integration. IEEE, 2007. http://dx.doi.org/10.1109/vlsisoc.2007.4402521.

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Dangra, Komal H., and G. S. Gawande. "Efficient design and implementation of multiplierless FIR filter." In 2016 International Conference on Computing Communication Control and automation (ICCUBEA). IEEE, 2016. http://dx.doi.org/10.1109/iccubea.2016.7860096.

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