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Relevant bibliographies by topics / NAND Gate

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Academic literature on the topic 'NAND Gate'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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Journal articles on the topic "NAND Gate"

1

Jain, Shivkaran, and Arun Kr Chatterjee. "Nand gate architectures for memory decoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 2 (2013): 610–14. http://dx.doi.org/10.24297/ijct.v7i2.3464.

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This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more pow

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An, X., K. M. Geib, M. J. Hafich, et al. "Integrated optical NAND gate." Electronics Letters 28, no. 16 (1992): 1545. http://dx.doi.org/10.1049/el:19920981.

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Sim, Jae-Min, Bong-Seok Kim, In-Ho Nam, and Yun-Heub Song. "Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation." Electronics 10, no. 15 (2021): 1828. http://dx.doi.org/10.3390/electronics10151828.

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A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.

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Shan, Yu Qiong, Chang Ji Shan, Jun Luo, Xiao Pan Li, and Li Zhou. "Calculation of External Resistance of Two Gates' Circuits Connected with Different Loads." Advanced Materials Research 722 (July 2013): 18–22. http://dx.doi.org/10.4028/www.scientific.net/amr.722.18.

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The TTL nand gate cannot be directly connected with the output port of two gates to set a relationship with their output information while the integrated open-collector nand gate can do so by making a proper choice of between the integrated open-collector lines and the resistances.This paper aims to analyze the calculation of, Rp, the externally connected resistance of integrated gate circuit which is made up of open-collector gate, and open-drain gate when the and-not gate, and nor gate of the Loaded gates are discussed respectively.

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Siregar, Helmi Fauzi, and Ikhsan Parinduri. "PROTOYPE GERBANG LOGIKA ( AND, OR, NOT, NAND, NOR ) PADA LABORATORIUM ELEKTRONIKA STMIK ROYAL KISARAN." JURNAL TEKNOLOGI INFORMASI 1, no. 1 (2017): 37. http://dx.doi.org/10.36294/jurti.v1i1.41.

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Abstract - Logic gate prototype aims to meet the needs and smoothness of the teaching and learning process in one of the digital circuit lecture materials. Proof of the logic of OR, AND, NOT, NOR, and NAND gates. The working principle of logic gate prototype is working based on input logic including 0 and 1. For AND logic gates are input multiplication gates consisting of (0,0, 0,1, 1,0, 1,1) and output consists of 1 for high (1) and 3 for low (0). For OR gate is the input sum gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For the NAND gate is the lo

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Unutulmaz, Ahmet. "A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate." Gazi University Journal of Science Part A: Engineering and Innovation 12, no. 1 (2025): 61–71. https://doi.org/10.54287/gujsa.1645022.

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Threshold Logic Gate (TLG) has gained attention with the emergence of novel technologies such as memristors. TLG offers improved performance and lower power dissipation while occupying less silicon area. This paper introduces a novel dynamic clock generator circuit that further enhances TLG performance. The proposed circuit replaces the NAND gate-based approach used for clock generation in differential TLG implementations. It reduces the propagation delay of the TLG while reducing its static power dissipation, an important factor in energy-efficient circuit design. Simulations indicate up to a

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Li, Huang, and Li Feng Lin. "Design of a Digital Breathing Rate Tester Circuit." Applied Mechanics and Materials 556-562 (May 2014): 2161–64. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2161.

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Digital breathing rate tester uses amplifier circuit, filter circuit, shaping circuit, and frequency quadruplicator circuit to process respiration signals. The signals processed are mixed with signals from logic controller circuit, pass the NAND gate, combine with signals from NAND gate and enter the pulse counter circuit. Pulse counter circuit’s digital tube shows the breathing rates.

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N Md, Mohasinul Huq, Mohan Das S, and Bilal N Md. "Estimation of Leakage Power and Delay in CMOS Circuits." International Journal of Engineering Technology and Management Sciences 4, no. 7 (2020): 14–19. http://dx.doi.org/10.46647/ijetms.2020.v04i07.003.

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This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation

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Tanwar, Vanshika. "Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NAND Logic Gate using Open-Source Software eSim." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3972–77. http://dx.doi.org/10.22214/ijraset.2021.37128.

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A real world signals are mostly based on Boolean operators. In simple language Boolean operators are logic gates and logic gates are the building blocks of any circuit. There are different types of logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR. These all-logic gates are implemented using a Boolean function. And all these logic gates internally are implemented using diodes and transistors. And when we implement all these logic gates using transistor and diodes then it comes under logic families. In this paper we are going to do the analysis of NAND GATE using CMOS in 180 nm technology

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Xiong, Qin, Fei Wu, Zhonghai Lu, et al. "Characterizing 3D Floating Gate NAND Flash." ACM SIGMETRICS Performance Evaluation Review 44, no. 1 (2017): 31–32. http://dx.doi.org/10.1145/3143314.3078550.

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Dissertations / Theses on the topic "NAND Gate"

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Cejpek, Miroslav. "Řídicí obvody výukového laboratorního standu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219916.

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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.

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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.

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Efavi, Johnson Kwame. "Metal gate development for nano-CMOS technologies." Aachen Shaker, 2007. http://d-nb.info/988123606/04.

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Markov, Stanislav Nikolaev. "Gate leakage variability in nano-CMOS transistors." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/771/.

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Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach

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Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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Henschel, Wolfgang [Verfasser]. "Dual-Gate Nano-FETs auf SOI : Grundlegende Prozessschritte / Wolfgang Henschel." Aachen : Shaker, 2003. http://d-nb.info/117054469X/34.

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Efavi, Johnson K. [Verfasser]. "Metal Gate Development for nano-CMOS Technologies / Johnson K Efavi." Aachen : Shaker, 2008. http://d-nb.info/1162790040/34.

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Cupido, Stephen William John. "Augmentation of a nano-satellite electronic power system using a field-programmable-gate-array." Thesis, Cape Peninsula University of Technology, 2013. http://hdl.handle.net/20.500.11838/1084.

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Thesis is submitted in fulfilment of the requirements for the degree Master of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2013<br>The CubeSat standard has various engineering challenges due to its small size and surface area. The challenge is to incorporate a large amount of technology into a form factor no bigger than 10cm3. This research project investigates the space environment, solar cells, secondary sources of power, and Field-Programmable-Gate-Array (FPGA) technology in order to address the size, weight and power chall

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Shumba, Angela-Tafadzwa. "Channel coding on a nano-satellite platform." Thesis, Cape Peninsula University of Technology, 2018. http://hdl.handle.net/20.500.11838/2768.

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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.<br>The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly

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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.

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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-she

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Books on the topic "NAND Gate"

1

Milano, Università di, ed. Exoteric gate: Nanda Vigo. Skira, 2017.

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Evgeni, Gusev, ed. Defects in high-k gate dielectric stacks: Nano-electronic semiconductor devices. Springer, 2006.

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3

Strayton, George R. Tales of the Jedi Companion: The official companion to the Tales of the Jedi and Freedon Nadd Uprising series by Dark Horse Games. West End Games, 1996.

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4

Kikuchi, Nobuteru. Nihon-gata shin jiyū shugi to wa nani ka: Senryōki kaikaku kara abenomikusu made. Kabushiki Kaisha Iwanami Shoten, 2016.

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5

Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Nano-CMOS gate dielectric engineering. CRC Press, 2012.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2013.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Book chapters on the topic "NAND Gate"

1

Weik, Martin H. "NAND gate." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_12064.

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2

Micheloni, Rino, and Luca Crippa. "3D Floating Gate NAND Flash Memories." In 3D Flash Memories. Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7512-0_5.

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3

Ward, Hubert Henry. "Moving On from the NAND Gate." In Maker Innovations Series. Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9878-7_4.

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4

Sauro, Herbert M. "A Biochemical “NAND” Gate and Assorted Circuits." In Modern Trends in Biothermokinetics. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-2962-0_22.

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Sakai, Yoko, Yoriko Mawatari, Kiyonari Yamasaki, Koh-ichiroh Shohda, and Akira Suyama. "Construction of AND Gate for RTRACS with the Capacity of Extension to NAND Gate." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10604-0_14.

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Boruah, Kuntala, Rashmi Deka, and Jiten Ch Dutta. "A Model to Demonstrate the Universality of DNA-NAND Gate." In Lecture Notes in Electrical Engineering. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4765-7_8.

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Sardar, Rupam, Arkapravo Nandi, Aishi Pramanik, et al. "Artificial Neural Network Design for CMOS NAND Gate Using Sigmoid Function." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8477-8_9.

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Prabhakar, Gyan, Rabindra Kumar Singh, and Abhishek Vikram. "Boosted Clock Generator Using NAND Gate for Dickson Charge Pump Circuit." In Information and Communication Technology for Intelligent Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1747-7_6.

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Bohara, Pooja, and S. K. Vishvakarma. "Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics." In Springer Proceedings in Physics. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_88.

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Malavena, Gerardo. "Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks." In Special Topics in Information Technology. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_4.

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AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenome

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Conference papers on the topic "NAND Gate"

1

Takiguchi, Koichi, and Hironori Nishihara. "Flexible Opto-electronic Logical Gate Circuit Comprising Waveguide-based Interferometer and Photodetector." In Integrated Photonics Research, Silicon and Nanophotonics. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/iprsn.2024.itu2b.3.

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We report an opto-electronic logical gate with flexible operation, which consists of an integrated-optic symmetric Mach-Zehnder interferometer and a balanced photodetector. We show Boolean AND and NAND computations of 40 Gbit/s signals with the gate.

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Sun, Lifei, Pengfei Lyu, and Xiaohui Ren. "Process Window Optimization for Gate Etch Process of 2D NAND." In 2025 Conference of Science and Technology of Integrated Circuits (CSTIC). IEEE, 2025. https://doi.org/10.1109/cstic64481.2025.11017943.

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Rich, Chandler, Wayne Harlow, Becky Muñoz, et al. "Pluck-and-Probe Method for EBIRCH Isolation of Wordline Defects in 3D Replacement Gate NAND." In ISTFA 2024. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0090.

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Abstract Wordline defects in 3D Replacement Gate NAND (RG NAND) are a major issue holding back part functionality and yield. Shorted wordline locations isolated by EBIRCH enable precise lamella preparation for STEM/TEM, increasing the defect visual rate for physical failure analysis. Due to deprocessing limitations, such as specialized tool requirements, part-specific die preparation knowledge, and the location of the defect in the die, makes preparing samples for successful EBIRCH isolation difficult and time-consuming. A novel sample preparation method for SEM-based nanoprobing has been deve

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Qin, Yixin, Saikat Chakraborty, Zijian Zhao, et al. "Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage." In 2025 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2025. https://doi.org/10.1109/irps48204.2025.10983219.

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Uddin, M. Rakib, Law Foo Kui, Nazri Ahmad, and Zainidi Haji Abdul Hamid. "Silicon photonic NAND gate." In 2017 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR). IEEE, 2017. http://dx.doi.org/10.1109/cleopr.2017.8118621.

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An, Xilin, K. M. Geib, M. J. Hafich, et al. "Single-Mesa Optical Memory and Logic Pixels for Highly Parallel Arrays." In Photonics in Switching. Optica Publishing Group, 1993. http://dx.doi.org/10.1364/ps.1993.sps85.

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A new family of optical logic gates is presented. The two inputs of these devices are separated by wavelength, thus isolating the two signals and reducing cross talk. Experimental results showing the operation of the optical set-reset memory, optical inverter, optical gated latch, optical AND gate and NAND gate are presented. Output on/off contrast ratios ranging from 6 up to over 50 have been obtained.

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Huang, Zhihong, Xing Wei, Grace Zgheib, et al. "NAND-NOR." In FPGA '17: The 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2017. http://dx.doi.org/10.1145/3020078.3021750.

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Long, Hongchang, Xi Zhu, Zhiwei Li, Jietao Diao, Haijun Liu, and Qingjiang Li. "MAGIC NAND within NOR gate." In 2019 IEEE International Workshop on Future Computing (IWOFC). IEEE, 2019. http://dx.doi.org/10.1109/iwofc48002.2019.9078439.

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Hurtado, A., A. P. Gonzalez-Marcos, and J. A. Martin-Pereda. "Low-power vertical cavity NAND gate." In Microtechnologies for the New Millennium 2005, edited by Goncal Badenes, Derek Abbott, and Ali Serpenguzel. SPIE, 2005. http://dx.doi.org/10.1117/12.608468.

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Xiong, Qin, Fei Wu, Zhonghai Lu, et al. "Characterizing 3D Floating Gate NAND Flash." In SIGMETRICS '17: ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. ACM, 2017. http://dx.doi.org/10.1145/3078505.3078550.

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Reports on the topic "NAND Gate"

1

Sorensen, Neil Robert. Failure analysis for the dual input quad NAND gate CD4011 under dormant storage conditions. Office of Scientific and Technical Information (OSTI), 2007. http://dx.doi.org/10.2172/908064.

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