Relevant bibliographies by topics / NAND Gate

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'NAND Gate'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 September 2023

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Journal articles on the topic "NAND Gate"

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Jain, Shivkaran, and Arun Kr Chatterjee. "Nand gate architectures for memory decoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 2 (June 5, 2013): 610–14. http://dx.doi.org/10.24297/ijct.v7i2.3464.

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This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more power efficient than conventional. Source coupled nand is found to be 36% faster and 82% more power efficient than conventional nand gate.
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An, X., K. M. Geib, M. J. Hafich, L. M. Woods, S. A. Feld, F. R. Beyette, G. Y. Robinson, and C. W. Wilmsen. "Integrated optical NAND gate." Electronics Letters 28, no. 16 (1992): 1545. http://dx.doi.org/10.1049/el:19920981.

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Sim, Jae-Min, Bong-Seok Kim, In-Ho Nam, and Yun-Heub Song. "Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation." Electronics 10, no. 15 (July 30, 2021): 1828. http://dx.doi.org/10.3390/electronics10151828.

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A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.
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Shan, Yu Qiong, Chang Ji Shan, Jun Luo, Xiao Pan Li, and Li Zhou. "Calculation of External Resistance of Two Gates' Circuits Connected with Different Loads." Advanced Materials Research 722 (July 2013): 18–22. http://dx.doi.org/10.4028/www.scientific.net/amr.722.18.

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The TTL nand gate cannot be directly connected with the output port of two gates to set a relationship with their output information while the integrated open-collector nand gate can do so by making a proper choice of between the integrated open-collector lines and the resistances.This paper aims to analyze the calculation of, Rp, the externally connected resistance of integrated gate circuit which is made up of open-collector gate, and open-drain gate when the and-not gate, and nor gate of the Loaded gates are discussed respectively.
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Siregar, Helmi Fauzi, and Ikhsan Parinduri. "PROTOYPE GERBANG LOGIKA ( AND, OR, NOT, NAND, NOR ) PADA LABORATORIUM ELEKTRONIKA STMIK ROYAL KISARAN." JURNAL TEKNOLOGI INFORMASI 1, no. 1 (June 1, 2017): 37. http://dx.doi.org/10.36294/jurti.v1i1.41.

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Abstract - Logic gate prototype aims to meet the needs and smoothness of the teaching and learning process in one of the digital circuit lecture materials. Proof of the logic of OR, AND, NOT, NOR, and NAND gates. The working principle of logic gate prototype is working based on input logic including 0 and 1. For AND logic gates are input multiplication gates consisting of (0,0, 0,1, 1,0, 1,1) and output consists of 1 for high (1) and 3 for low (0). For OR gate is the input sum gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For the NAND gate is the logic inverting gate of the AND input gate consisting of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For NOR input logic gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 1 for high (1) and 3 for low (0). For the NOT gate is the inverse gate with input (1, 0) and the output consists of (0,1). Keywords - Logic Gate, Prototype, OR, AND, NOT, NOR, NAND
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Xiong, Qin, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, and Ping Huang. "Characterizing 3D Floating Gate NAND Flash." ACM SIGMETRICS Performance Evaluation Review 44, no. 1 (June 5, 2017): 31–32. http://dx.doi.org/10.1145/3143314.3078550.

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Xiong, Qin, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, and Ping Huang. "Characterizing 3D Floating Gate NAND Flash." ACM Transactions on Storage 14, no. 2 (May 25, 2018): 1–31. http://dx.doi.org/10.1145/3162616.

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Li, Huang, and Li Feng Lin. "Design of a Digital Breathing Rate Tester Circuit." Applied Mechanics and Materials 556-562 (May 2014): 2161–64. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2161.

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Digital breathing rate tester uses amplifier circuit, filter circuit, shaping circuit, and frequency quadruplicator circuit to process respiration signals. The signals processed are mixed with signals from logic controller circuit, pass the NAND gate, combine with signals from NAND gate and enter the pulse counter circuit. Pulse counter circuit’s digital tube shows the breathing rates.
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N Md, Mohasinul Huq, Mohan Das S, and Bilal N Md. "Estimation of Leakage Power and Delay in CMOS Circuits." International Journal of Engineering Technology and Management Sciences 4, no. 7 (November 28, 2020): 14–19. http://dx.doi.org/10.46647/ijetms.2020.v04i07.003.

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This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.
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Tanwar, Vanshika. "Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NAND Logic Gate using Open-Source Software eSim." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3972–77. http://dx.doi.org/10.22214/ijraset.2021.37128.

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A real world signals are mostly based on Boolean operators. In simple language Boolean operators are logic gates and logic gates are the building blocks of any circuit. There are different types of logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR. These all-logic gates are implemented using a Boolean function. And all these logic gates internally are implemented using diodes and transistors. And when we implement all these logic gates using transistor and diodes then it comes under logic families. In this paper we are going to do the analysis of NAND GATE using CMOS in 180 nm technology and has also designed its PCB layout. We are going to carried out the whole simulation of the proposed design of NAND Gate in eSim (Electronic Simulation) Software which is an EDA tool. And by changing the different values of inputs of NAND Gate we are observing respective output in simulation process of eSim.
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Dissertations / Theses on the topic "NAND Gate"

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Cejpek, Miroslav. "Řídicí obvody výukového laboratorního standu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219916.

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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.

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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.
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Efavi, Johnson Kwame. "Metal gate development for nano-CMOS technologies." Aachen Shaker, 2007. http://d-nb.info/988123606/04.

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Markov, Stanislav Nikolaev. "Gate leakage variability in nano-CMOS transistors." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/771/.

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Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface.
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Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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Henschel, Wolfgang [Verfasser]. "Dual-Gate Nano-FETs auf SOI : Grundlegende Prozessschritte / Wolfgang Henschel." Aachen : Shaker, 2003. http://d-nb.info/117054469X/34.

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Efavi, Johnson K. [Verfasser]. "Metal Gate Development for nano-CMOS Technologies / Johnson K Efavi." Aachen : Shaker, 2008. http://d-nb.info/1162790040/34.

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Cupido, Stephen William John. "Augmentation of a nano-satellite electronic power system using a field-programmable-gate-array." Thesis, Cape Peninsula University of Technology, 2013. http://hdl.handle.net/20.500.11838/1084.

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Thesis is submitted in fulfilment of the requirements for the degree Master of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2013
The CubeSat standard has various engineering challenges due to its small size and surface area. The challenge is to incorporate a large amount of technology into a form factor no bigger than 10cm3. This research project investigates the space environment, solar cells, secondary sources of power, and Field-Programmable-Gate-Array (FPGA) technology in order to address the size, weight and power challenges presented by the CubeSat standard. As FPGAs have not yet been utilised in this particular sub-system as the main controller, this research investigates whether or not the implementation of an FPGA-based electronic power supply sub-system will optimise its functionality by overcoming these size weight and power challenges. The SmartFusion FPGA was chosen due to its analogue front end which can reduce the number of peripheral components required by such complex systems. Various maximum power point tracking algorithms were studied and it was determined that the perturb-and-observe maximum power point tracking algorithm best suits the design constraints, as it only requires the measurement of either solar cell voltage or solar cell current, thus further decreasing the component count. The SmartFusion FPGA analogue compute engine allows for increased performance of the perturb-and-observe algorithm implemented on the microcontroller sub-system as it allows for the offloading of many repetitive calculations. A VHDL implementation of the pulse-width-modulator was developed in order to produce the various changes in duty cycle produced by the perturb-and-observe algorithm. The aim of this research project was achieved through the development and testing of a nano-satellite power system prototype using the SmartFusion FPGA from Microsemi with a decreased number of peripheral circuits. Maximum power point was achieved in 347ms at worst case with a 55% decrease in power consumption from the estimated 330mW as indicated in the power budget. The SmartFusion FPGA consumes only a worst case of 148.93mW. It was found that the unique features of the SmartFusion FPGA do in fact address the size weight and power constraints of the CubeSat standard within this sub-system.
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Shumba, Angela-Tafadzwa. "Channel coding on a nano-satellite platform." Thesis, Cape Peninsula University of Technology, 2018. http://hdl.handle.net/20.500.11838/2768.

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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.
The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.
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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.

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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.
This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
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Books on the topic "NAND Gate"

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Milano, Università di, ed. Exoteric gate: Nanda Vigo. Milano, Italy: Skira, 2017.

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Nano-CMOS gate dielectric engineering. Boca Raton: CRC Press, 2012.

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Evgeni, Gusev, ed. Defects in high-k gate dielectric stacks: Nano-electronic semiconductor devices. Dordrecht: Springer, 2006.

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Nihon-gata toshi keikaku to wa nani ka. Kyōto: Gakugei Shuppansha, 2002.

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Hōka daigakuin: Nihon-gata rō sukūru to wa nani ka. Tōkyō: Heibonsha, 2002.

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Strayton, George R. Tales of the Jedi Companion: The official companion to the Tales of the Jedi and Freedon Nadd Uprising series by Dark Horse Games. Honesdale, Pennsylvania, United States of America: West End Games, 1996.

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Jobu-gata koyō shakai to wa nani ka: Seishain taisei no mujun to tenki. Tōkyō: Kabushiki Kaisha Iwanami Shoten, 2021.

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Kikuchi, Nobuteru. Nihon-gata shin jiyū shugi to wa nani ka: Senryōki kaikaku kara abenomikusu made. Tōkyō: Kabushiki Kaisha Iwanami Shoten, 2016.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Wong, Hei. Nano-CMOS Gate Dielectric Engineering. Taylor & Francis Group, 2017.

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Book chapters on the topic "NAND Gate"

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Weik, Martin H. "NAND gate." In Computer Science and Communications Dictionary, 1068. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_12064.

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Micheloni, Rino, and Luca Crippa. "3D Floating Gate NAND Flash Memories." In 3D Flash Memories, 129–65. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7512-0_5.

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Sauro, Herbert M. "A Biochemical “NAND” Gate and Assorted Circuits." In Modern Trends in Biothermokinetics, 133–40. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-2962-0_22.

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Sakai, Yoko, Yoriko Mawatari, Kiyonari Yamasaki, Koh-ichiroh Shohda, and Akira Suyama. "Construction of AND Gate for RTRACS with the Capacity of Extension to NAND Gate." In Lecture Notes in Computer Science, 137–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10604-0_14.

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Boruah, Kuntala, Rashmi Deka, and Jiten Ch Dutta. "A Model to Demonstrate the Universality of DNA-NAND Gate." In Lecture Notes in Electrical Engineering, 67–76. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4765-7_8.

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Prabhakar, Gyan, Rabindra Kumar Singh, and Abhishek Vikram. "Boosted Clock Generator Using NAND Gate for Dickson Charge Pump Circuit." In Information and Communication Technology for Intelligent Systems, 51–60. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1747-7_6.

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Sardar, Rupam, Arkapravo Nandi, Aishi Pramanik, Soumen Bhowmick, De Debashis, Sudip Ghosh, and Hafizur Rahaman. "Artificial Neural Network Design for CMOS NAND Gate Using Sigmoid Function." In Lecture Notes in Electrical Engineering, 99–113. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8477-8_9.

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Bohara, Pooja, and S. K. Vishvakarma. "Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics." In Springer Proceedings in Physics, 567–70. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_88.

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Malavena, Gerardo. "Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks." In Special Topics in Information Technology, 43–53. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_4.

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AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.
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Frank, M. M., and Y. J. Chabal. "Surface and Interface Chemistry for Gate Stacks on Silicon." In Into the Nano Era, 113–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-74559-4_6.

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Conference papers on the topic "NAND Gate"

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Uddin, M. Rakib, Law Foo Kui, Nazri Ahmad, and Zainidi Haji Abdul Hamid. "Silicon photonic NAND gate." In 2017 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR). IEEE, 2017. http://dx.doi.org/10.1109/cleopr.2017.8118621.

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An, Xilin, K. M. Geib, M. J. Hafich, F. R. Beyette, S. A. Feld, S. Y. Robinson, and C. W. Wilmsen. "Single-Mesa Optical Memory and Logic Pixels for Highly Parallel Arrays." In Photonics in Switching. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/ps.1993.sps85.

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A new family of optical logic gates is presented. The two inputs of these devices are separated by wavelength, thus isolating the two signals and reducing cross talk. Experimental results showing the operation of the optical set-reset memory, optical inverter, optical gated latch, optical AND gate and NAND gate are presented. Output on/off contrast ratios ranging from 6 up to over 50 have been obtained.
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Huang, Zhihong, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, and Haigang Yang. "NAND-NOR." In FPGA '17: The 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3020078.3021750.

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Long, Hongchang, Xi Zhu, Zhiwei Li, Jietao Diao, Haijun Liu, and Qingjiang Li. "MAGIC NAND within NOR gate." In 2019 IEEE International Workshop on Future Computing (IWOFC). IEEE, 2019. http://dx.doi.org/10.1109/iwofc48002.2019.9078439.

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Hurtado, A., A. P. Gonzalez-Marcos, and J. A. Martin-Pereda. "Low-power vertical cavity NAND gate." In Microtechnologies for the New Millennium 2005, edited by Goncal Badenes, Derek Abbott, and Ali Serpenguzel. SPIE, 2005. http://dx.doi.org/10.1117/12.608468.

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Xiong, Qin, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, and Ping Huang. "Characterizing 3D Floating Gate NAND Flash." In SIGMETRICS '17: ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3078505.3078550.

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Chan, N., M. F. Beug, R. Knoefler, T. Mueller, T. Melde, M. Ackermann, S. Riedel, M. Specht, C. Ludwig, and A. T. Tilke. "Metal control gate for sub-30nm floating gate NAND memory." In 2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2008. http://dx.doi.org/10.1109/nvmt.2008.4731199.

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Zhu, Xi, Hongchang Long, Zhiwei Li, Hui Xu, Haijun Liu, and Qingjiang Li. "Instability changes the MAGIC NAND gate to the NOR gate." In 2019 IEEE International Workshop on Future Computing (IWOFC). IEEE, 2019. http://dx.doi.org/10.1109/iwofc48002.2019.9078441.

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Luo, Yi, Deniz Mengu, and Aydogan Ozcan. "Diffractive networks form cascadable all-optical NAND gates." In CLEO: QELS_Fundamental Science. Washington, D.C.: Optica Publishing Group, 2022. http://dx.doi.org/10.1364/cleo_qels.2022.fm5h.8.

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A cascadable, all-optical NAND gate based on diffractive networks is presented. The resulting NAND design was cascaded by projecting the output field of one diffractive gate onto another, all-optically performing logical operations, e.g., a half-adder.
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Prise, Michael E., Norbert Streibl, and Maralene M. Downs. "Computational Properties of Nonlinear Optical Devices." In Photonic Switching. Washington, D.C.: Optica Publishing Group, 1987. http://dx.doi.org/10.1364/phs.1987.fb4.

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To design an optical digital computer it is essential to have a cascadable logic gate with a fanin and fanout of at least two. For a complete logical coverage it is necessary to have either a NAND or a NOR gate or have an AND and an OR gate and use dual rail logic to perform a spatial inversion. To built a general purpose computer without a ridiculous number of gates we must have loops in the system. That is the data must flow through the same gates more than once. This means one gate must be able to drive any other identical ones.
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Reports on the topic "NAND Gate"

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Sorensen, Neil Robert. Failure analysis for the dual input quad NAND gate CD4011 under dormant storage conditions. Office of Scientific and Technical Information (OSTI), May 2007. http://dx.doi.org/10.2172/908064.

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