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Dissertations / Theses on the topic 'NAND Gate'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Cejpek, Miroslav. "Řídicí obvody výukového laboratorního standu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219916.

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2

Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.

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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.

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3

Efavi, Johnson Kwame. "Metal gate development for nano-CMOS technologies." Aachen Shaker, 2007. http://d-nb.info/988123606/04.

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4

Markov, Stanislav Nikolaev. "Gate leakage variability in nano-CMOS transistors." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/771/.

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Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach

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5

Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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6

Henschel, Wolfgang [Verfasser]. "Dual-Gate Nano-FETs auf SOI : Grundlegende Prozessschritte / Wolfgang Henschel." Aachen : Shaker, 2003. http://d-nb.info/117054469X/34.

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7

Efavi, Johnson K. [Verfasser]. "Metal Gate Development for nano-CMOS Technologies / Johnson K Efavi." Aachen : Shaker, 2008. http://d-nb.info/1162790040/34.

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8

Cupido, Stephen William John. "Augmentation of a nano-satellite electronic power system using a field-programmable-gate-array." Thesis, Cape Peninsula University of Technology, 2013. http://hdl.handle.net/20.500.11838/1084.

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Thesis is submitted in fulfilment of the requirements for the degree Master of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2013<br>The CubeSat standard has various engineering challenges due to its small size and surface area. The challenge is to incorporate a large amount of technology into a form factor no bigger than 10cm3. This research project investigates the space environment, solar cells, secondary sources of power, and Field-Programmable-Gate-Array (FPGA) technology in order to address the size, weight and power chall

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Shumba, Angela-Tafadzwa. "Channel coding on a nano-satellite platform." Thesis, Cape Peninsula University of Technology, 2018. http://hdl.handle.net/20.500.11838/2768.

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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.<br>The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly

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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.

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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-she

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11

Martin, Nicolas. "Allosteric modulation of pentameric ligand gated ion channels : from the jiggling of atoms to neuropharmacological strategies." Thesis, Strasbourg, 2017. http://www.theses.fr/2017STRAF079/document.

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Les récepteurs pentamériques canaux (pLGICs) sont des récepteurs neuronaux impliqués dans la neurotransmission rapide et qui comprennent les récepteurs suivants : nAchR, GABAR, GlyR or 5HT3R. Lorsqu’ils ne fonctionnent pas correctement ils sont impliqués dans des pathologies comme Alzheimer ou Parkinson. Dans cette étude, nous avons réalisé des simulations de dynamique moléculaire d’un homologue procaryote des pLGICs. Grâce à l’analyse de 2.5 us de simulation nous avons pu capturer la fermeture complète dudit récepteur et décrire un mécanisme de gating. Ce mécanisme en deux étapes, 1) twisting

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Johnson, Timothy Michael. "Strain Monitoring of Carbon Fiber Composite with Embedded Nickel Nano-Composite Strain Gage." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2622.

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Carbon fiber reinforced plastic (CFRP) composites have extensive value in the aerospace, defense, sporting goods, and high performance automobile industries. These composites have huge benefits including high strength to weight ratios and the ability to tailor their properties. A significant issue with carbon fiber composites is the potential for catastrophic fatigue failure. To better understand this fatigue, there is first a huge push to measure strain accurately and in-situ to monitor carbon fiber composites. In this paper, piezoresistive nickel nanostrand (NiNs) nanocomposites were embedde

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Hyatt, Thomas B. "Piezoresistive Nano-Composites: Characterization and Applications." BYU ScholarsArchive, 2010. https://scholarsarchive.byu.edu/etd/2175.

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Innovative multifunctional materials are essential to many new sensor applications. Piezoresistive nano-composites make up a promising class of such materials that have the potential to provide a measurable response to strain over a much wider range than typical strain gages. Commercial strain gages are currently dominated by metallic sensors with a useable range of a few percent strain at most. There are, however, many applications that would benefit from a reliable wide-range sensor. These might include the study of explosive behavior, instrumentation of flexible components, motion detection

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14

Cheriton, Ross. "Electrostatic Control of Single InAs Quantum Dots Using InP Nanotemplates." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/22758.

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This thesis focuses on pioneering a scalable route to fabricate quantum information devices based upon single InAs/InP quantum dots emitting in the telecommunications wavelength band around 1550 nm. Using metallic gates in combination with nanotemplate, site-selective epitaxy techniques, arrays of single quantum dots are produced and electrostatically tuned with a high degree of control over the electrical and optical properties of each individual quantum dot. Using metallic gates to apply local electric fields, the number of electrons within each quantum dot can be tuned and the nature of the

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15

Li, Shuo. "Realization and characterization of Organic Field Effect Transistors and nano-floating gates memories on rigid and flexible substrates." Thesis, Lille 1, 2018. http://www.theses.fr/2018LIL1I011/document.

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Depuis la découverte des polymères conducteurs, de nombreuses études ont été menées afin d’utiliser ces nouveaux matériaux semiconducteurs en tant que couche active de composants électroniques. Dans cette thèse nous nous intéressons à deux composants clés de l’électronique organique : Les transistors à effet de champs et les mémoires à nano-grille flottante seront réalisés à la fois sur des substrats rigides et flexibles. Pour l’optimisation de nos dispositifs, nous avons choisi de travailler sur les interfaces.Tout d’abord, des monocouches auto-assemblées SAMs ont été utilisés pour optimiser

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16

Ingram, Ian David Victor. "New materials and processes for flexible nanoelectronics." Thesis, University of Manchester, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588129.

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Planar electronic devices represent an attractive approach towards roll-to-roll printed electronics without the need for the sequential, precisely aligned, patterning steps inherent in the fabrication of conventional ‘3D’ electronic devices. Self-switching diodes (SSDs) and in-plane-gate field-effect transistors (IPG-FETs) can be patterned using a single process into a substrate precoated with semiconductor.These devices function in depletion mode, requiring the semiconductor to be doped in order for the devices to function. To achieve this, a reliable and controllable method was developed for

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17

Bounouar, Mohamed Amine. "Transistors mono-electroniques double-grille : Modélisation, conception and évaluation d’architectures logiques." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0068/document.

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Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leu

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18

Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TK

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19

Wang, Kuan-Ti, and 王冠迪. "The Study of Wrapped-Select-Gate SONOS Memory with Split-Control- Gate in NAND Array." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/34613891024644221513.

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碩士<br>國立交通大學<br>電子物理系所<br>96<br>For the first time, we propose the novel Wrapped-Select Gate SONOS (WSG-SONOS) memory with split-control gate in NAND architecture. The memory process is not only simple but also compatible with embedded non-volatile memory in conventional standard logic CMOS products. In this thesis, we demonstrate the physical mechanism and elimination of 2nd bit effect in 2 bit/cell operation. The results show that non-ideal 2nd bit effect would not be a consideration for the novel WSG-SONOS memory device with multi-level operation. It effectively increases the reliability of

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20

Yeh, Teng-Hao, and 葉騰豪. "Electrical Study of Vertical Gate (VG) Type 3D NAND Flash Memory Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/72285234100282791022.

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博士<br>國立清華大學<br>電子工程研究所<br>104<br>Throughout the technology development history of NAND Flash memory, the lower chip cost achieved by higher density array is the main driving force for further evolution. For conventional planar 2D NAND, when the critical dimension (CD) is shrunk to 10nm node, it will inevitably encounter numerous challenges in terms of degraded device performance and complex process modules, such as SAQP (Self-Aligned Quadruple Patterning) scheme. In order to keep pursuing more competitive NAND Flash memory, 3D (three dimensional) NAND Flash technology has been rapidly develop

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21

Hao, Shang Lung, and 郝興隆. "The Algorithm and CAD Design of Multiple-level and Multiple- output NAND Gate Network." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/13224551257683353232.

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22

Ho, Ching Yuan, and 何青原. "Study of Tunnel Oxide and Inter-poly Dielectric with WSix Gate for Application in Nano-scale NAND Flash Memory Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/11079680279743839275.

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博士<br>國立清華大學<br>電子工程研究所<br>97<br>The objective of this dissertation is to investigate the feasibility of continued scaling for nanoscale floating gate NAND flash memory by means of integration optimization and novel process application. The analysis of anomalous tunnel oxide re-growth has been clarified and has obtained good reliability from shallow trench isolation modification. The functionality of interpoly dielectric layer constrained by coupling ratio reduction is enhanced using plasma nitridation method; simultaneously, aluminum oxide is evaluated as candidate for future interpoly dielec

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23

Kuo, Chin Chia, and 郭晉佳. "The Design and Simulation of BiCMOS D-Flip-Flop, CML Full- Adder, and Four-Phase NAND Gate." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/32475890477362444307.

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碩士<br>國立成功大學<br>電機工程研究所<br>81<br>BiCMOS technology combines Bipolar and CMOS transistors in a common integrated circuit. It significantly enhances speed performance while incurring a negligible power and penalty. Thus BiCMOS can provide applications with CMOS power and ensities at speeds which were previously the exclusive domain of bipolar. The analysis and circuit design of BiCMOS circuits for this thesis focus on the high speed BiCMOS logic gates, including the merged BiCMOS D-type Flip-

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24

Twu, Horng-Tay, and 涂宏泰. "Synthesis of multilevel multioutput NAND gate logic network and its CAD design using permissible cubes and PCRM graph." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/41329223087882599806.

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碩士<br>中原大學<br>電子工程學系<br>82<br>The subject of two-level logic synthesis is well developed and well understood. In contrast, multilevel logic synthesis is less studied, more difficult, and relatively new. Nevertheless, multilevel logic synthesis has received most attention by CAD researchers, because (1) it enables circuitry sharing among the multiple functions, (2) there is usually an area/delay tradeoff for the implementations of a Boolean function. Namely, multi- level logic synthesis

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Tu, Hong-Tai, and 涂宏泰. "Synthesis of multilevel multioutput NAND gate logic network and its CAD design using permissible cubes and PCRM graph." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/93477997437216230669.

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26

Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. https://etd.iisc.ac.in/handle/2005/1080.

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With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and predic

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Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. http://hdl.handle.net/2005/1080.

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With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and predic

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28

Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, 2009. https://tud.qucosa.de/id/qucosa%3A25930.

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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung Abstract 1 Einleitung 2 Grundlagen aktiver Halblei

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29

Wu, Ya-Huan, and 吳亞桓. "Gate Resistance Impacts on Nano-meter CMOS Technology." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/qvncuu.

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30

Chih-Hsin, Cheng. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0006-1601200609214200.

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31

Hsu, Wen-Liang, and 許紋梁. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano MOS Device." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81277873797449488530.

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碩士<br>國立臺北科技大學<br>自動化科技研究所<br>91<br>Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks

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32

Chih-Hsin, Cheng, and 鄭稚信. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/4dk7b5.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>92<br>Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlene

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33

Cheng, Chih-Hsin, and 鄭稚信. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/27mbs3.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>94<br>Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks in devi

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34

Hsu, Meng-Kai, and 許孟凱. "Studies on Nano/Micro Gate Microwave Field-Effect Transistors." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/23609531073383607761.

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碩士<br>國立臺灣海洋大學<br>電機工程學系<br>92<br>Meng-Kai Hsu* Wen-Shiung Lour** Shiou-Ying Cheng** Department of Electrical Engineering National Taiwan Ocean University, Keelung, Taiwan, R.O.C Abstract In this thesis, we report on the sub-0.5-mm and sub-0.25mm gate-length field-effect transistor (FET) processing technique by using conventional i-line (λ=365 nm) optical lithography. The key methodology of sub-0.5mm is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal

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35

Lee, Y. J., та 李毅君. "Characteristics of High κ Gate Dielectrics for Nano Electronics". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80333969390187135580.

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碩士<br>國立清華大學<br>材料科學工程學系<br>93<br>The rapid shrinkage of transistor feature size in Si CMOS technology is now facing a great challenge, namely the thickness of the critical gate oxide thickness is now approaching to the quantum tunneling limit. An immediate remedy is to identify alternative high �� gate dielectrics replacing SiO2 in the near future by year 2007. The ultimate solution will likely be found in adopting compound semiconductors that offer competitive advantages over Si in high-speed computations, and microwave high power applications. Hafnium oxides, HfO2 with a ��nof 20 was shown

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Chen, Chien-Liang, and 陳建良. "An Electrical and Reliability Study of High-k Gate Dielectric/ Metal Gate Device for nano-scale CMOS technologies." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/77210016539167467785.

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37

李子寬. "A Study of High Voltage Gate to Gate Coupling Floating Field Plate MOSFET by CMOS nano-scale Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/15761168961210428026.

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碩士<br>國立清華大學<br>電子工程研究所<br>102<br>Over the past few decades, the importance of sustainable development had been rooted in people’s mind deeply. Therefore, the energy harvesting and power IC technology becomes the key issues. How to get a good balance between the breakdown voltage and the on-resistance is critical in designing power devices. Typical power devices are fabricated by special process that need the extra wire bonding to connect the system circuit and the power device. So the high cost is a major problem of this. The general MOSFET’s breakdown voltage is affected by surface peak e

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38

Shao, Chi Shen, and 邵繼聖. "Study of Novel Nano-Scale Multi-Gate Junctionless Field Effect Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4acdu6.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and les

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39

Chen, Hung-Bin, and 陳弘斌. "Gate-All-Around Nano-wire Channel Transistors and Nonvolatile Memory Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/39836199160952168576.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>101<br>This thesis is divided into five parts to demonstrate 3D IC applicable nonvolatile memories and thin-film transistors with nanostructures. In the first part, a poly-Si thin-film flash NVM with a Si-nanocrystal (Si-NC) embedded charge trapping layer through self-assembly processes has been presented. Experimental results indicate that memories with the Si-NC charge trapping layer exhibits high retention and endurance characteristics. After 10k P/E cycles, the data retention is remarkable for NVM applications due to the deep quantum well of Si-NC encapsulat

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Lee, Hai-Ming, and 李海明. "Functional Reliability Study of MOS Transistors with Nano-Scale Gate Oxides." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/00212883958107943667.

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博士<br>國立清華大學<br>電子工程研究所<br>91<br>In this study, functional reliability of MOS transistors with oxide thickness ranging from 3.3 nm down to 1.2 nm is investigated in detail. In contrast with most reliability tests which focus on oxide reliability, various mechanisms resulting in transistor performance degradation are examined, while the on-state drain conduction current and off-state drain leakage current are the two most decisive device parameters that dominates MOS transistor functional reliability in the ultra-thin oxide regime. The degradation of off-state drain leakage current is caused by

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Chia-WeiHsu and 許家維. "Studies of High Performance Poly and High-k Metal Gate Nano Scaled MOSFET with Novel Gate and Channel Structures." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/11031971107102510230.

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羅正愷. "A Study on the Multi-gate TiN Nano-crystal Non-volatile Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/96500211272564548080.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>In this thesis, we proposed a trapping layer engineered n-channel multi-gate TiN nano-crystal non-volatile memories on SOI wafer. P+ poly-Si gate and Al2O3 high-K blocking dielectric are used to suppress electron back tunneling current during erase operation and to reduce operation voltage, respectively. TiN nano-crystals are formed by annealing the ALD-deposited TiN/Al2O3 nano-laminate. Small geometry multi-gate TiN nano-crystal non-volatile memory cell with physical gate length of 80nm and physical fin width of 50nm is fabricated. The TiN nano-crystals have di

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Yao, Ming-Jiun, and 姚銘峻. "Fabrication and Quantum Pumping Transport of Multiple-gate Modulated Nano-Channel Devices." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/242hm4.

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碩士<br>國立交通大學<br>電子物理系所<br>92<br>In this thesis, we have studied the quantum transport properties of one dimensional channels defined by split-gates in GaAs/AlxGa1-xAs heterostructures. In addition to the observation of the usual quantized conductance plateaus in the clean narrow channels, other interesting transport properties have been investigated with the additional electrostatic confinements via overlaying finger-gates in the channel. In the aspect of nano-pattern fabrication, we have successfully produced different geometric bi-layer metal gates on GaAs/AlGaAs heterostructures by elect

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Chen, Yu, and 陳語. "Ramping Metrology Projecting Breakdown Characteristics of Nano-scaled High-k Gate Dielectric." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/7sbz7s.

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碩士<br>國立臺北科技大學<br>機電整合研究所<br>100<br>CMOS devices have been scaling and improving in order to reduce cost, promote performance, and possess multi-function. Owing to the shrinking of MOSFETs, the thickness of gate dielectric has become much thinner. However, the serious problems of leakage current and reliability due to the thinning oxide also appear. Therefore, using high-k gate dielectrics to replace SiO2 is unavoidable. Among many high-k materials, Hf-based dielectrics are considered as the leading high-k candidates with metal electrode for next generation of CMOS technology. In recent years,

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Lin, Shi-Tin, and 林式庭. "Degradation and breakdown characteristics of thin gate oxide under nano-scaled stresses." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/21700578005619791054.

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博士<br>國立暨南國際大學<br>電機工程學系<br>96<br>The main purpose of this thesis is to understand the degradation and breakdown characteristics of thin gate oxide under nano-scaled electrical stresses. Recently, a number of research results published in the literature indicate that the mechanism of oxide degradation and breakdown is an extremely localized phenomenon which has been confirmed to occur in the range of 10-14 ~10-12 cm2. Thus, conventional oxide reliability tests can only provide us average information under the gate area for oxide degradation and breakdown because the gate area of the MOS device

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Heng-YuChou and 周恆宇. "Investigation of nano-structured TaN metal gate thin films using reactive sputtering." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/95485425931436446257.

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碩士<br>國立成功大學<br>材料科學及工程學系碩博士班<br>100<br>In this research, TaN is used as a metal gate due to its excellent conductivity, thermal stability, and tunable work function. A reactive magnetron sputtering system is used to deposit TaN thin films with various deposition parameters, such as the working pressures and deposition powers. The film thickness is measured by a profilometer. The sheet resistance is characterized by a four-point probe. The surface morphology and structures are characterized by scanning electron microscopy and X-ray diffraction, respectively. The electrical results are charact

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Lee, Chih-Peng, and 李志鵬. "The Weibull Distribution of Thin Gate Oxide Subjected to Nano-scaled Electrical Stress." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/43131426663187013412.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>95<br>In this thesis, we used conductive atomic force microscopy (C-AFM) in conjunction with semiconductor parameter analyzer (HP4156C) to study the degradation and breakdown behavior of thin gate oxide under nano-scaled stress with different oxide thickness at various stress conditions. Weibull distribution was used in this work to analyze the oxide breakdown events statistically. The C-AFM conductive tip acting as the metal gate electrode in a traditional metal oxide semiconductor (MOS) capacitor for electrical measurements was placed in contact with the bare oxid

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Tsai, Chia-Chou, and 蔡佳州. "Study on Nano-Scaled Poly-Si Thin-Film Transistor with Stacked Gate Dielectric." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/14052982472738530877.

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碩士<br>國立交通大學<br>電子工程系所<br>94<br>In this thesis, we have proposed and fabricated the SONOS-TFT with nanowire structure. The SONOS-TFTs can be used on the high performance driving device application and nonvolatile memory device application. For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior

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Wang, Yu-Chun, and 王育群. "Two Novel Capacitorless One-Transistor DRAMs with Multi-Gate and Nano-Pillar Structures." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62848552400920872265.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>103<br>In this thesis, we propose two novel capacitorless 1T-DRAMs, with the multi-gate and nano-pillar structures : The first type is a double-gate Nanowire TFT, with the fin-gate and pillar-body structure (FGPB). The second type is a vertical current bridge MOSFET, with the gate-all-around and nano-pillar structure (GAANP). We adopt the GIDL mechanism as 1T-DRAM programming method, and use the Sentaurus TCAD 12.0 simulation tool to confirm the memory performance. Compared with the conv. DG-NTFT, the FGPB device has nano-pillar structure, which can increase the ps

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Lin, Chien-Ting, and 林建廷. "The Study of Advanced Strain Engineering andFUSI-gate for Nano Meter CMOSFET Technology Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/41588497245907279700.

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博士<br>國立成功大學<br>微電子工程研究所碩博士班<br>96<br>In this dissertation, we study the impact of strain engineering and FUSI-gate technologies on nano meter scale MOSFETs performances in detail. The study is divided in five parts. First, we propose three types of the new strain engineering in FUSI-gate MOSFET. Three strain sources on FUSI are studied and analyzed, including enveloped FUSI phase transfer induced stress, the second-CESL induced stress, and the first CESL on poly-gate top removed by FUSI CMP. Second, we propose a simple CMOS FUSI process, which has the work function near to the N or PMOSFET ba

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