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Cejpek, Miroslav. "Řídicí obvody výukového laboratorního standu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219916.
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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.
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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.
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Efavi, Johnson Kwame. "Metal gate development for nano-CMOS technologies." Aachen Shaker, 2007. http://d-nb.info/988123606/04.
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Markov, Stanislav Nikolaev. "Gate leakage variability in nano-CMOS transistors." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/771/.
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Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface.
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Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.
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Henschel, Wolfgang [Verfasser]. "Dual-Gate Nano-FETs auf SOI : Grundlegende Prozessschritte / Wolfgang Henschel." Aachen : Shaker, 2003. http://d-nb.info/117054469X/34.
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Efavi, Johnson K. [Verfasser]. "Metal Gate Development for nano-CMOS Technologies / Johnson K Efavi." Aachen : Shaker, 2008. http://d-nb.info/1162790040/34.
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Cupido, Stephen William John. "Augmentation of a nano-satellite electronic power system using a field-programmable-gate-array." Thesis, Cape Peninsula University of Technology, 2013. http://hdl.handle.net/20.500.11838/1084.
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Thesis is submitted in fulfilment of the requirements for the degree
Master of Technology: Electrical Engineering
in the Faculty of Engineering
at the Cape Peninsula University of Technology
2013The CubeSat standard has various engineering challenges due to its small size and surface area. The challenge is to incorporate a large amount of technology into a form factor no bigger than 10cm3. This research project investigates the space environment, solar cells, secondary sources of power, and Field-Programmable-Gate-Array (FPGA) technology in order to address the size, weight and power challenges presented by the CubeSat standard. As FPGAs have not yet been utilised in this particular sub-system as the main controller, this research investigates whether or not the implementation of an FPGA-based electronic power supply sub-system will optimise its functionality by overcoming these size weight and power challenges. The SmartFusion FPGA was chosen due to its analogue front end which can reduce the number of peripheral components required by such complex systems. Various maximum power point tracking algorithms were studied and it was determined that the perturb-and-observe maximum power point tracking algorithm best suits the design constraints, as it only requires the measurement of either solar cell voltage or solar cell current, thus further decreasing the component count. The SmartFusion FPGA analogue compute engine allows for increased performance of the perturb-and-observe algorithm implemented on the microcontroller sub-system as it allows for the offloading of many repetitive calculations. A VHDL implementation of the pulse-width-modulator was developed in order to produce the various changes in duty cycle produced by the perturb-and-observe algorithm. The aim of this research project was achieved through the development and testing of a nano-satellite power system prototype using the SmartFusion FPGA from Microsemi with a decreased number of peripheral circuits. Maximum power point was achieved in 347ms at worst case with a 55% decrease in power consumption from the estimated 330mW as indicated in the power budget. The SmartFusion FPGA consumes only a worst case of 148.93mW. It was found that the unique features of the SmartFusion FPGA do in fact address the size weight and power constraints of the CubeSat standard within this sub-system.
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Shumba, Angela-Tafadzwa. "Channel coding on a nano-satellite platform." Thesis, Cape Peninsula University of Technology, 2018. http://hdl.handle.net/20.500.11838/2768.
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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.
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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.
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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
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Martin, Nicolas. "Allosteric modulation of pentameric ligand gated ion channels : from the jiggling of atoms to neuropharmacological strategies." Thesis, Strasbourg, 2017. http://www.theses.fr/2017STRAF079/document.
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Les récepteurs pentamériques canaux (pLGICs) sont des récepteurs neuronaux impliqués dans la neurotransmission rapide et qui comprennent les récepteurs suivants : nAchR, GABAR, GlyR or 5HT3R. Lorsqu’ils ne fonctionnent pas correctement ils sont impliqués dans des pathologies comme Alzheimer ou Parkinson. Dans cette étude, nous avons réalisé des simulations de dynamique moléculaire d’un homologue procaryote des pLGICs. Grâce à l’analyse de 2.5 us de simulation nous avons pu capturer la fermeture complète dudit récepteur et décrire un mécanisme de gating. Ce mécanisme en deux étapes, 1) twisting puis 2) blooming semble compatible avec tous les pLGICs. Dans un second temps, nous avons utilisé notre connaissance du mécanisme de gating afin de faire des calculs d’énergie libre le long du twisting, pour différents complexes protéine/ligands. De cette façon, nous avons pu discriminer entre des ligands actifs et inactifs et ainsi fournir des pistes pour le design de nouveaux traitementsPentameric ligand gated ion channels (pLGICs) are brain receptors involved in fast neurotransmission and include nAchR, GABAR, GlyR or 5HT3R. When dysfunctioning, they are involved in diseases such as Alzheimer’s and Parkinson’s. In this study we have performed molecular dynamic simulations of an eukaryotic homologue of the pLGICs (GluCl) to understand the gating mechanism of pLGICs. Thanks to the analysis of two 2.5 us long simulations in which we could capture the full closing of the receptor we described in great details a gating mechanism in two steps, first twisting then blooming, that we believe applicable to the whole pLGICs family. In a second time we used our description of the gating mechanism to perform free energy calculations along the twisting reaction coordinate, for various ligands in complex with GluCl. Doing so we could show a significant difference between IVM-bound and non-bound states and provide hints for the design of new treatments
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Johnson, Timothy Michael. "Strain Monitoring of Carbon Fiber Composite with Embedded Nickel Nano-Composite Strain Gage." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2622.
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Carbon fiber reinforced plastic (CFRP) composites have extensive value in the aerospace, defense, sporting goods, and high performance automobile industries. These composites have huge benefits including high strength to weight ratios and the ability to tailor their properties. A significant issue with carbon fiber composites is the potential for catastrophic fatigue failure. To better understand this fatigue, there is first a huge push to measure strain accurately and in-situ to monitor carbon fiber composites. In this paper, piezoresistive nickel nanostrand (NiNs) nanocomposites were embedded in between layers of carbon fiber composite for real time, in situ strain monitoring. Several different embedding methods have been investigated. These include the direct embedding of a patch of dry NiNs and the embedding of NiNs-polymer matrix nanocomposite patches which are insulated from the surrounding carbon fiber. Also, two different polymer matrix materials were used in the nanocomposite to compare the piezoresistive signal. These nanocomposites are shown to display repeatable piezoresistivity, thus becoming a strain sensor capable of accurately measuring strain real time and in-situ. This patch has compatible mechanical properties to existing advanced composites and shows good resolution to small strain. This method of strain sensing in carbon fiber composites is more easily implemented and used than other strain measurement methods including fiber Bragg grating and acoustic emissions. To show that these embedded strain gages can be used in a variety of carbon fiber components, two different applications were also pursued.
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Hyatt, Thomas B. "Piezoresistive Nano-Composites: Characterization and Applications." BYU ScholarsArchive, 2010. https://scholarsarchive.byu.edu/etd/2175.
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Innovative multifunctional materials are essential to many new sensor applications. Piezoresistive nano-composites make up a promising class of such materials that have the potential to provide a measurable response to strain over a much wider range than typical strain gages. Commercial strain gages are currently dominated by metallic sensors with a useable range of a few percent strain at most. There are, however, many applications that would benefit from a reliable wide-range sensor. These might include the study of explosive behavior, instrumentation of flexible components, motion detection for compliant mechanisms and hinges, human-technology interfaces, and a wide variety of bio-mechanical applications where structural materials may often be approximated as elastomeric. In order to quantify large strains, researchers often use optical methods which are tedious and difficult. This thesis proposes a new material and technique for quantifying large strain (up to 40%) by use of piezoresistive nano-composite strain gages. The nano-composite strain gage material is manufactured by suspending nickel nano-strands within a biocompatible silicone matrix. Study and design iteration on the strain gage material requires an improved understanding of the electrical behavior and conduction path within the material when strained. A percolation model has been suggested for numerical approximations, but has only provided marginal results for lack of data. Critical missing information in the percolation model is the nano-strand cluster size, and how that size changes in response to strain. These data are gathered using a dynamic technique in the scanning electron microscope called voltage contrast. Cluster sizes were found to vary in size by approximately 6% upon being strained to 10%. A feasibility study is also conducted on the nano-composite to show its usability as a strain gage. High Displacement Strain Gages (HDSGs) were manufactured from the nano-composite. HDSGs measured the strain of bovine ligament under prescribed loading conditions. Results demonstrate that HDSGs are an accurate means for measuring ligament strains across a broad spectrum of applied deformations.
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Cheriton, Ross. "Electrostatic Control of Single InAs Quantum Dots Using InP Nanotemplates." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/22758.
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This thesis focuses on pioneering a scalable route to fabricate quantum information devices based upon single InAs/InP quantum dots emitting in the telecommunications wavelength band around 1550 nm. Using metallic gates in combination with nanotemplate, site-selective epitaxy techniques, arrays of single quantum dots are produced and electrostatically tuned with a high degree of control over the electrical and optical properties of each individual quantum dot. Using metallic gates to apply local electric fields, the number of electrons within each quantum dot can be tuned and the nature of the optical recombination process controlled. Four electrostatic gates mounted along the sides of a square-based, pyramidal nanotemplate in combination with a flat metallic gate on the back of the InP substrate allow the application of electric fields in any direction across a single quantum dot. Using lateral fields provided by the metallic gates on the sidewalls of the pyramid and a vertical electric field able to control the charge state of the quantum dot, the exchange splitting of the exciton, trion and biexciton are measured as a function of gate voltage. A quadrupole electric field configuration is predicted to symmetrize the product of electron and hole wavefunctions within the dot, producing two degenerate exciton states from the two possible optical decay pathways of the biexciton. Building upon these capabilities, the anisotropic exchange splitting between the exciton states within the biexciton cascade is shown to be reversibly tuned through zero for the first time. We show direct control over the electron and hole wavefunction symmetry, thus enabling the entanglement of emitted photon pairs in asymmetric quantum dots. Optical spectroscopy of single InAs/InP quantum dots atop pyramidal nanotemplates in magnetic fields up to 28T is used to examine the dispersion of the s, p and d shell states. The g-factor and diamagnetic shift of the exciton and charged exciton states from over thirty single quantum dots are calculated from the spectra. The g-factor shows a generally linear dependence on dot emission energy, in agreement with previous work on this subject. A positive linear correlation between diamagnetic coefficient and g-factor is observed.
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Li, Shuo. "Realization and characterization of Organic Field Effect Transistors and nano-floating gates memories on rigid and flexible substrates." Thesis, Lille 1, 2018. http://www.theses.fr/2018LIL1I011/document.
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Depuis la découverte des polymères conducteurs, de nombreuses études ont été menées afin d’utiliser ces nouveaux matériaux semiconducteurs en tant que couche active de composants électroniques. Dans cette thèse nous nous intéressons à deux composants clés de l’électronique organique : Les transistors à effet de champs et les mémoires à nano-grille flottante seront réalisés à la fois sur des substrats rigides et flexibles. Pour l’optimisation de nos dispositifs, nous avons choisi de travailler sur les interfaces.Tout d’abord, des monocouches auto-assemblées SAMs ont été utilisés pour optimiser les interfaces électrode/SCO et diélectrique/SCO de l’OFET : des mobilités de 0.68 cm2V-1S-1 et des rapports on/off ˃106 ont été obtenus. Par la suite, nous avons fabriqué des dispositifs de mémoire à simple grille flottante SFG en utilisant les en nanoparticules (NP) d’or et à double grille flottante DFG en utilisant les NP d’or et des feuillets de graphène comme couches de piégeage de charges. En particulier, les DFG avec PFBT présentent en effet d'excellentes performances (une large fenêtre mémoire de 51 V et un temps de rétention stable et de plus de 108s).Ensuite, nous avons fabriqué tous les dispositifs sur des substrats souples en kapton avec des processus de fabrication simples et à basse température. Ces NFGM flexibles ont été caractérisés et leurs performances mesurées (fenêtre mémoire de 23V). Nous avons également mis en évidence un piégeage multi-niveaux dans les NP. De plus, ces composants ont montré une bonne résistance aux tests de flexibilité et de pliage et une stabilité très satisfaisante (supérieure à 500 cycles)Organic field effect transistor (OFET) and organic based nano-floating gate memory (NFGM) devices are essentially expected to meet emerging technological demands that realizing flexible and wearable electronic devices. The objective of this thesis is to develop and optimize the pentacene OFET and NFGM based on rigid and flexible substrates. First, self-assembled monolayers (SAMs) were used to optimize the OFET, a high mobility of 0.68 cm2V-1S-1 and current on/off ratio ˃106 were obtained. Then, we fabricated single floating gate (SFG) and double floating gate (DFG) memory devices by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers. In particular, the DFG with PFBT exhibits excellent memory performances, including the large memory window of 51 V, and the stable retention property more than 108 s. Third, we fabricated all organics based OFET and NFGM on kapton flexible substrates with simple fabrication process under low temperature. The large memory window of 23 V was obtained, and the multi-level data storage performance was observed for our flexible NFGM devices. In addition, the bending stability/mechanical stability test present high current on /off ratio ˃105, retention time ˃104, as well as cycling exceed 500 cycles. Based on the experiments results of this work, we highlight the efficient ways to optimize the OFET and fabricate the high performances of flexible NFGM by simple fabrication process
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Ingram, Ian David Victor. "New materials and processes for flexible nanoelectronics." Thesis, University of Manchester, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588129.
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Planar electronic devices represent an attractive approach towards roll-to-roll printed electronics without the need for the sequential, precisely aligned, patterning steps inherent in the fabrication of conventional ‘3D’ electronic devices. Self-switching diodes (SSDs) and in-plane-gate field-effect transistors (IPG-FETs) can be patterned using a single process into a substrate precoated with semiconductor.These devices function in depletion mode, requiring the semiconductor to be doped in order for the devices to function. To achieve this, a reliable and controllable method was developed for doping organic semiconducting polymers by the immersion of optimally deposited films in a solution of dopant. The process was shown to apply both semicrystalline and air-stable, amorphous materials indicating that the approach is broadly applicable to a wide range of organic semiconductors.Simultaneously with the development of the doping protocol specialised hot-embossing equipment was designed and constructed and a high-yielding method of patterning the structures of IPG-FETs and SSDs was arrived at. This method allowed for consistent and reliable patterning of features with a minimum line-width of 200nm.Following the development of these doping and patterning processes these were combined to fabricate controllably doped, functioning planar devices. SSDs showed true zero-threshold rectification behaviour with no observed breakdown in the reverse direction up to 100 V. IPG-FETs showed switching behaviour in response to an applied gate potential and were largely free of detectable gate leakage current, verifying the quality of the patterning process.Furthermore, high-performance semiconducting polymer PAAD was synthesised and characterised in field-effect transistors as steps towards its use in planar electronic devices. It was also shown that this material could be doped using the developed immersion doping protocol and that this protocol was compatible with top-gated device architectures and the use of fluoropolymer CYTOP as a dielectric.
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Bounouar, Mohamed Amine. "Transistors mono-electroniques double-grille : Modélisation, conception and évaluation d’architectures logiques." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0068/document.
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Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. Ainsi, le caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d’envisager la réalisation de transistors et de cellules mémoires à haute densité d’intégration, basse consommation. L’objectif principal de ce travail de thèse est d’explorer et d’évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DGSETs dans une approche ‘‘cellules standards’’ ; et iii) l’exploration d’architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l’aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en terme de consommation d’énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiquesIn this work, we have presented a physics-based analytical SET model for hybrid SET-CMOS circuit simulations. A realistic SET modeling approach has been used to provide a compact SET model that takes several conduction mechanisms into account and closely matches experimental SET characteristics. The model is implemented in Verilog-A language, and can provide suitable environment to simulate hybrid SET-CMOS architectures. We have presented logic circuit design technique based on double gate metallic SET at room temperature. We have also shown the flexibility that the second gate can bring in order to configure the SET into P-type and N-type. Given that the same device is utilized, the circuit design approach exhibits regularity of the logic gate that simplifies the design process and leads to reduce the increasing process variations. Afterwards, we have addressed a new Boolean logic family based on DG-SET. An evaluation of the performance metrics have been carried out to quantify SET technology at the circuit level and compared to advanced CMOS technology nodes. SET-based static memory was achieved and performances metrics have been discussed. At the architectural level, we have investigated both full DG-SET based arithmetic logic blocks (FA and ALU) and programmable logic circuits to emphasize the low power aspect of the technology. The extra power reduction of SETs based logic gates compared to the CMOS makes this technology much attractive for ultra-low power embedded applications. In this way, architectures based on SETs may offer a new computational paradigm with low power consumption and low voltage operation. We have also addressed a flexible logic design methodology based on DG-SET transmission gates. Unlike conventional design approach, the XOR / XNOR behavior can be efficiently implemented with only 4 transistors. Moreover, this approach allows obtaining reconfigurable XOR / XNOR gates by swapping the cell biasing. Given that the same device is utilized, the structure can be physically implemented and established in a regular manner. Finally, complex logic gates based on DG-SET transmission gates offer an improvement in terms of transistor device count and power consumption compared to standard complementary SETs implementations.Process variations are introduced through our model enabling then a statistical study to better estimate the SET-based circuit performances and robustness. SET features low power but limited operating frequency, i.e. the parasitics linked to the interconnects reduce the circuit operating frequency as the SET Ion current is limited to the nA range. In term of perspectives: i) detailed studying the impact on SET-based logic cells of process variation and random back ground charge ii) considering multi-level computational model and their associate architectures iii) investigating new computation paradigms (neuro-inspired architectures, quantum cellular automata) should be considered for future works
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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.
Full textAbstract:
Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Wang, Kuan-Ti, and 王冠迪. "The Study of Wrapped-Select-Gate SONOS Memory with Split-Control- Gate in NAND Array." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/34613891024644221513.
Full textAbstract:
碩士國立交通大學
電子物理系所
96
For the first time, we propose the novel Wrapped-Select Gate SONOS (WSG-SONOS) memory with split-control gate in NAND architecture. The memory process is not only simple but also compatible with embedded non-volatile memory in conventional standard logic CMOS products. In this thesis, we demonstrate the physical mechanism and elimination of 2nd bit effect in 2 bit/cell operation. The results show that non-ideal 2nd bit effect would not be a consideration for the novel WSG-SONOS memory device with multi-level operation. It effectively increases the reliability of memory cell for the larger sensing margin of each state. Moreover, we operate the WSG-SONOS memory in 2 bit/cell mode with multi-level operation. The programming and erasing operations are performed by the Source-Side Injection (SSI) and Band-to-Band Tunneling Hot-Hole (BTBTHH), respectively. While operating the memory device in multi-level mode, the slowest program speed would be still less than 30us; the programming current is about 80nA as the wrapped-select gate voltage and word-line gate voltage are 0.45V and 11V, respectively. The fastest erase speed of 8ms is achieved. The main features of this novel device contain the wrapped-select gate and split-control gate. By utilizing the wrapped-select gate to be an assistance gate, the SSI could accomplish the precisely multi-level operation in this memory cell. The SSI programming operation would achieve the low power consumption and high program speed’s characteristics in the memory device. In addition, the split-control gate could effectively decrease the variation of threshold voltage by eliminating the 2nd bit effect disturbance. It would remain the sense margin in this novel memory with multi-level operation. Moreover, the optimum thickness of ONO stack performs excellently for almost no gate disturbance, no read disturbance and long data retention. Even after 10K P/E cycling stress, the error bit wouldn’t happen in such device’s sensing window. As a result, the WSG-SONOS memory with split-control gate in NAND array is very adapted for the 2 bit/cell mode with multi-level operation. It owns the high program speed, low power consumption and high reliability characteristics for the flash memory technology demands. Thus, it has the larger application potential for flash memory market in the future.
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Yeh, Teng-Hao, and 葉騰豪. "Electrical Study of Vertical Gate (VG) Type 3D NAND Flash Memory Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/72285234100282791022.
Full textAbstract:
博士國立清華大學
電子工程研究所
104
Throughout the technology development history of NAND Flash memory, the lower chip cost achieved by higher density array is the main driving force for further evolution. For conventional planar 2D NAND, when the critical dimension (CD) is shrunk to 10nm node, it will inevitably encounter numerous challenges in terms of degraded device performance and complex process modules, such as SAQP (Self-Aligned Quadruple Patterning) scheme. In order to keep pursuing more competitive NAND Flash memory, 3D (three dimensional) NAND Flash technology has been rapidly developed in recent years. 3D NAND Flash memory can improve the device performance by designing a larger cell size. Moreover, it can also achieve lower bit-cost based on the concept of “multiple-layer stack and one critical etching”. Unlike the cell size is relentlessly shrunk in the conventional NAND technology, the 3D NAND Flash memory stacks plural memory layers with relaxed cell size and divides each device by a deep etching scheme, which makes it as a high performance and low cost chip. Via this concept, NAND technology could be effectively scaled in an economic way. Among the 3D NAND Flash architectures ever proposed, each one owns its merits and demerits. After systematic comparison, it is found that the Vertical Gate (VG) type 3D NAND architecture possesses the superiority of smaller cell size than that of Vertical Channel (VC) one. Besides, the sensing current of this architecture will not be degraded when stacking more layers vertically. Therefore, this work analyzes and optimizes the special effects encountered inherently in the VG-type 3D NAND architecture. In Chapter 2, the VG-type 3D NAND array design and structure will be introduced. Furthermore, the corresponding operations and the decoding methods are also revealed in Chapter 2. As to Chapter 3, the “split-page” architecture that previously proposed by Chen et al., will be reviewed and its array efficiency will be discussed. Then we will propose a new string decoding scheme, named stagger string select line (stagger SSL) scheme, to improve the array efficiency from 71% to 81%. The corresponding operations and electrical data of this scheme will also be studied therein. Stagger SSL scheme is a promising method for cost-effective design of VG-type 3D NAND architecture in the future. In 3D NAND process, the process capability of the critical etching module is limited by the highest aspect ratio (AR) that could be achieved by the etching tool. Thus, for a given stack height, we will obtain a higher array capacity by scaling down the thickness of each memory layer. In Chapter 4, the Z-pitch (one poly-silicon and one oxide) reduced from 60nm to 18nm were successfully demonstrated by using two-layer devices. However, the memory margin and read current are degraded accordingly when shrinking the Z-pitch. As to the mechanisms of memory margin degradation, both “Z-interference” and “Z-disturbance” are introduced to explain the Vt (threshold voltage) shift of inhibited transistor. Among them, Z-interference is the major killer of memory margin. Hence, the Z-interference is analyzed in detail in Chapter 5 by eight-layer devices. Aided by simulation verification, the experimental data are analyzed to propose a suitable Z-pitch as the baseline for fabricating VG-type 3D NAND. In addition, several approaches are discussed to suppress the Z-interference and enlarge the memory margin. Not only the Z-pitch factor but also the horizontal distances can directly affect the device performances. Among various horizontal distances, one important parameter is the distance between edge word line (WL) and ground select line (GSL) or string select line (SSL) transistors. In Chapter 6, the distance effect on VG-type 3D NAND array operations, including read current, erase speed, and programming inhibition performance are discussed. Based on experimental and simulation data, the suitable distance will be summarized as a design guideline in the end of Chapter 6. Finally, we will conclude the results from Chapters 3 to 6 to provide important guidelines on the perspectives of fabrication aspect and design aspect. Through these studies, we can well understand its merits and limitations of VG-type 3D NAND architecture.
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Hao, Shang Lung, and 郝興隆. "The Algorithm and CAD Design of Multiple-level and Multiple- output NAND Gate Network." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/13224551257683353232.
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Ho, Ching Yuan, and 何青原. "Study of Tunnel Oxide and Inter-poly Dielectric with WSix Gate for Application in Nano-scale NAND Flash Memory Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/11079680279743839275.
Full textAbstract:
博士國立清華大學
電子工程研究所
97
The objective of this dissertation is to investigate the feasibility of continued scaling for nanoscale floating gate NAND flash memory by means of integration optimization and novel process application. The analysis of anomalous tunnel oxide re-growth has been clarified and has obtained good reliability from shallow trench isolation modification. The functionality of interpoly dielectric layer constrained by coupling ratio reduction is enhanced using plasma nitridation method; simultaneously, aluminum oxide is evaluated as candidate for future interpoly dielectric material. The size effect of word line is mitigated by using process flow design, and then the low sheet resistance is proposed for achieving fast programming speed. The bit line contact with high aspect ratio structure suffered from severe junction leakage owing to silicon substrate loss; a novel selective epitaxial silicon growth technology is proposed as salicide sacrifice layer for junction leakage current reduction. To incorporate our process modification with novel technologies, the floating gate NAND can be easily extend to sub- 50 nm generation. First of all, the advanced high-density plasma (HDP) method for self-aligned shallow trench isolation (SA-STI) suffers from existed moisture during trench gap filling, and then induces abnormal tunneling oxide re-growth; consequently, it probably exhibits poor tunnel oxide qualities. The optimal STI integrated process is proposed to mitigate moisture encroachment of tunnel oxide. Secondly, for nano-scaling dimension of memory cell, coupling capability between control gate and floating gate is gradually degraded, thus program / erase speed both face critical challenge; plasma nitridation of interpoly dielectric are proposed to enhance gate’s coupling and program / erase speed. Besides, solutions of retention problem by oxidation process of bottom oxide are provided. To evaluate higher dielectric constant material as future IPD candidate, SiO2-Al2O3-SiO2 (OAO) stacked film instead of conventional IPD material is studied for thermal resistance, lower current leakage and less electron trap. Thirdly, sheet resistance (Rs) reduction of WSix gate as well as integrated gate process optimization is explored in detail for WSix extrusion investigation and operation speed improvement. Consequently, the selective epitaxial growth silicon (SEG) technique is evaluated to reduce junction leakage for bit line contact without sacrificing contact resistance. To adopt our studying results, the conventional floating fate NAND flash structure is capable of extending to 50 nm node and beyond.
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Kuo, Chin Chia, and 郭晉佳. "The Design and Simulation of BiCMOS D-Flip-Flop, CML Full- Adder, and Four-Phase NAND Gate." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/32475890477362444307.
Full textAbstract:
碩士國立成功大學
電機工程研究所
81
BiCMOS technology combines Bipolar and CMOS transistors in a common integrated circuit. It significantly enhances speed performance while incurring a negligible power and penalty. Thus BiCMOS can provide applications with CMOS power and ensities at speeds which were previously the exclusive domain of bipolar. The analysis and circuit design of BiCMOS circuits for this thesis focus on the high speed BiCMOS logic gates, including the merged BiCMOS D-type Flip-Flop, multi-emitter MOS/ bipolar merged CML full-adder and BiCMOS high-speed four-phase logic gates. The merged BiCMOS D-type Flip-Flop decreases the circuit complexity and the consumption of silicon area, and no more speed degradation as compared to the QC-BiCMOS D-type Flip- Flop. In order to study the performance of the full-adder designed by multi-emitter CML gates, we introduce three different types multi emitter CML full-adders and the comparison between their simulation results are shown. For the purpose to widely apply to high-performance VLSI design, the conventional BiCMOS high-speed four-phase logic gates are presented for higher speed than high- speed precharge-discharge CMOS logic gates. And the proposed QC- BiCMOS high-speed four- phase logic gates are suitable for low supply voltage and smaller dependence on the load capacitance. We investigate these properties from four-phase 3-input NAND gates.
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Twu, Horng-Tay, and 涂宏泰. "Synthesis of multilevel multioutput NAND gate logic network and its CAD design using permissible cubes and PCRM graph." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/41329223087882599806.
Full textAbstract:
碩士中原大學
電子工程學系
82
The subject of two-level logic synthesis is well developed and well understood. In contrast, multilevel logic synthesis is less studied, more difficult, and relatively new. Nevertheless, multilevel logic synthesis has received most attention by CAD researchers, because (1) it enables circuitry sharing among the multiple functions, (2) there is usually an area/delay tradeoff for the implementations of a Boolean function. Namely, multi- level logic synthesis is very flexible. This paper proposes algorithms of synthesizing multilevel multioutput NAND gate logic network. We use ZOI(Zero One Inter- action) of permissible cube to achieve logic synthesis. Only uncomplemented input variables are needed by using the ZOI al- gorithm to synthesis NAND gate logic network. We modify Kar- naugh map into PCRM (Permissible Cube Related Minterm) graph. We use PCRM graph to generate and locate permissible cubes which are required for multilevel NAND gate logic synthesis. Our logic synthesis system includes synthesis of multilevel NAND gate logic network, level reduction of multilevel NAND gate logic network, gate reduction of multilevel NAND gate logic network, and synthesis of multilevel multioutput NAND gate logic network. The level reduction technique reduces cir- cuit delay. The gate reduction technique eliminate redundant gates in the synthesized NAND gate logic network. The proposed logic synthesis system is implemented in C language. The ex- perimental results shows that multilevel logic networks use less gates than two-level logic networks.
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Tu, Hong-Tai, and 涂宏泰. "Synthesis of multilevel multioutput NAND gate logic network and its CAD design using permissible cubes and PCRM graph." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/93477997437216230669.
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Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. https://etd.iisc.ac.in/handle/2005/1080.
Full textAbstract:
With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation.
We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM).
To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets.
Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
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Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. http://hdl.handle.net/2005/1080.
Full textAbstract:
With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation.
We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM).
To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets.
Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, 2009. https://tud.qucosa.de/id/qucosa%3A25930.
Full textAbstract:
Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung
Abstract
1 Einleitung
2 Grundlagen aktiver Halbleiterelemente
2.1 Die MOS-Struktur
2.2 Der MOS-Feldeffekt-Transistor
2.3 Nichtflüchtige Festkörperspeicher
2.4 Speicherarchitekturen
2.5 Charakterisierungsmethoden von Halbleiter-Speicherelementen
3 Defektbasierte Ladungsspeicherung in dielektrischen Schichten
3.1 Physikalische Grundlagen von Haftstellen
3.2 Betrachtung der vertikalen Ladungsverteilung mit Hilfe von Simulationen
3.3 Ableitung der vertikalen Ladungsverteilung aus Messungen
4 Elektrisches Verhalten einer haftstellen-basierten Speicherzelle
4.1 Auswirkung von inhomogen verteilter Ladung in der Speicherschicht
4.2 Auswirkungen von Al2O3-Topoxid auf das Zellverhalten
4.3 Auswirkung des Steuerelektrodenmaterials auf das Zellverhalten
4.4 Einfluss von Kanal- und Source/Drain-Dotierung
5 Integration in eine stark skalierte NAND Architektur
5.1 Auswirkung struktureller Effekte auf die Speicherzelle
5.2 Störmechanismen beim Betrieb von stark skalierten NAND-Speichern
6 Zusammenfassung und Ausblick
6.1 Zusammenfassung
6.2 Ausblick
Danksagung
Lebenslauf
Symbol- und Abkürzungsverzeichnis
Literaturverzeichnis
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Wu, Ya-Huan, and 吳亞桓. "Gate Resistance Impacts on Nano-meter CMOS Technology." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/qvncuu.
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Chih-Hsin, Cheng. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0006-1601200609214200.
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Hsu, Wen-Liang, and 許紋梁. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano MOS Device." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81277873797449488530.
Full textAbstract:
碩士國立臺北科技大學
自動化科技研究所
91
Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks in device processing, design, performance modeling, characterization, parameter extraction and so forth. This thesis proposes some related researches and discussions to describe and characterize the nano device’s characteristics, inclusive of high gate oxide leakage current, tunneling leakage current, punch-through current, I-V & C-V behaviors, reliability, stress condition, temperature dependence effect, frequency dependence effect and so on. We know, in/after 90nm manufacturing generation, there will be more and more technology skills and key-issues waiting for us to improve even completely solute. Hope our research results could provide some contribution to the final nano-issued-solution especially on ultra thin gate oxide leakage issue.
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Chih-Hsin, Cheng, and 鄭稚信. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/4dk7b5.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
92
Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks in device processing, design, performance modeling, characterization, parameter extraction and so forth. This thesis proposes some related researches and discussions to describe and characterize the nano device’s characteristics, inclusive of high gate oxide leakage current, tunneling leakage current, punch-through current, I-V behaviors, reliability, stress condition and so on. We know, in/after 90nm manufacturing generation, there will be more and more technology skills and key-issues waiting for us to improve even completely solute. Hope our research results could provide some contribution to the final nano-issued-solution especially on ultra thin gate oxide leakage issue.
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Cheng, Chih-Hsin, and 鄭稚信. "High Gate Leakage Current Characterization and Analysis of Ultra-thin Gate Oxide Nano PMOS Device." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/27mbs3.
Full textAbstract:
碩士國立臺北科技大學
機電整合研究所
94
Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks in device processing, design, performance modeling, characterization, parameter extraction and so forth. This thesis proposes some related researches and discussions to describe and characterize the nano device’s characteristics, inclusive of high gate oxide leakage current, tunneling leakage current, punch-through current, I-V behaviors, reliability, stress condition and so on. We know, in/after 90nm manufacturing generation, there will be more and more technology skills and key-issues waiting for us to improve even completely solute. Hope our research results could provide some contribution to the final nano-issued-solution especially on ultra thin gate oxide leakage issue.
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Hsu, Meng-Kai, and 許孟凱. "Studies on Nano/Micro Gate Microwave Field-Effect Transistors." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/23609531073383607761.
Full textAbstract:
碩士國立臺灣海洋大學
電機工程學系
92
Meng-Kai Hsu* Wen-Shiung Lour** Shiou-Ying Cheng** Department of Electrical Engineering National Taiwan Ocean University, Keelung, Taiwan, R.O.C Abstract In this thesis, we report on the sub-0.5-mm and sub-0.25mm gate-length field-effect transistor (FET) processing technique by using conventional i-line (λ=365 nm) optical lithography. The key methodology of sub-0.5mm is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. Furthermore, undercutting formed during isotropic etch spin-on-glass film is beneficial to subsequent lift-off process, achieving high fabrication yield. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded InxGa1-xAs multi-layer forming a HEMT-like channel. This digital-graded InxGa1-xAs channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The implemented gate length is as short as 0.41 mm. A fabricated 0.41´100 mm2 HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and f t (f max) of 26 (32) GHz. Separate methodology of sub-0.25mm gate-length FET is the formation of GaAs V-grooves with well-controllable notch angles. The key methodology used to control the notch angle of a V-groove is to preset temperature of etching chemicals. It is found that the notch angle of a V-groove increase with increasing temperature of etching chemicals. Then V-groove gates different notch angle were employed in the fabrication of InGaP/InGaAs heterojunction doped-channel FETs (HDCFETs). Effects of temperature-dependent notch angle on V-groove gate HDCFETs were investigated in detail, including dc, ac performances and short-channel effects. Experimental results reveal that a small notch-angle V-groove gate is very promise for high-frequency applications. Finally, comparisons between simulated results for planar-gate HDCFETs and experimental results for V-groove gate HDCFETs are used to determine the equivalent gate length of a V-groove gate. It is found that the equivalent gate length of a V-groove gate is in the range of 0.1 ~ 0.2 mm. Otherwise; we also investigate the high frequency characteristics of capacitance effects of V-groove edges in detail. * Author ** Advisor
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Lee, Y. J., and 李毅君. "Characteristics of High κ Gate Dielectrics for Nano Electronics." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80333969390187135580.
Full textAbstract:
碩士國立清華大學
材料科學工程學系
93
The rapid shrinkage of transistor feature size in Si CMOS technology is now facing a great challenge, namely the thickness of the critical gate oxide thickness is now approaching to the quantum tunneling limit. An immediate remedy is to identify alternative high �� gate dielectrics replacing SiO2 in the near future by year 2007. The ultimate solution will likely be found in adopting compound semiconductors that offer competitive advantages over Si in high-speed computations, and microwave high power applications. Hafnium oxides, HfO2 with a ���nof 20 was shown recently to be a promising candidate as alternative gate dielectric for both Si and GaAs CMOSFETs due to its suitable band gap, high dielectrics constant, and good thermal stability in contact with Si and GaAs interfaces. Structural characteristics of these thin films were carried out by high resolution transmission electron microscopy (HRTEM) in conjunction with AFM, and X-ray reflectivity measurements. Electrical analysis were by the AGILENT 4284A and AGILENT 4156C to measure the I-V and C-V characteristics.
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Chen, Chien-Liang, and 陳建良. "An Electrical and Reliability Study of High-k Gate Dielectric/ Metal Gate Device for nano-scale CMOS technologies." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/77210016539167467785.
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李子寬. "A Study of High Voltage Gate to Gate Coupling Floating Field Plate MOSFET by CMOS nano-scale Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/15761168961210428026.
Full textAbstract:
碩士國立清華大學
電子工程研究所
102
Over the past few decades, the importance of sustainable development had been rooted in people’s mind deeply. Therefore, the energy harvesting and power IC technology becomes the key issues. How to get a good balance between the breakdown voltage and the on-resistance is critical in designing power devices. Typical power devices are fabricated by special process that need the extra wire bonding to connect the system circuit and the power device. So the high cost is a major problem of this. The general MOSFET’s breakdown voltage is affected by surface peak electric field. It causes the MOSFET’s gate dielectric reliability getting worse. In the previous work, a Floating Field Plate MOSFET (FFP-MOSFET) was fabricated by 28nm CMOS process. With floating gate as its field plate, its depletion region will be extended, reduces the drain-side peak electric-field. However, FFPMOS suffers from large on-resistance. This work presents a GGCFFPMOS which introduce external capacitors between the floating gates. Measurement results show that gated-breakdown voltage is successfully extended. Furthermore, the trade-off between the breakdown voltage and the on-resistance improves. Without special process defined drift region or extra masks, this device is formed by pure logic process and allow for high flexibility.
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Shao, Chi Shen, and 邵繼聖. "Study of Novel Nano-Scale Multi-Gate Junctionless Field Effect Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4acdu6.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
103
In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and less sensitivity of the fin angle to electrical performances by reducing effective channel thickness that is caused by the channel/ substrate junction. Hence, the JL bulk FinFET is highly recommended in sub-10-nm nodes. Additionally, this work demonstrates for the first time the fabrication of a proposed hybrid P/N poly-Si channel junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structure. The novel hybrid P/N JL-TFTs showed excellent electrical performances in terms of a steep subthreshold swing of 64mV/dec, a high Ion/Ioff current ratio (>107), a low drain-induced barrier lowering value of 3 mV/V, small series resistance and temperature stability were investigated, indicating greater gate electrostatic controllability and less current crowding than in conventional JL-TFTs. Furthermore, simulated results and a quantum model physical model were discussed initially but not detailed enough for future work support experimental data. Hence, the proposed hybrid P/N JL-TFT is highly promising for future further sub-10-nm scaling and 3D stacked ICs applications.
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Chen, Hung-Bin, and 陳弘斌. "Gate-All-Around Nano-wire Channel Transistors and Nonvolatile Memory Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/39836199160952168576.
Full textAbstract:
博士國立交通大學
電子工程學系 電子研究所
101
This thesis is divided into five parts to demonstrate 3D IC applicable nonvolatile memories and thin-film transistors with nanostructures. In the first part, a poly-Si thin-film flash NVM with a Si-nanocrystal (Si-NC) embedded charge trapping layer through self-assembly processes has been presented. Experimental results indicate that memories with the Si-NC charge trapping layer exhibits high retention and endurance characteristics. After 10k P/E cycles, the data retention is remarkable for NVM applications due to the deep quantum well of Si-NC encapsulated in the Si3N4 layer and immunity to the enhanced electric field underneath the disk-shaped Si-NCs. In addition, reducing the thickness of the tunnel oxide can further lower the P/E voltage. This investigation examines the feasibility of poly-Si thin-film nonvolatile memory with the Si-NC embedded charge trapping layer on 3-D layer-to-layer stacked high-density NAND memory applications. In the second part, the bimodal shape of bent NWs has an impact on the electrical characteristics of GAA flash memory. Since the dielectric strength is not reduced in the dual-gate cell, the dual-gate GAA poly-Si NWs flash memory has better P/E characteristics and reliability performance than the single-gate memory. Additionally, the incorporation of the Si3N4/Si-NC/Si3N4 hybrid discrete trap layer causes dual-gate devices to exhibit excellent retention (>108 seconds for 17% charge loss). In the third part, The 2-bit effect of GAA NVM with Si NCs through self-assembly processes is investigated. The experimental results reveal that the GAA Si-NCs NVM performs clear 2-bit effect with gate length of 0.5 μm by CHE programming and channel hot holes erasing. At large gate length of 1 μm, F-N tunneling occurred and dominated which resulted in the absence of the 2-bit effect. In the programming and erasing characteristics studies, the gate-all-around structure can reduce operation voltage and shorten pulse time. In the retention characteristics studies, the Si-NCs of confining electrons in the narrow region assist the gate length scaling and lateral migration. In the forth part, A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The planar and GAA structure with ultra-thin channel and a Si3N4/Si-NC/Si3N4 hybrid discrete trap layer are introduced to poly-Si TFT flash memories. The experimental results indicate that ultra-low voltage operation for 3-nm Tch device by drain avalanche hot electron injection (DAHE) condition (Vg, Vd) = (0, <-3V) can process quantum programming. The ultra-thin channel device satisfies with both ultra-low power and high performance applications, and that with Si-NCs performs large memory window and data retention. Finally, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our junctionless device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low IOFF and the steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications.
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Lee, Hai-Ming, and 李海明. "Functional Reliability Study of MOS Transistors with Nano-Scale Gate Oxides." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/00212883958107943667.
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博士國立清華大學
電子工程研究所
91
In this study, functional reliability of MOS transistors with oxide thickness ranging from 3.3 nm down to 1.2 nm is investigated in detail. In contrast with most reliability tests which focus on oxide reliability, various mechanisms resulting in transistor performance degradation are examined, while the on-state drain conduction current and off-state drain leakage current are the two most decisive device parameters that dominates MOS transistor functional reliability in the ultra-thin oxide regime. The degradation of off-state drain leakage current is caused by lately observed oxide soft-breakdown within the gate-to-drain overlap area, and its dominance tends to grow with scaling oxide thickness. Through experimental data analyses and theoretical calculations, we verified the dependences of device lifetime on oxide electric field, failure rate and device dimension. On the basis of physical mechanisms and models, we propose a methodology for MOS transistor functional reliability evaluation and a correlated unified functional reliability model which may contribute to the microelectronics technology development in the near future.
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Chia-WeiHsu and 許家維. "Studies of High Performance Poly and High-k Metal Gate Nano Scaled MOSFET with Novel Gate and Channel Structures." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/11031971107102510230.
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羅正愷. "A Study on the Multi-gate TiN Nano-crystal Non-volatile Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/96500211272564548080.
Full textAbstract:
碩士國立交通大學
電子工程系所
96
In this thesis, we proposed a trapping layer engineered n-channel multi-gate TiN nano-crystal non-volatile memories on SOI wafer. P+ poly-Si gate and Al2O3 high-K blocking dielectric are used to suppress electron back tunneling current during erase operation and to reduce operation voltage, respectively. TiN nano-crystals are formed by annealing the ALD-deposited TiN/Al2O3 nano-laminate. Small geometry multi-gate TiN nano-crystal non-volatile memory cell with physical gate length of 80nm and physical fin width of 50nm is fabricated. The TiN nano-crystals have diameter of 1~2nm. Memory performance of the cells with different thicknesses of TiN layer, blocking layer, and with different anneal time are investigated. It can be found that device using thicker TiN nano-laminate has much larger memory window than the others. The memory exhibits acceptable program and erase speed and little Vt shift saturation. Good 10-year extrapolated charge retention and high endurance after 104 P/E cycles are also exhibited. The small read and gate disturbance characteristics show that the TiN nano-crystal memory cell adapts to the application of NAND type flash memory. Finally, we present a novel memory operation scheme by sensing the level of off-region current after ban-to-band hot hole programming. Negligible memory window narrowing after 106 seconds and low operation voltage have been demonstrated. The mechanism of this operation scheme and outstanding retention performance is not clear at this moment and is worthy to be investigated.
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Yao, Ming-Jiun, and 姚銘峻. "Fabrication and Quantum Pumping Transport of Multiple-gate Modulated Nano-Channel Devices." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/242hm4.
Full textAbstract:
碩士國立交通大學
電子物理系所
92
In this thesis, we have studied the quantum transport properties of one dimensional channels defined by split-gates in GaAs/AlxGa1-xAs heterostructures. In addition to the observation of the usual quantized conductance plateaus in the clean narrow channels, other interesting transport properties have been investigated with the additional electrostatic confinements via overlaying finger-gates in the channel. In the aspect of nano-pattern fabrication, we have successfully produced different geometric bi-layer metal gates on GaAs/AlGaAs heterostructures by electron beam lithography. A layer of PMMA between split-gate and finger-gate layers was made to be an insulator, so that all gates can be independently controlled. When a negative voltage is applied to split-gate, the underlying two dimensional electron gas is electrostatically squeezed into a one dimensional channel. Finger-gates on the top layer can be used to deplete electrons within the channel. Moreover, they can introduce QPCs in both ends of the channel to act as the entrance and exit barrier to a dot. Through the processing, we also learned that shallow etching can prevent the electric leakage between mesa and gates. In order to increase the carrier density and mobility of the samples, they were first illuminated with the far infrared light at low temperature upon the measurement. Magnetoresistance Rxx and Hall resistance RH have been measured to determine the carrier density and mobility of the two dimensional electron gas, and estimate the mean free path of electrons. The conductance measurements as a function of split-gate voltage demonstrate conductance plateaus at multiples of consistent with theoretical prediction for 1D channel. Applying a negative bias to one finger-gate atop the channel causes extra channel width confinement and dominate mainly the transport when its defined width is less than the original channel width. We also present the conductance measurements for a dot configurations with different coupling strengths between dot and its environment by controlling both finger-gates that affect the entrance and exit barriers.
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Chen, Yu, and 陳語. "Ramping Metrology Projecting Breakdown Characteristics of Nano-scaled High-k Gate Dielectric." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/7sbz7s.
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碩士國立臺北科技大學
機電整合研究所
100
CMOS devices have been scaling and improving in order to reduce cost, promote performance, and possess multi-function. Owing to the shrinking of MOSFETs, the thickness of gate dielectric has become much thinner. However, the serious problems of leakage current and reliability due to the thinning oxide also appear. Therefore, using high-k gate dielectrics to replace SiO2 is unavoidable. Among many high-k materials, Hf-based dielectrics are considered as the leading high-k candidates with metal electrode for next generation of CMOS technology. In recent years, the combination of nitrogen in Hafnium-based gate oxide has generally used due to the augment in thermal stability, diminish in equivalent oxide thickness (EOT), and important of the breakdown characteristics. In this work, the breakdown characteristics of HfO2 dielectrics with different temperature and nitrogen concentration are investigated. The PMOS experimental samples are fabricated from 28nm node high performance logic technology of UMC. In addition, the process of the dielectric layer was deposited by atomic layer deposition (ALD). The wafers were then annealed with different temperatures and nitrogen concentrations after ALD. The stress and measurement conditions in this research are performed at different ramp rates and temperatures. Then, ramp breakdown model is applied to fit with the measured data. Furthermore, the relations of breakdown characteristics under different processes, experiment temperatures, and ramp rates are also analyzed. Under VRDB stress, the breakdown voltages of the dielectrics decreased as temperatures and ramp rates increased, which is consistent with the projection of the ramp breakdown model. Specifically, the breakdown voltage in PDA process is slightly larger than that in DPN process from our measurement data. For the samples through DPN processes, the higher concentrations of nitrogen have higher breakdown voltages and higher process temperatures have lower breakdown voltages.
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Lin, Shi-Tin, and 林式庭. "Degradation and breakdown characteristics of thin gate oxide under nano-scaled stresses." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/21700578005619791054.
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博士國立暨南國際大學
電機工程學系
96
The main purpose of this thesis is to understand the degradation and breakdown characteristics of thin gate oxide under nano-scaled electrical stresses. Recently, a number of research results published in the literature indicate that the mechanism of oxide degradation and breakdown is an extremely localized phenomenon which has been confirmed to occur in the range of 10-14 ~10-12 cm2. Thus, conventional oxide reliability tests can only provide us average information under the gate area for oxide degradation and breakdown because the gate area of the MOS devices used for conventional tests is rarely less than 10-8 cm2. Since the contact area between the tip of conductive atomic force microscopy (C-AFM) and the sample surface is in the range of 10-12 ~ 10-10 cm2 which is close to the oxide breakdown area, the C-AFM becomes a powerful tool for investigating the degradation behaviors of a single degradation and breakdown spot of oxide. In order to extend the current measurement range as well as facilitating the capabilities of applying constant voltage stress (CVS) and constant current stress (CCS) to the oxide, the semiconductor analyzer (Agilent 4156 C) has been connected to the C–AFM system in this work. Repetitive ramped voltage stress (RVS) was applied to the oxide samples and we found two parallel oxide degradation mechanisms, bond-breaking and negative charge accumulation near the SiO2/Si interface as well as oxide thinning which results in an effective barrier height increase at the SiO2/Si interface, as determined from the measured current-voltage (I-V) characteristics and surface topographies. Breakdown does not actually occur until permanent damage is formed within the oxide during the after several times of repetitive RVS. The permanent damage produced inside the oxide film is in the form of traps, which will cause the bending as well as current oscillation in I-V curves. An energy band modulation model and a two-trap-assisted tunneling (TTAT) model were proposed to explain the post-breakdown I-V behaviors in this work. Both of the two models can explain the current oscillation occurred in the post-breakdown I – V curve, and the TTAT model can illustrate the bended I – V behavior. We also investigated the reliability of thin gate oxide subjected to irradiation followed by nano-scale stress. By taking advantage of a small contact area we report the nano-scale post-irradiation bias annealing effect in thin SiO2 film using C-AFM. Based on the number of fluctuating current peaks appearing in the I-V curves of the pre- and post-treatment oxide films as well as the calculated effective barrier height from the Fowler-Nordheim (F–N) tunneling theory, we found that the trapped charge in the oxide films caused by Co60γ-ray irradiation, can be effectively annealed out by a post-irradiation ramped voltage. Nano-scaled constant voltage stress (CVS) and constant current stress (CCS) were also applied to the gate oxide in this work. We found that the CVS-triggered breakdown I-V characteristics obtained by C-AFM were dependent on the current compliance during measurement. Two different post-breakdown conduction modes in thin SiO2 films, one follows the F–N tunneling and the other obeys the power law, were observed. Furthermore, the post-breakdown conduction follows F–N tunneling which is dominant when the current compliance is low, while power law is dominant if the current compliance is high. This result clarifies the previous controversy about the oxide post-breakdown conduction discussed in the literature. We also found that the post-breakdown conduction after nano-scaled CVS with a low current compliance is highly similar to the SILC conduction measured by conventional oxide breakdown tests. Base on our observation, the SILC conduction can be recognized as a light breakdown conduction behavior. In this work, we also investigated the Weibull plots of time-to-breakdown tBD and charge-to-breakdown QBD obtained under nano-scaled CVS and CCS. It is found that the Weibull slope obtained in this work is in consistent with those in the conventional stress tests, which states that the breakdown triggering mechanism under nano-scaled stress is the same as the one obtained in conventional oxide breakdown tests. As to QBD distribution under nano-scaled stress, an opposite trend to the results obtained in conventional tests was observed. We believe that QBD obtained under nano-scaled stress is more close to the actual QBD value of a single breakdown spot.
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Heng-YuChou and 周恆宇. "Investigation of nano-structured TaN metal gate thin films using reactive sputtering." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/95485425931436446257.
Full textAbstract:
碩士國立成功大學
材料科學及工程學系碩博士班
100
In this research, TaN is used as a metal gate due to its excellent conductivity, thermal stability, and tunable work function. A reactive magnetron sputtering system is used to deposit TaN thin films with various deposition parameters, such as the working pressures and deposition powers. The film thickness is measured by a profilometer. The sheet resistance is characterized by a four-point probe. The surface morphology and structures are characterized by scanning electron microscopy and X-ray diffraction, respectively. The electrical results are characterized by a probe station equipped with a LCR meter. The effects of different working pressures and working powers on sheet resistance, deposition rate, crystallinity, grain size, particle size and work functions are investigated in this research. We found the TaN thin films made at higher working power (〉 85W) and lower deposition pressures (〈 7 mTorr) are with reasonable good conductivity and nanocrystallinity. The work function of TaN made at 100W and 5 mTorr is 5.07 eV which is promising for P-MOS application.
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Lee, Chih-Peng, and 李志鵬. "The Weibull Distribution of Thin Gate Oxide Subjected to Nano-scaled Electrical Stress." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/43131426663187013412.
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碩士國立暨南國際大學
電機工程學系
95
In this thesis, we used conductive atomic force microscopy (C-AFM) in conjunction with semiconductor parameter analyzer (HP4156C) to study the degradation and breakdown behavior of thin gate oxide under nano-scaled stress with different oxide thickness at various stress conditions. Weibull distribution was used in this work to analyze the oxide breakdown events statistically. The C-AFM conductive tip acting as the metal gate electrode in a traditional metal oxide semiconductor (MOS) capacitor for electrical measurements was placed in contact with the bare oxide surface directly in this work. The contact area between the tip and the sample surface is small enough that the breakdown events we measured can be considered as the intrinsic degradation and breakdown behavior of the oxide. By using the semiconductor parameter analyzer we are able to apply either constant voltage stress (CVS) or constant current stress (CCS) to the samples as well as measure the current/voltage versus time characteristics during stress. From the experimental data, we can then analyze the data statistically and make the Weibull distribution plot. In this work, we compared the Weibull distribution obtained by using C-AFM connected with Agilent 4156C with those obtained by using the traditional MOS capacitors measurement. Charge-to-breakdown (QBD) of the oxides can be determined from the Weibull distribution. In general, the amount of QBD that an oxide can sustain depends on the gate area of the MOS capacitors for test. The increase of the gate area of MOS capacitor enhances the possibility of the weak points of the oxide being met during stress. This would make the oxide breakdown earlier and smaller QBD be obtained. Basically, the breakdown and degradation characteristics of thin oxide are a highly localized phenomenon, typically in a range of hundreds of nm2. However, the gate areas of conventional MOS capacitors used for breakdown test are rarely less than 10-7cm2. Therefore, breakdown test using conventional MOS capacitors only gives average oxide breakdown information under the gate area. In this thesis, the contact area between the conductive tip and the oxide surface is around 3x10-12cm2, which is extremely small so that it can be considered as a single breakdown point when oxide breakdown occurs. Therefore, the Weibull plot in this work depicts the behavior of intrinsic oxide degradation and breakdown. Basically, the shape parameter β in the Weibull distribution is dependent on the oxide thickness measured. For thin oxides, the β value decreases as the oxide thickness decreases. The β value indicates the scatter of the time-to-breakdown data, which has a linear relationship with the oxide thickness. When the oxide is thicker, the oxide breakdown probability becomes more concentrated due to the charge injected into the oxide during stress and formation of a leakage path in the oxide. In this thesis, we demonstrated, for the first time, the breakdown characteristics of 3 nm- and 5 nm-thick silicon dioxide by applying CVS and CCS through C-AFM in connection with Agilent 4156C. We successfully pushed the measuring limit of breakdown test area to around 10-12 cm2 and plotted the Weibull distribution of QBD and tBD. From the Weibull plot, we found that the 3 nm samples exhibited better QBD and tBD than the 5 nm samples. We also found that the values of the Weibull plots agreed well with those obtained in the conventional breakdown tests.
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Tsai, Chia-Chou, and 蔡佳州. "Study on Nano-Scaled Poly-Si Thin-Film Transistor with Stacked Gate Dielectric." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/14052982472738530877.
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碩士國立交通大學
電子工程系所
94
In this thesis, we have proposed and fabricated the SONOS-TFT with nanowire structure. The SONOS-TFTs can be used on the high performance driving device application and nonvolatile memory device application. For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability. In nonvolatile memory application, the SONOS-TFT with nanowire structure have superior program / erase efficiency for its higher electric field near the corner region. On the other hand, SONOS-TFT with nanowire structure have better reliability, either retention or endurance. The SONOS-TFTs combined the TFT and memory properties at the same time. Furthermore, the process flow is compatible with conventional poly-Si TFTs fabrication without additional process steps. Hence, the application of SONOS TFTs structure can reach the goal of system on panel (SOP) in the future.
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Wang, Yu-Chun, and 王育群. "Two Novel Capacitorless One-Transistor DRAMs with Multi-Gate and Nano-Pillar Structures." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62848552400920872265.
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碩士國立中山大學
電機工程學系研究所
103
In this thesis, we propose two novel capacitorless 1T-DRAMs, with the multi-gate and nano-pillar structures : The first type is a double-gate Nanowire TFT, with the fin-gate and pillar-body structure (FGPB). The second type is a vertical current bridge MOSFET, with the gate-all-around and nano-pillar structure (GAANP). We adopt the GIDL mechanism as 1T-DRAM programming method, and use the Sentaurus TCAD 12.0 simulation tool to confirm the memory performance. Compared with the conv. DG-NTFT, the FGPB device has nano-pillar structure, which can increase the pseudo neutral region without additional occupied area. This structure can improve the band-to-band tunneling, and keep the holes away from the P-N junction. The GIDL current is improved about 274.33 %. With fin-gate to control the excess hole efficiently, this structure can also overcome the SRH recombination influence indirectly. In terms of the low-power application, and the power consumption can maintained below 0.8 μW/μm. Compared with the lateral current bridge 1T-DRAMs, the GAANP SOI/Bulk-Silicon device has surrounding gate, which can enhance the excess hole control-ability; the vertical channel not only keeps the device in long-channel, but also maintains at a certain level of memory performance. In terms of the current bridge devices benchmark comparison, the GAANP SOI 1T-DRAM PW is improved at least about 238.54 %. The RT at 358 K is improved about 6.91 %. Two novel devices not only achieve low-power consumption, but also have sufficient operating endurance and disturbance immunity. We provide two excellent candidates for future 1T-DRAM applications.
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Lin, Chien-Ting, and 林建廷. "The Study of Advanced Strain Engineering andFUSI-gate for Nano Meter CMOSFET Technology Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/41588497245907279700.
Full textAbstract:
博士國立成功大學
微電子工程研究所碩博士班
96
In this dissertation, we study the impact of strain engineering and FUSI-gate technologies on nano meter scale MOSFETs performances in detail. The study is divided in five parts. First, we propose three types of the new strain engineering in FUSI-gate MOSFET. Three strain sources on FUSI are studied and analyzed, including enveloped FUSI phase transfer induced stress, the second-CESL induced stress, and the first CESL on poly-gate top removed by FUSI CMP. Second, we propose a simple CMOS FUSI process, which has the work function near to the N or PMOSFET band-edge, and is fully compatible with the conventional CMOSFET technology. Third, we extensively investigate the impact of CESL strain engineering on the PD-SOI (partially depleted silicon-on-insulator) devices with various TSI (SOI silicon thickness). We found the related device characteristics are supported by (IV) simulation data. Besides, the results are also important for the study of CESL strain engineering on FD-SOI (fully depleted SOI) and multi-gate MOFET design. Fourth, we study the interactions of STI stress with various mobility enhancement approaches systematically. The interaction between STI (shallow trench isolation) stress and CESL stress is significant, and results in a different LOD (length of diffusion) mobility trend for NMOSFET and PMOSFET, respectively. Finally, impacts of the notched-gate structure on contact etch stop layer (CESL) stressed 90nm NMOSFET were studied in detail. Based on both of simulation and measurement, a notched-gate structure with the high tensile-stress CESL enhances the driving capability, SCE, and DIBL of the device but without increasing the leakages obviously.