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Journal articles on the topic 'NAND Gate'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Jain, Shivkaran, and Arun Kr Chatterjee. "Nand gate architectures for memory decoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 2 (2013): 610–14. http://dx.doi.org/10.24297/ijct.v7i2.3464.

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This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more pow

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2

An, X., K. M. Geib, M. J. Hafich, et al. "Integrated optical NAND gate." Electronics Letters 28, no. 16 (1992): 1545. http://dx.doi.org/10.1049/el:19920981.

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3

Sim, Jae-Min, Bong-Seok Kim, In-Ho Nam, and Yun-Heub Song. "Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation." Electronics 10, no. 15 (2021): 1828. http://dx.doi.org/10.3390/electronics10151828.

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A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.

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4

Shan, Yu Qiong, Chang Ji Shan, Jun Luo, Xiao Pan Li, and Li Zhou. "Calculation of External Resistance of Two Gates' Circuits Connected with Different Loads." Advanced Materials Research 722 (July 2013): 18–22. http://dx.doi.org/10.4028/www.scientific.net/amr.722.18.

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The TTL nand gate cannot be directly connected with the output port of two gates to set a relationship with their output information while the integrated open-collector nand gate can do so by making a proper choice of between the integrated open-collector lines and the resistances.This paper aims to analyze the calculation of, Rp, the externally connected resistance of integrated gate circuit which is made up of open-collector gate, and open-drain gate when the and-not gate, and nor gate of the Loaded gates are discussed respectively.

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5

Siregar, Helmi Fauzi, and Ikhsan Parinduri. "PROTOYPE GERBANG LOGIKA ( AND, OR, NOT, NAND, NOR ) PADA LABORATORIUM ELEKTRONIKA STMIK ROYAL KISARAN." JURNAL TEKNOLOGI INFORMASI 1, no. 1 (2017): 37. http://dx.doi.org/10.36294/jurti.v1i1.41.

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Abstract - Logic gate prototype aims to meet the needs and smoothness of the teaching and learning process in one of the digital circuit lecture materials. Proof of the logic of OR, AND, NOT, NOR, and NAND gates. The working principle of logic gate prototype is working based on input logic including 0 and 1. For AND logic gates are input multiplication gates consisting of (0,0, 0,1, 1,0, 1,1) and output consists of 1 for high (1) and 3 for low (0). For OR gate is the input sum gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For the NAND gate is the lo

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6

Unutulmaz, Ahmet. "A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate." Gazi University Journal of Science Part A: Engineering and Innovation 12, no. 1 (2025): 61–71. https://doi.org/10.54287/gujsa.1645022.

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Threshold Logic Gate (TLG) has gained attention with the emergence of novel technologies such as memristors. TLG offers improved performance and lower power dissipation while occupying less silicon area. This paper introduces a novel dynamic clock generator circuit that further enhances TLG performance. The proposed circuit replaces the NAND gate-based approach used for clock generation in differential TLG implementations. It reduces the propagation delay of the TLG while reducing its static power dissipation, an important factor in energy-efficient circuit design. Simulations indicate up to a

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7

Li, Huang, and Li Feng Lin. "Design of a Digital Breathing Rate Tester Circuit." Applied Mechanics and Materials 556-562 (May 2014): 2161–64. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2161.

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Digital breathing rate tester uses amplifier circuit, filter circuit, shaping circuit, and frequency quadruplicator circuit to process respiration signals. The signals processed are mixed with signals from logic controller circuit, pass the NAND gate, combine with signals from NAND gate and enter the pulse counter circuit. Pulse counter circuit’s digital tube shows the breathing rates.

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8

N Md, Mohasinul Huq, Mohan Das S, and Bilal N Md. "Estimation of Leakage Power and Delay in CMOS Circuits." International Journal of Engineering Technology and Management Sciences 4, no. 7 (2020): 14–19. http://dx.doi.org/10.46647/ijetms.2020.v04i07.003.

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This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation

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9

Tanwar, Vanshika. "Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NAND Logic Gate using Open-Source Software eSim." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3972–77. http://dx.doi.org/10.22214/ijraset.2021.37128.

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A real world signals are mostly based on Boolean operators. In simple language Boolean operators are logic gates and logic gates are the building blocks of any circuit. There are different types of logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR. These all-logic gates are implemented using a Boolean function. And all these logic gates internally are implemented using diodes and transistors. And when we implement all these logic gates using transistor and diodes then it comes under logic families. In this paper we are going to do the analysis of NAND GATE using CMOS in 180 nm technology

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10

Xiong, Qin, Fei Wu, Zhonghai Lu, et al. "Characterizing 3D Floating Gate NAND Flash." ACM SIGMETRICS Performance Evaluation Review 44, no. 1 (2017): 31–32. http://dx.doi.org/10.1145/3143314.3078550.

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11

Xiong, Qin, Fei Wu, Zhonghai Lu, et al. "Characterizing 3D Floating Gate NAND Flash." ACM Transactions on Storage 14, no. 2 (2018): 1–31. http://dx.doi.org/10.1145/3162616.

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12

Wang, Xiyuan, Zhixiang Yin, Zhen Tang, Jing Yang, Jianzhong Cui, and Rujie Xu. "Visual Construction of Logical AND and NAND Gates." Journal of Chemistry 2022 (March 7, 2022): 1–10. http://dx.doi.org/10.1155/2022/1319762.

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DNA logic gates are an important branch of DNA computing and have a wide range of applications in DNA computing. In this study, logic circuits of AND gate and NAND gate are built on origami substrate. The realization of AND gate uses polymerase strand displacement (PSD) reaction and hybridization chain reaction (HCR). If there is a fluorescent band “1” displayed, the result is true. The realization of the NAND gate requires a cyclic reaction. If there is a fluorescent band “A” or “T” displayed, the result is true; if no fluorescent band is displayed, the result is false.

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13

Yu, Ji-Man, Chungryeol Lee, Joon-Kyu Han, et al. "Multi-functional logic circuits composed of ultra-thin electrolyte-gated transistors with wafer-scale integration." Journal of Materials Chemistry C 9, no. 22 (2021): 7222–27. http://dx.doi.org/10.1039/d1tc01486b.

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Wafer-scale integration of electrolyte gated transistors is demonstrated by using iCVD. A solid-state pEGDMA was used as a gate electrolyte, and it configures multi-functional logic circuits, such as inverter, NAND, and NOR with high performance.

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14

Chvála, Aleš, Lukáš Nagy, Juraj Marek, et al. "Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs." Journal of Circuits, Systems and Computers 28, supp01 (2019): 1940009. http://dx.doi.org/10.1142/s0218126619400097.

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This paper presents monolithic integrated InAlN/GaN NAND and NOR logic cells comprising depletion-mode, enhancement-mode and dual-gate enhancement-mode high electron mobility transistors (HEMTs). The designed NAND and NOR logic cells consist of the depletion-mode and enhancement-mode HEMT transistors integrated onto a single die. InAlN/GaN-based NAND and NOR logic cells with good static and dynamic performance are demonstrated for the first time. Calibrated static and dynamic electrophysical models are proposed for 2D device simulations in Sentaurus Device environment. Sentaurus Device mixed-m

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15

Shakir, Muhammad, Hossein Elahipanah, Raheleh Hedayati та Carl Mikael Zetterling. "Electrical Characterization of Integrated 2-Input TTL NAND Gate at Elevated Temperature, Fabricated in Bipolar SiС-Technology". Materials Science Forum 924 (червень 2018): 958–61. http://dx.doi.org/10.4028/www.scientific.net/msf.924.958.

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This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage.The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperature

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16

Anusuya, K., and Dr S. Kavitha. "Implementation of Full Adder Using Nand Gates." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (2023): 3887–90. http://dx.doi.org/10.22214/ijraset.2023.51133.

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: In digital electronics, there are different types of logic circuits used to perform different kinds ofarithmetic operations. One of them is adder. Adder (or Binary Adder) is a combinational logic circuit that performs the addition of two or more binary numbers and gives an output sum. There are two types of adders present namely, half adder and fulladder. Since, adder are logic circuits, thus they are implemented using different types of digital logic gates such as OR gate, AND gate, NOT gate, NAND gates, NOR gates, etc. In this article, we will discuss the Full Adder Realization using NAND

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17

Yang, Tao, Bao Zhang, Qi Wang, Lei Jin, and Zhiliang Xia. "Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash." Micromachines 14, no. 3 (2023): 686. http://dx.doi.org/10.3390/mi14030686.

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), c

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18

., Vibha Soni. "COMPARISON OF LOGIC FAMILIES USING NAND GATE." International Journal of Research in Engineering and Technology 02, no. 09 (2013): 573–76. http://dx.doi.org/10.15623/ijret.2013.0209088.

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19

Goñi-Moreno, Angel, and Martyn Amos. "A reconfigurable NAND/NOR genetic logic gate." BMC Systems Biology 6, no. 1 (2012): 126. http://dx.doi.org/10.1186/1752-0509-6-126.

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20

Bae, Hee Young, Seul Ki Hong, and Jong Kyung Park. "Systematic Analysis of Spacer and Gate Length Scaling on Memory Characteristics in 3D NAND Flash Memory." Applied Sciences 14, no. 15 (2024): 6689. http://dx.doi.org/10.3390/app14156689.

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This study investigates the impact of oxide/nitride (ON) pitch scaling on the memory performance of 3D NAND flash memory. We aim to enhance 3D NAND flash memory by systematically reducing the spacer length (Ls) and gate length (Lg) to achieve improved memory characteristics. Using TCAD simulations, we evaluate the effects of Ls and Lg scaling on the program speed, erase speed, and Z-interference. Furthermore, we examine the influence of concave and convex channel structures in the context of Ls and Lg scaling. By analyzing the distributions of electron and hole-trapped charges, we provide insi

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21

Dehghan, E., D. Sanavi Khoshnoud, and A. S. Naeimi. "NAND/AND/NOT logic gates response in series of mesoscopic quantum rings." Modern Physics Letters B 33, no. 34 (2019): 1950431. http://dx.doi.org/10.1142/s0217984919504311.

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There is a special class of logic gates, called universal gates, any one of which is sufficient to express any desired computation. The NAND gate is truly global, given that it is already known, each Boolean function can be represented in a circuit that contains only NOT and AND gates, it is sufficient to show that these gates can be defined from the NAND gate. The effect of Rashba spin-orbit interaction (SOI) on the gate response and spin current density in a series of non-interacting one-dimensional rings connected to some leads is studied theoretically within the waveguide theory. The gates

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22

Kotb, Amer, Antonios Hatziefremidis, Gamal Said, and Kyriakos E. Zoiros. "High-Speed and Cost-Efficient NAND Logic Gate Using a Single SOA-DI Configuration." Photonics 11, no. 12 (2024): 1182. https://doi.org/10.3390/photonics11121182.

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In this study, we propose a novel design for a NAND gate using a single semiconductor optical amplifier (SOA) followed by a delay interferometer (DI). This streamlined configuration significantly reduces complexity and cost compared to conventional methods, which typically require cascading multiple SOA-Mach–Zehnder interferometers (SOA-MZIs) for NAND gate implementation. Our approach directly generates the NAND logic output with a single SOA and DI, simplifying the overall design. The gate’s performance is evaluated at 80 Gb/s, achieving a high-quality factor (QF) of 10.75. We also analyze th

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23

Sharma, Manoj, and Arti Noor. "Reconfigurable CPL Adiabatic Gated Logic RCPLAG based Universal NAND/NOR Gate." International Journal of Computer Applications 95, no. 26 (2014): 27–32. http://dx.doi.org/10.5120/16961-7078.

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24

Lin, Kai-Cheng, Chia-Yin Kuo, Chih-Chun Nieh, and Wei-Lung Tseng. "Molecular beacon-based NAND logic gate for sensing triplex DNA binders." RSC Adv. 4, no. 72 (2014): 38389–92. http://dx.doi.org/10.1039/c4ra06158f.

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25

Al-Sabea, Z. S., A. A. Ibrahim, and S. H. Abdulnabi. "Plasmonic Logic Gates at Optimum Optical Communications Wavelength." Advanced Electromagnetics 11, no. 4 (2022): 10–21. http://dx.doi.org/10.7716/aem.v11i4.1894.

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This paper displays a design that realizes all optical logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and consisting of one nanoring and four strips Operates on the principle of resonance. the proposed design works at the wavelength of 1550 nm using insulator-metal-insulator (IMI) plasmonic waveguide. The basic principle of the operation of these gates is input and control signals’ constructive and destructive interference. The proposed transmission threshold’s value is 0.25 between OFF state and ON state. The proposed design has small dimensions (300 nm × 300 nm) and can realize seven logic

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26

Gerardin, Simone, Marta Bagatin, Alberto Ferrario, et al. "Neutron-Induced Upsets in NAND Floating Gate Memories." IEEE Transactions on Device and Materials Reliability 12, no. 2 (2012): 437–44. http://dx.doi.org/10.1109/tdmr.2012.2192440.

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27

Tang, Zhen, Zhi-Xiang Yin, Xia Sun, Jian-Zhong Cui, Jing Yang, and Ri-sheng Wang. "Dynamically NAND gate system on DNA origami template." Computers in Biology and Medicine 109 (June 2019): 112–20. http://dx.doi.org/10.1016/j.compbiomed.2019.04.026.

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28

Jayalakshmi, R., M. Senthil Kumaran, and R. Amutha. "A Step Towards Optimisation of 2 to 4 Decoder Using Farooq-Nikesh-Zaid Gate with Coplanar Crossing in Quantum Dot Cellular Automata." Journal of Computational and Theoretical Nanoscience 17, no. 5 (2020): 2120–24. http://dx.doi.org/10.1166/jctn.2020.8857.

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The limitations of the existing Complementary Metal Oxide Semiconductor are leading the momentum to various new approaches like Quantum-dot Cellular Automata (QCA). QCA offers low power dissipation, less area and high switching speeds. The Majority Voter is the basic structure that votes out on the majority of the inputs to implement a Boolean Function. The QCA architectures are created by using majority gates with inverters or by using universal gates like AND–OR-Inverter and NAND–NOR-Inverter gate. This paper proposes a quantum-dot cellular automata 2 to 4 decoder using Universal Farooq-Nike

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29

Yang, Liu, Yuqi Wang, Zhiru Wu, and Xiaoyuan Wang. "FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design." Micromachines 12, no. 11 (2021): 1344. http://dx.doi.org/10.3390/mi12111344.

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In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has distinct advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

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30

Yu, Xinyue, Zhongyuan Ma, Zixiao Shen, et al. "3D NAND Flash Memory Based on Double-Layer NC-Si Floating Gate with High Density of Multilevel Storage." Nanomaterials 12, no. 14 (2022): 2459. http://dx.doi.org/10.3390/nano12142459.

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As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the computing in a memory chip, a new candidate with high density and a large on/off current ratio is now urgently needed. Here, we first report that 3D NAND flash memory with a high density of multilevel storage can be realized in a double-layered Si quantum dot floating-gate MOS structure. The largest capacitance–voltage (C-V) memory window of 6

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31

de Almeida, Léo César, Fabio B. de Sousa, Waldomiro Paschoal Jr., and Marcos Costa. "2D FDTD Electromagnetic Simulation of an Ultracompact All Optical Logic Gate Based on 2D Photonic Crystal for Ultrafast Applications." Journal of Communication and Information Systems 39, no. 2024 (2024): 35–45. http://dx.doi.org/10.14209/jcis.2024.4.

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In this paper, the concept of photonic crystals (PhCs) is fundamental to designing and simulating an all-optical logic gate device. We proposed an all-optical switch composed of two-dimensional (2D) photonic crystal waveguides with a central photonic crystal ring resonator (PCRR). The new all-optical NAND logic gate device comprises two linear waveguides coupled to each other through a single compact PCRR. The plane wave expansion (PWE) and finite-difference time-domain (FDTD) methods are applied to simulate the properties of the system. The structure is implemented on the operational waveleng

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32

Seo, Moon-Sik, and Tetsuo Endoh. "Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate." Japanese Journal of Applied Physics 51, no. 2S (2012): 02BD04. http://dx.doi.org/10.7567/jjap.51.02bd04.

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Seo, Moon-Sik, and Tetsuo Endoh. "Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate." Japanese Journal of Applied Physics 51, no. 2 (2012): 02BD04. http://dx.doi.org/10.1143/jjap.51.02bd04.

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34

Kumar, Manoj. "VCO Design using NAND Gate for Low Power Application." JSTS:Journal of Semiconductor Technology and Science 16, no. 5 (2016): 650–56. http://dx.doi.org/10.5573/jsts.2016.16.5.650.

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35

Samiappan, Manickasundaram, Zehavit Dadon, and Gonen Ashkenasy. "Replication NAND gate with light as input and output." Chem. Commun. 47, no. 2 (2011): 710–12. http://dx.doi.org/10.1039/c0cc04098c.

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36

Omprakash, S. S., and S. K. Naveen Kumar. "PANI/ZnO Hybrid Nanocomposites TFT for NAND Gate Application." Materials Today: Proceedings 5, no. 4 (2018): 10827–32. http://dx.doi.org/10.1016/j.matpr.2017.12.369.

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37

Rahmanian Koushkaki, Hassan, and Majid Akhlaghi. "Investigating the optical nand gate using plasmonic nano-spheres." Optical and Quantum Electronics 47, no. 11 (2015): 3637–45. http://dx.doi.org/10.1007/s11082-015-0236-9.

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Lisoni, Judit G., Laurent Breuil, Pieter Blomme, et al. "Material selection for hybrid floating gate NAND memory applications." physica status solidi (a) 213, no. 2 (2016): 237–44. http://dx.doi.org/10.1002/pssa.201532829.

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39

Hu, Hongsheng, Zhongyuan Ma, Xinyue Yu, et al. "Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer." Nanomaterials 13, no. 6 (2023): 962. http://dx.doi.org/10.3390/nano13060962.

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Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture. Here, we first report the carrier injection efficiency of 3D NAND flash memory based on a nanocrystalline silicon floating gate, which can be controlled by a novel design of the control layer. The carrier injection efficiency in nanocrystalline Si can be monitored by the capacitance–voltage (C–V) hysteresis direction of an nc-Si floating-gate MOS structure. When the cont

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40

Takahashi, Yasuo, Shinichiro Ueno, and Masashi Arita. "Multifunctional Logic Gate by Means of Nanodot Array with Different Arrangements." Journal of Nanomaterials 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/702094.

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Multifunctional logic gate devices consisting of a nanodot array are studied from the viewpoint of single electronics. In a nanodot array, the dots come in a random variety of sizes, which sometimes has a negative effect on the performance of electrical device applications. Here, this feature is used in a positive sense to achieve higher functionality in the form of flexible logic gates with low power consumption in which the variability of logic functions is guaranteed. Nanodot arrays with two input gates and one control gate in a variety of arrangements are considered, in which the two-input

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41

R., Krishna, and Duraiswamy Punithavathi. "Low leakage decoder using dual-threshold technique for static random-access memory applications." Low leakage decoder using dual-threshold technique for static random-access memory applications 30, no. 3 (2023): 1420–27. https://doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.

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Decoders are one of the significant peripheral components of static randomaccess memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate bias

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Parinduri, Ikhsan, and Siti Nurhabibah Hutagalung. "PERANGKAIAN GERBANG LOGIKA DENGAN MENGGUNAKAN MATLAB (SIMULINK)." JURTEKSI (Jurnal Teknologi dan Sistem Informasi) 5, no. 1 (2019): 63–70. http://dx.doi.org/10.33330/jurteksi.v5i1.300.

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Abstrack: The logic gate circuit using the simulink method matlab is a series of ways to prove between theories in simulation using the matlab program by entering parameters in the truth table at each logic gate. Parameters in the truth table consist of logic 0 for low and logic 1 for high. The simulation is done by giving input (input) and outpout (output) at each basic logic gate which consists of 7 gates of which are NOT gates, AND, OR, NAND, NOR, X-OR and X-NOR. This proof is intended as a medium to study the logic gate in higher learning learning in digital engineering learning and digita

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Krishna, R., and Punithavathi Duraiswamy. "Low leakage decoder using dual-threshold technique for static random-access memory applications." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 3 (2023): 1420. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.

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Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate bia

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44

Hwang, Hwiho, Gyeonghae Kim, Dayeon Yu, and Hyungjin Kim. "Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash." Biomimetics 10, no. 5 (2025): 318. https://doi.org/10.3390/biomimetics10050318.

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In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al2O3/Si3N4/SiO2/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were c

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Refaldi, David G., Gerardo Malavena, Luca Chiavarone, Alessandro S. Spinelli, and Christian Monzio Compagnoni. "Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories." Micromachines 15, no. 12 (2024): 1516. https://doi.org/10.3390/mi15121516.

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Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potent

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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian, and Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit." Applied Mechanics and Materials 644-650 (September 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.

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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.

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TERASHIMA, HIROAKI, and MASAHITO UEDA. "NONUNITARY QUANTUM CIRCUIT." International Journal of Quantum Information 03, no. 04 (2005): 633–47. http://dx.doi.org/10.1142/s0219749905001456.

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A quantum circuit is generalized to a nonunitary one whose constituents are nonunitary gates operated by quantum measurement. It is shown that a specific type of one-qubit nonunitary gates, the controlled-NOT gate, and all one-qubit unitary gates constitute a universal set of gates for the nonunitary quantum circuit, without the necessity of introducing ancilla qubits. A reversing measurement scheme is used to improve the probability of successful nonunitary gate operation. A quantum NAND gate and Abrams–Lloyd's nonlinear gate are analyzed as examples. Our nonunitary circuit can be used to red

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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physic

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Anusooya, V., S. Ponmalar, and M. S. K. Manikandan. "Photonic-crystal-based design and FDTD simulation of all-optical NAND and NOR gates with improved contrast ratio." Laser Physics 32, no. 1 (2021): 016202. http://dx.doi.org/10.1088/1555-6611/ac3514.

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Abstract The proposed research reports the simulation of a photonic crystal (PhC) ring-resonator-based full-optical NAND and NOR gate design. The designed structure comprises a 18 × 30 square lattice dielectric silicon rod-type PhC with a refractive index of n = 3.46. An interatomic distance ‘a’ of 560 nm, radius ‘r’ of 0.21a (0.133 μm) and input wavelength λ = 1550 nm with an input signal amplitude of 1 volt are used in this design. The proposed structure provides two large band gaps in Transverse Electric polarized mode in the ranges of 1342–1980 nm and 758–779 nm. Similar parameters are use

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KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal

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