Academic literature on the topic 'Nano-scale transistor'
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Journal articles on the topic "Nano-scale transistor"
Wulf, Ulrich, and Hans Richter. "Scale-Invariant Drain Current in Nano-FETs." Journal of Nano Research 10 (April 2010): 49–61. http://dx.doi.org/10.4028/www.scientific.net/jnanor.10.49.
Full textWu, Jerry, Yin-Lin Shen, Kitt Reinhardt, Harold Szu, and Boqun Dong. "A Nanotechnology Enhancement to Moore's Law." Applied Computational Intelligence and Soft Computing 2013 (2013): 1–13. http://dx.doi.org/10.1155/2013/426962.
Full textDadoria, Ajay Kumar, Kavita Khare, Traun K. Gupta, and R. P. Singh. "A Survey on Nano-Scale Double Gate CMOS Transistor." Advanced Science Letters 21, no. 9 (September 1, 2015): 2830–32. http://dx.doi.org/10.1166/asl.2015.6365.
Full textMukhopadhyay, Joyjit, and Soumya Pandit. "Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics." VLSI Design 2012 (April 22, 2012): 1–13. http://dx.doi.org/10.1155/2012/505983.
Full textTripathi, Suman Lata. "Pocket Vertical Junction-Less U-Shape Tunnel FET and Its Challenges in Nano-Scale Regime." Advanced Science, Engineering and Medicine 11, no. 12 (December 1, 2019): 1225–30. http://dx.doi.org/10.1166/asem.2019.2466.
Full textWalker, James Alfred, Richard Sinnott, Gordon Stewart, James A. Hilder, and Andy M. Tyrrell. "Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 368, no. 1925 (August 28, 2010): 3967–81. http://dx.doi.org/10.1098/rsta.2010.0150.
Full textMehrad, Mahsa, and Meysam Zareiee. "Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET." ECS Journal of Solid State Science and Technology 5, no. 7 (2016): M74—M77. http://dx.doi.org/10.1149/2.0231607jss.
Full textYu, Chang Hong. "Accurate SER Estimation by Transform Matrix Analysis for Fault Tolerant Circuits Design." Advanced Materials Research 121-122 (June 2010): 87–92. http://dx.doi.org/10.4028/www.scientific.net/amr.121-122.87.
Full textRjoub, Abdoul, Almotasem Bellah Alajlouni, and Hassan Almanasrah. "Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits." Circuits and Systems 04, no. 02 (2013): 123–36. http://dx.doi.org/10.4236/cs.2013.42018.
Full textRANA, ASHWANI K., NAROTTAM CHAND, and VINOD KAPOOR. "MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER." Journal of Circuits, Systems and Computers 20, no. 08 (December 2011): 1659–75. http://dx.doi.org/10.1142/s0218126611008006.
Full textDissertations / Theses on the topic "Nano-scale transistor"
Ravichandran, Karthik. "Nano-scale process and device simulation." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1125340288.
Full textMoezi, Negin. "Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability." Thesis, University of Glasgow, 2012. http://theses.gla.ac.uk/3447/.
Full textBaniahmad, Ata. "QUANTUM MECHANICAL Study and Modelling of MOLECULAR ELECTRONIC DEVICES." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13193/.
Full textLin, Wun Jey, and 林文傑. "A Study on CoSi2 Schottky Barrier Poly-Si Thin-Film Transistor with Nano-Scale Channel Width." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94240015926995473530.
Full text國立交通大學
電資學院學程碩士班
91
In this thesis, we proposed and demonstrated a novel poly-Si TFT device with nano-scale fin-like channel featuring silicide source/drain and electrical junction induced by a sub-gate configuration lying over the passivation dielectric. The fin-like channel, which is consisted of as-deposited LPCVD poly-Si material, is surrounded on three sides by the main-gate, forming the “tri-gate” configuration. The drain-to-source leakage current can thus be effectively suppressed. Moreover, the controllability of short-channel effects is also significantly improved. The fabricated devices show excellent ambipolar subthreshold characteristics with steep subthreshold slope and high on/off current ratio. It is also shown that the application of sub-gate bias can not only increase the on-current, but also reduce the off-state leakage. Differences in device characteristics between poly-Si FinFETs fabricated in this study and the SOI FinFETs previously reported by a senior classmate (F. J. Hou) are also discussed in this thesis.
Chiang, Yih-Ray, and 蔣宇睿. "Preliminary Dynamic Analysis of Nano-scale Silicon-based Transistors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/68157177288000808056.
Full text國立成功大學
機械工程學系碩博士班
96
The goal of this thesis is aimed at the investigation upon the kinematic characteristics of the charge carriers within the silicon-based transistor under nano-scale effects, via classical transport model to include a quantum correction term so that the difference between quantum transport model and classical transport model can be unveiled. Based on the computer simulation of the commercial software nanoMOS, the impacts on nanowire field effect transistors due to various design of crystal structure and choice of doped material composition are analyzed. Conductance performance such as the sub-threshold swing and the threshold voltage are studied. Furthermore, this thesis utilizes software package VASP (Vienna ab initio Simulation Package) to simulate the behavior of the silicon-based nanowires by varying nanowires geometric cross-section and replacement of the silicon atoms in crystal by other elements, such that the induced distribution of the electron density of state of the nanowires owing to change of the crystal structure can be obtained. The simulation results provide essential basis for nanowires field effect transistor in structural design and potential choice of the device material for future developments. Finally, this thesis proposes a simple and easily realizable fabrication technique, sidewall spacer formation, for implementation of silicon nanowires.
Shao, Chi Shen, and 邵繼聖. "Study of Novel Nano-Scale Multi-Gate Junctionless Field Effect Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4acdu6.
Full text國立交通大學
電子工程學系 電子研究所
103
In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and less sensitivity of the fin angle to electrical performances by reducing effective channel thickness that is caused by the channel/ substrate junction. Hence, the JL bulk FinFET is highly recommended in sub-10-nm nodes. Additionally, this work demonstrates for the first time the fabrication of a proposed hybrid P/N poly-Si channel junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structure. The novel hybrid P/N JL-TFTs showed excellent electrical performances in terms of a steep subthreshold swing of 64mV/dec, a high Ion/Ioff current ratio (>107), a low drain-induced barrier lowering value of 3 mV/V, small series resistance and temperature stability were investigated, indicating greater gate electrostatic controllability and less current crowding than in conventional JL-TFTs. Furthermore, simulated results and a quantum model physical model were discussed initially but not detailed enough for future work support experimental data. Hence, the proposed hybrid P/N JL-TFT is highly promising for future further sub-10-nm scaling and 3D stacked ICs applications.
Lee, Hai-Ming, and 李海明. "Functional Reliability Study of MOS Transistors with Nano-Scale Gate Oxides." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/00212883958107943667.
Full text國立清華大學
電子工程研究所
91
In this study, functional reliability of MOS transistors with oxide thickness ranging from 3.3 nm down to 1.2 nm is investigated in detail. In contrast with most reliability tests which focus on oxide reliability, various mechanisms resulting in transistor performance degradation are examined, while the on-state drain conduction current and off-state drain leakage current are the two most decisive device parameters that dominates MOS transistor functional reliability in the ultra-thin oxide regime. The degradation of off-state drain leakage current is caused by lately observed oxide soft-breakdown within the gate-to-drain overlap area, and its dominance tends to grow with scaling oxide thickness. Through experimental data analyses and theoretical calculations, we verified the dependences of device lifetime on oxide electric field, failure rate and device dimension. On the basis of physical mechanisms and models, we propose a methodology for MOS transistor functional reliability evaluation and a correlated unified functional reliability model which may contribute to the microelectronics technology development in the near future.
Cheng, Ya Chi, and 埕雅琪. "Study of Novel Nano-Scale Junctionless Fin Field-Effect Transistors for 3D-IC Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/kwr6b2.
Full text國立清華大學
工程與系統科學系
104
In this work, we comprehensively study the device fabrication, electrical characteristic, and reliability of the various novel nano-scale Junctionless fin field-effect transistors for three-dimensional (3D) stacked IC application. In the first part of this work, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our JL device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low Ioff and steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications. We also measure the breakdown voltage of such device and compare it to IM TFT. Our JL TFT obtains higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application. The junctionless transistor is proposed to be a future device because of the simple fabrication and suffered the suppression of On-current owing to the thin channel structure. In the second part of this work, the raised source and drain (RSD) structure is combined with the juncitonless transistor for the improvement of On-current. In the basic electrical measurement, the On-current of the RSD device almost reaches 1A that is ten times for that of the non-RSD devices. The RSD juncitonless device gets the steep sub-threshold swing (SS=100mV/dec.) and the Off-current is low (10-14A) due to the remained thin channel structure. For reliability experiment, the temperature and the stress tests are taken for the RSD junctionless device. When the RSD junctionless device is heated up, the positive shifting of threshold voltage, degradation of SS and increase of the On-current as well as Off-current could be observed. The stress operation makes the electrical characteristics of the RSD junctionless device changes due to the trapped carriers injected by gate at the edges of the gate insulator. The special structure of the N-type RSD junctionless device called the dual gate is discussed. The two gates at the same layer would make the threshold voltage become tunable flexibly. For the N-type RSD junctionless device, when the bias-gate voltage is negative, the Vth would shift toward the right side. When the bias gate voltage is positive, the Vth would shift toward the left side. It should be noticed that the shifts of Vth is linear regression with the bias gate voltage as well as the change of the On-current fits the quadratic regression. In the last part of this work, the new structure of the junctionless device is brought up called Hybrid P/N channel. The idea of the Hybrid P/N channel is intrigued by the bulk device. The different type layers are stacked as the channel to enhance the simplicity of the fabrication for the thin channel. The performance of the Hybrid P/N is good with the low SS (64mV/dec.). The simulation is added for proving the existence of the depletion region. Using different doping concentration in Hybrid P/N channel devices can adjust Vth. In further, using back-gate achieves device multi-Vth adjustment without adding process budget and device performance optimization for increased Ion simultaneously decreased Ioff via negative back-gate bias, which becomes the key technology in low-power circuit and power management applications. We also success demonstrates a 3D stacked hybrid P/N layer in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law, which provide valuable information regarding their practical industrial and academic applications. The 3D stacked hybrid P/N layer can increase on-state current and maintain low leakage current, small SS and great DIBL characteristics of short channel effect.
Wu, Yung-Chun, and 吳永俊. "Fabrication and Characterization of Novel Structure with Nano-Scale Low-Temperature High-Performance Polysilicon Thin-film Transistors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/uu26ku.
Full text國立交通大學
電子工程系所
94
In first part, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure. Additionally, NH3-plasma passivation more efficiently affects M10 TFT than it does other TFTs. The M10 TFT has a split nano-wire structure, most of which is exposed to NH3 plasma passivation, further reducing the number of grain boundary defects. On the other hand, the ac and dc reliability of ten-nanowire poly-Si TFTs are investigated. In static and dynamic hot-carrier stress experiments, the ten-nanowire poly-Si TFTs reduces the degradation of Vth, SS, Ion, On/OFF ratio and DIBL, for all kind of frequency, rising time, falling time and temperature, compared to single-channel TFT. These high reliability results of multiple nanowire poly-Si TFTs can be also explained by its robust tri-gate control and its superior channel NH3 passivation on the poly-Si grain boundary. Devices that contain the proposed M10 TFT are highly promising for use in active-matrix liquid-crystal-display and 3-D CMOS technologies without any additional processing. In second part, the effects of channel width and NH3 plasma passivation on the electrical characteristics of a series of a novel 4-mask pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs) were studied. The mobility and device performance of PDMILC TFTs improves as the each channel width decreasing. Furthermore, PDMILC TFTs with NH3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nano-scale TFT with ten 67 nm-wide split channels (M10) are superior to those of other TFTs. The former include a higher field effect mobility of 84.63 cm2/Vs, a higher ON/OFF current ratio (>106), a steeper subthreshold slope (SS) of 230 mV/decade, an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit most poly-Si grain enhanced to reduce the grain boundary defects and best NH3 plasma passivation due to its split nanowire structure. Both effects can reduce the number of defects at grain boundaries of poly-Si in active region for high performances. In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.
Book chapters on the topic "Nano-scale transistor"
Sengupta, Sarmista, and Soumya Pandit. "Statistical Characterization of Flicker Noise Fluctuation of a Nano-Scale NMOS Transistor." In Springer Proceedings in Physics, 203–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-34216-5_21.
Full textPratap, Surender, and Niladri Sarkar. "Transport Properties and Sub-band Modulation of the SWCNT Based Nano-scale Transistors." In Springer Proceedings in Physics, 155–62. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_24.
Full text"Modeling of Scaled MOS Transistor for VLSI Circuit Simulation." In Nano-scale CMOS Analog Circuits, 85–156. CRC Press, 2014. http://dx.doi.org/10.1201/b16447-4.
Full textPandit, Soumya, Chittaranjan Mandal, and Amit Patra. "Modeling of Scaled MOS Transistor for VLSI Circuit Simulation." In Nano-Scale CMOS Analog Circuits, 85–156. CRC Press, 2018. http://dx.doi.org/10.1201/9781315216102-3.
Full text"Advanced Effects of Scaled MOS Transistors." In Nano-scale CMOS Analog Circuits, 253–303. CRC Press, 2014. http://dx.doi.org/10.1201/b16447-7.
Full textPandit, Soumya, Chittaranjan Mandal, and Amit Patra. "Advanced Effects of Scaled MOS Transistors." In Nano-Scale CMOS Analog Circuits, 253–304. CRC Press, 2018. http://dx.doi.org/10.1201/9781315216102-6.
Full textChakraborty, Debapriya, Jeetendra Singh, and Shashi Bala. "Brace of Nanowire FETs in the Advancements and Miniaturizations of Recent Integrated Circuits Design." In Advances in Computer and Electrical Engineering, 139–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch007.
Full textConference papers on the topic "Nano-scale transistor"
Tsutsui, K., M. Morita, M. Tokuda, H. Takagi, Y. Ito, and Y. Wada. "Three Terminal Nano-Scale Electrode for Molecular Transistor Evaluation." In 2011 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2011. http://dx.doi.org/10.7567/ssdm.2011.b-1-7l.
Full textKoyanagi, M., Y. Yamada, M. Park, T. Fukushima, and T. Tanaka. "Research and development of transistor structure in nano-scale region." In 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570974.
Full textRjoub, Abdoul, Hassan Almanasrah, and Shihab Ahmed Kattab. "An efficient DELOTS Algorithm for low leakage current at nano-scale transistor." In 2011 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT). IEEE, 2011. http://dx.doi.org/10.1109/aeect.2011.6132517.
Full textSharma, Baldeo Sharan, and M. S. Bhat. "A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry." In 2017 International Conference on Innovations in Electronics, Signal Processing and Communication (IESC). IEEE, 2017. http://dx.doi.org/10.1109/iespc.2017.8071854.
Full textFrank He, Haijun Lou, Wang Zhou, Lin Chen, Yiwen Xu, Hao Zhuang, and Xinnan Lin. "Numerical simulation on novel nano-scale lateral double-gate tunneling field effect transistor." In 2010 IEEE 3rd International Nanoelectronics Conference (INEC). IEEE, 2010. http://dx.doi.org/10.1109/inec.2010.5424618.
Full textMenchaca, Roberto, and Hamid Mahmoodi. "Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS." In 2012 13th International Symposium on Quality Electronic Design (ISQED). IEEE, 2012. http://dx.doi.org/10.1109/isqed.2012.6187515.
Full textRjoub, Abdoul, and Almotasem Bellah Alajlouni. "Graph modeling for Static Timing Analysis at transistor level in nano-scale CMOS circuits." In MELECON 2012 - 2012 16th IEEE Mediterranean Electrotechnical Conference. IEEE, 2012. http://dx.doi.org/10.1109/melcon.2012.6196385.
Full textSharma, Baldeo Sharan, and M. S. Bhat. "Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry." In 2017 IEEE 8th Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON). IEEE, 2017. http://dx.doi.org/10.1109/uemcon.2017.8249045.
Full textJie Peng, Quan Chen, Ngai Wong, LingYi Meng, ChiYung Yam, and GuanHua Chen. "A multi-scale framework for nano-electronic devices modeling with application to the junctionless transistor." In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2013. http://dx.doi.org/10.1109/edssc.2013.6628145.
Full textSengupta, Sarmista, and Soumya Pandit. "Semi-analytical estimation of intra-die variations of analog performances of nano-scale nMOS transistor." In 16th International Workshop on Physics of Semiconductor Devices, edited by Monica Katiyar, B. Mazhari, and Y. N. Mohapatra. SPIE, 2012. http://dx.doi.org/10.1117/12.925339.
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