Journal articles: 'Nano-scale transistor'

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Wulf, Ulrich, and Hans Richter. "Scale-Invariant Drain Current in Nano-FETs." Journal of Nano Research 10 (April 2010): 49–61. http://dx.doi.org/10.4028/www.scientific.net/jnanor.10.49.

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Starting from a three-dimensional transport model in the Landauer-Buttiker formalism we derive a scale-invariant expression for the drain current in a nano-transistor. Apart from dimensionless external parameters representing temperature, gate-, and drain voltage the normalized drain current depends on two dimensionless transistor parameters which are the characteristic length l and -width w of the electron channel. The latter quantities are the physical length and -width of the channel in units of the scaling length = ~(2mF )1=2. Here F is the Fermi energy in the source contact and m is the eective mass in the electron channel. In the limit of wide transistors and low temperatures we evaluate the scale-invariant IDVD characteristics as a function of the characteristic length. In the strong barrier regime, i. e. for l & 20 long-channel behavior is found. At weaker barriers source-drain tunneling leads to increasingly signicant deviations from the long-channel behavior. We compare with experimental results.

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Wu, Jerry, Yin-Lin Shen, Kitt Reinhardt, Harold Szu, and Boqun Dong. "A Nanotechnology Enhancement to Moore's Law." Applied Computational Intelligence and Soft Computing 2013 (2013): 1–13. http://dx.doi.org/10.1155/2013/426962.

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Intel Moore observed an exponential doubling in the number of transistors in every 18 months through the size reduction of transistor components since 1965. In viewing of mobile computing with insatiate appetite, we explored the necessary enhancement by an increasingly maturing nanotechnology and facing the inevitable quantum-mechanical atomic and nuclei limits. Since we cannot break down the atomic size barrier, the fact implies a fundamental size limit at the atomic/nucleus scale. This means, no more simple 18-month doubling, but other forms of transistor doubling may happen at a different slope. We are particularly interested in the nano enhancement area. (i) 3 Dimensions: If the progress in shrinking the in-plane dimensions is to slow down, vertical integration can help increasing the areal device transistor density. As the devices continue to shrink into the 20 to 30 nm range, the consideration of thermal properties and transport in such devices becomes increasingly important. (ii) Quantum computing: The other types of transistor material are rapidly developed in laboratories worldwide, for example, Spintronics, Nanostorage, HP display Nanotechnology, which are modifying this Law. We shall consider the limitation of phonon engineering fundamental information unit “Qubyte” in quantum computing, Nano/Micro Electrical Mechanical System (NEMS), Carbon Nanotubes, single-layer Graphenes, single-strip Nano-Ribbons, and so forth.

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Dadoria, Ajay Kumar, Kavita Khare, Traun K. Gupta, and R. P. Singh. "A Survey on Nano-Scale Double Gate CMOS Transistor." Advanced Science Letters 21, no. 9 (September 1, 2015): 2830–32. http://dx.doi.org/10.1166/asl.2015.6365.

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Mukhopadhyay, Joyjit, and Soumya Pandit. "Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics." VLSI Design 2012 (April 22, 2012): 1–13. http://dx.doi.org/10.1155/2012/505983.

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This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.

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Tripathi, Suman Lata. "Pocket Vertical Junction-Less U-Shape Tunnel FET and Its Challenges in Nano-Scale Regime." Advanced Science, Engineering and Medicine 11, no. 12 (December 1, 2019): 1225–30. http://dx.doi.org/10.1166/asem.2019.2466.

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Low voltage application of Tunnel FET with steep subthreshold slope, has potential to replace its MOSFET counterpart for future scaling due to thermal limits imposed on nano-level transistors. Longer channel region increases the tunneling area results in increasing tunneling current and decreasing miller capacitance to improve device switching performance for digital application. A new pocket tunnel junction-less UTFET (JLUTFET) exploits increased channel length with U shape and high ON current capability of junction-less transistor provide better device performance in subthreshold region showing improvement in ION/IOFF(∼109) as compared to other similar conventional TFET and vertical TFET structures. The proposed nJLUTFET also shows lower drain induced barrier lowering (<20 mV/V) and near to ideal subthreshold slope (∼66 mV/decade). The temperature analysis plays a vital role to decide a stable ON and OFF-state performance of transistors. So, the proposed pocket JLUTFET is investigated for temperature variations (ranging 250–400 K) to characterize the performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed n-channel JLUTFET has been designed on visual TCAD 2D/3D device simulator.

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Walker, James Alfred, Richard Sinnott, Gordon Stewart, James A. Hilder, and Andy M. Tyrrell. "Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 368, no. 1925 (August 28, 2010): 3967–81. http://dx.doi.org/10.1098/rsta.2010.0150.

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The project Meeting the Design Challenges of nano-CMOS Electronics ( http://www.nanocmos.ac.uk ) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.

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Mehrad, Mahsa, and Meysam Zareiee. "Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET." ECS Journal of Solid State Science and Technology 5, no. 7 (2016): M74—M77. http://dx.doi.org/10.1149/2.0231607jss.

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Yu, Chang Hong. "Accurate SER Estimation by Transform Matrix Analysis for Fault Tolerant Circuits Design." Advanced Materials Research 121-122 (June 2010): 87–92. http://dx.doi.org/10.4028/www.scientific.net/amr.121-122.87.

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As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of nano-electronics will have significantly impact on the way of circuits design, so defects and faults of nano-scale circuit technologies have to be taken into account early in the design of digital systems. Fault-tolerant architectures may become a necessity to ensure that the underlying circuit could function properly. In CAD software, a same logic can be made out with different circuits but different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the error rate of the circuit efficiently to make the design more fault tolerant. In this paper, a new way to fault tolerance design in nano-scale circuit by accurate soft error rate (SER) estimation is proposed. Transform matrix is used for SER computation and a design criteria is then proposed. Simulation results show that the proposed transform matrix model is effective for nano-scale circuits and the criteria delivered is suitable CAD tools development in nano-system design.

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Rjoub, Abdoul, Almotasem Bellah Alajlouni, and Hassan Almanasrah. "Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits." Circuits and Systems 04, no. 02 (2013): 123–36. http://dx.doi.org/10.4236/cs.2013.42018.

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RANA, ASHWANI K., NAROTTAM CHAND, and VINOD KAPOOR. "MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER." Journal of Circuits, Systems and Computers 20, no. 08 (December 2011): 1659–75. http://dx.doi.org/10.1142/s0218126611008006.

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Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

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Chang, Jeesoo, Sungmin Hwang, Kyungchul Park, Taejin Jang, Kyung-Kyu Min, Min-Hye Oh, Jonghyuk Park, Jong-Ho Lee, and Byung-Gook Park. "A Systematic Compact Model Parameter Calibration with Adaptive Pattern Search Algorithm." Applied Sciences 11, no. 9 (May 1, 2021): 4155. http://dx.doi.org/10.3390/app11094155.

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A systematic device-model calibration (extraction) methodology has been proposed to reduce parameter calibration time of advanced compact model for modern nano-scale semiconductor devices. The adaptive pattern search algorithm is a variant of the direct search method, which explore in the parameter space with adaptive searching step and direction. It is very straightforward, but powerful, in high dimensional optimization problem since adaptive step and direction are decided by simple computation. The proposed method iterates less but shows superior accuracy over the conventional method. It is possible to be applied to a behavioral or empirical model correspond to emerging devices, such as tunneling field-effect transistor (TFET) and negative capacitance field-effect transistor (NCFET) due to its universality in parameter calibration for the model accuracy.

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Phoohinkong, Weerachon, and Thitinat Sukonket. "A Simple Method for Large-Scale Synthesis of Nano-Sized Zinc Sulfide." Advanced Materials Research 979 (June 2014): 188–91. http://dx.doi.org/10.4028/www.scientific.net/amr.979.188.

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nanosized zinc sulfide (ZnS) is a special property semiconductor material widely used in many applications such as catalyst, light emitting diode, transistor, gas sensors, biosensors, UV-light sensors, and photovoltaic cell. The wet chemical method is a simple and low-cost method to prepare nanosized zinc sulfide. However, the wet chemical reaction using sodium sulfide without surfactant or template has rarely been reported. In the present work nanosized zinc sulfide particles were synthesized by simple wet chemical reaction method at room temperature and without any surfactant. The influence of sulfur source, sodium sulfide and potassium sulfide used as the reactant were investigated. The samples were characterized by scanning electron microscopy coupling with energy-dispersive X-ray spectroscopy (FESEM-EDX), and transmission electron microscopy (TEM). The results show that the nanoparticles of zinc sulfide were obtained from sodium sulfide and potassium sulfide with particles sizes are in the range of 10 to 50 nm and 25 to 50 nm respectively. In addition, from FESEM microphotograph the primary ZnS particles size of around 5 nm and 25 nm were obtained by 10% salt (sodium chloride, potassium chloride, sodium acetate) addition with sodium sulfide and potassium sulfide reactant respectively.

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Charles Pravin, J., D. Nirmal, P. Prajoon, N. Mohan Kumar, and J. Ajayan. "Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor." Superlattices and Microstructures 104 (April 2017): 470–76. http://dx.doi.org/10.1016/j.spmi.2017.03.012.

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Waheed, Sajjad, and Md Golam Rasel. "Design and Implementation of New Feynman and Toffoli (NFT) Gates in Quantum-dot Cellular Automata (QCA)." Circulation in Computer Science 2, no. 4 (May 20, 2017): 64–67. http://dx.doi.org/10.22632/ccs-2017-252-10.

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In this paper, New Feynman and Toffoli (NFT) gate is proposed based on QCA logic gates. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. A novel electronics paradigm for information processing and communication by QCA offers technology. QCA technology has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology.

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Yang Min-Yu, Song Jian-Jun, Zhang Jing, Tang Zhao-Huan, Zhang He-Ming, and Hu Hui-Yong. "Physical mechanism of uniaxial strain in nano-scale metal oxide semiconductor transistor caused by sin film." Acta Physica Sinica 64, no. 23 (2015): 238502. http://dx.doi.org/10.7498/aps.64.238502.

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Mehrad, Mahsa. "Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P+Region SOI-MOSFET." ECS Journal of Solid State Science and Technology 5, no. 9 (2016): M88—M92. http://dx.doi.org/10.1149/2.0251609jss.

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Waheed, Sajjad, Sharmin Aktar, and Ali Newaz Bahar. "A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)." European Scientific Journal, ESJ 13, no. 15 (May 31, 2017): 265. http://dx.doi.org/10.19044/esj.2017.v13n15p265.

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In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.

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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

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Laribi, Asma, and Ahlam Guen Bouazza. "Effect of Chirality and Oxide Thikness on the Performance of a Ballistic CNTFET." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4941. http://dx.doi.org/10.11591/ijece.v8i6.pp4941-4950.

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<p>Since the discovery of 1D nano-object, they are constantly revealing significant physical properties. In this regard, carbon nanotube (CNT) is considered as a promising candidate for application in future nanoelectronics devices like carbon nanotube field effect transistor (CNTFET). In this work, the impact of chirality and gate oxide thikness on the electrical characteristics of a CNTFET are studied. The chiralities used are (5, 0), (10, 0), (19, 0), (26, 0), and the gate oxide thikness varied from 1 to 5 nm.This work is based on a numerical simulation program based on surface potential model. CNTFET Modeling is useful for semiconductor industries for nano scale devices manufacturing. From our results we have observed that the output current increases with chirality increasing.We have also highlight the importance of the gate oxide thickness on the drain current that increases when gate oxide is thin.</p>

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Farrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri, and Bita Davoodi. "Effect of Varying Dielectric Constant on Relative Stability for Graphene Nanoribbon Interconnects." Applied Mechanics and Materials 229-231 (November 2012): 201–4. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.201.

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The remarkable properties of graphene nanoribbons (GNRs) make them attractive for nano-scale devices applications, especially for transistor and interconnect. Furthermore, for reduction interconnects signal delay, low dielectric constant materials are being introduced to replace conventional dielectrics in next generation IC technologies. With these regards, studding the effect of varying dielectric constant (ɛr) on relative stability of graphene nanoribbons interconnect is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for graphene nanoribbon interconnects is investigated. In this analysis, the dependence of the degree of relative stability for multilayer GNR (MLGNR) interconnects on the dielectric constant has been acquired. It is shown that, increasing the dielectric constant of each ribbon, MLGNR interconnects become more stable.

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Liu, Canchang, Ruirui Jiang, Lei Li, and Yingchao Zhou. "Nonlinear Vibration Control for Nanobeam with Time Delay by Field Effect Transistor Sensing." International Journal of Structural Stability and Dynamics 21, no. 10 (June 17, 2021): 2150145. http://dx.doi.org/10.1142/s0219455421501455.

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A vibration control signal sensing method is proposed utilizing the grid electrode displacement sensitive effect of field-effect transistors. The signal sensing method is applied to nonlinear resonance delay control of a nanobeam that is used as the core component of nano–microdevices. The nonlinear vibration dynamical model of the nanobeam based on the field-effect tube sensing is established and the differential equation of motion with time delay control is presented. The amplitude frequency response equation and phase frequency response equation of the nanobeam are obtained by analyzing the first-order approximate solution of the primary and superharmonic vibration of the nonlinear equation with multi-scale method. The vibration feedback gain and time delay can affect the vibration amplitude and nonlinear behavior of the nanobeam. The nonlinear vibration of the nanobeam can be adjusted and effectively controlled by selecting appropriate feedback gains and time delays.

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Malara, Natalia, Francesco Gentile, Lorenzo Ferrara, Marco Villani, Salvatore Iannotta, Andrea Zappettini, Enzo Di Fabrizio, Valentina Trunzo, Vincenzo Mollace, and Nicola Coppedé. "Tailoring super-hydrophobic properties of electrochemical biosensor for early cancer detection." MRS Advances 1, no. 52 (2016): 3545–52. http://dx.doi.org/10.1557/adv.2016.543.

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ABSTRACTIn this paper, we demonstrate an organic electrochemical transistor (OECT) based on the conductive polymer PEDOT:PSS for the analysis of the cell culture medium upon interaction with circulating cells isolated form peripheral blood sampling of health, sub-clinical and cancer patients. The device comprises arrays of super-hydrophobic micro-pillars in which a finite number of pillars incorporates nano-electrodes for site specific measurements of a solution. Due to its nano-scale architecture, the device realizes time and space resolved measurement of biological solution. Tumor metabolism could produce reactive species able to determine a different electronic behavior of correspondent microenviroment. On this basis, the device here presented the changes in the ESR signals was used to identify electronic changes occurring in the analysis of different type of microenvironment. Our results demonstrate that the device is able to register significative difference to differentiate healthy individuals form cancer patients, through an easy blood sampling. In conclusion, these preliminary data are suggestive of a novel test potentially useful to early identification of subjects at risk to development cancer disease.

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Khan, Fasihullah, Waqar Khan, and Sam-Dong Kim. "High-Performance Ultraviolet Light Detection Using Nano-Scale-Fin Isolation AlGaN/GaN Heterostructures with ZnO Nanorods." Nanomaterials 9, no. 3 (March 15, 2019): 440. http://dx.doi.org/10.3390/nano9030440.

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Owing to their intrinsic wide bandgap properties ZnO and GaN materials are widely used for fabricating passive-type visible-blind ultraviolet (UV) photodetectors (PDs). However, most of these PDs have a very low spectral responsivity R, which is not sufficient for detecting very low-level UV signals. We demonstrate an active type UV PD with a ZnO nanorod (NR) structure for the floating gate of AlGaN/GaN high electron mobility transistor (HEMT), where the AlGaN/GaN epitaxial layers are isolated by the nano-scale fins (NFIs) of two different fin widths (70 and 80 nm). In the dark condition, oxygen adsorbed at the surface of the ZnO NRs generates negative gate potential. Upon UV light illumination, the negative charge on the ZnO NRs is reduced due to desorption of oxygen, and this reversible process controls the source-drain carrier transport property of HEMT based PDs. The NFI PDs of a 70 nm fin width show the highest R of a ~3.2 × 107 A/W at 340 nm wavelength among the solid-state UV PDs reported to date. We also compare the performances of NFI PDs with those of conventional mesa isolation (MI, 40 × 100 µm2). NFI devices show ~100 times enhanced R and on-off current ratio than those of MI devices. Due to the volume effect of the small active region, a much faster response speed (rise-up and fall-off times of 0.21 and 1.05 s) is also obtained from the NFI PDs with a 70 nm fin width upon the UV on-off transient.

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Chin, Huei Chaeng, Cheng Siong Lim, Weng Soon Wong, Kumeresan A. Danapalasingam, Vijay K. Arora, and Michael Loong Peng Tan. "Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects." Journal of Nanomaterials 2014 (2014): 1–14. http://dx.doi.org/10.1155/2014/879813.

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Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-VdandId-Vg), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (November 11, 2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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Park, Jae Hyo, Hyung Yoon Kim, Ki Hwan Seok, Zohreh Kiaee, Hee Jae Chae, and Seung Ki Joo. "50-nm Nano-Scaled Vertical-Transistor with NiSi2 Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration." Journal of Nanoscience and Nanotechnology 17, no. 2 (February 1, 2017): 1296–99. http://dx.doi.org/10.1166/jnn.2017.12634.

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Li, Haixia, Aiming Ji, Canyan Zhu, and Ling-Feng Mao. "Structure properties and electrical mechanisms of Si(001)/SiO 2 interface with varying Si layer thickness in nano-scale transistor." Current Applied Physics 18, no. 9 (September 2018): 1020–25. http://dx.doi.org/10.1016/j.cap.2018.05.010.

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Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (May 31, 2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.

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In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for future Integrated Circuits (ICs). A quantum dot cellular automaton complex gate is composed from simple 3-input majority gate. In this paper, a 8-3 encoder circuit is proposed based on QCA logic gates: the 4-input Majority Voter (MV) OR gate. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, 2-input AND and 2-input OR gates, 2-input complex gates, multi-input complex gates. The proposed circuit has a promising future in the area of nano-computing information processing system and can be stimulated with higher digital applications in QCA.

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Li, Fang, Zhongrong Wang, and Yunfang Jia. "Reduced Carboxylate Graphene Oxide based Field Effect Transistor as Pb2+ Aptamer Sensor." Micromachines 10, no. 6 (June 11, 2019): 388. http://dx.doi.org/10.3390/mi10060388.

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Aptamer functionalized graphene field effect transistor (apta-GFET) is a versatile bio-sensing platform. However, the chemical inertness of graphene is still an obstacle for its large-scale applications and commercialization. In this work, reduced carboxyl-graphene oxide (rGO-COOH) is studied as a self-activated channel material in the screen-printed apta-GFETs for the first time. Examinations are carefully executed using lead-specific-aptamer as a proof-of-concept to demonstrate its functions in accommodating aptamer bio-probes and promoting the sensing reaction. The graphene-state, few-layer nano-structure, plenty of oxygen-containing groups and enhanced LSA immobilization of the rGO-COOH channel film are evidenced by X-ray photoelectron spectroscopy, Raman spectrum, UV-visible absorbance, atomic force microscopy and scanning electron microscope. Based on these characterizations, as well as a site-binding model based on solution-gated field effect transistor (SgFET) working principle, theoretical deductions for rGO-COOH enhanced apta-GFETs’ response are provided. Furthermore, detections for disturbing ions and real samples demonstrate the rGO-COOH channeled apta-GFET has a good specificity, a limit-of-detection of 0.001 ppb, and is in agreement with the conventional inductively coupled plasma mass spectrometry method. In conclusion, the careful examinations demonstrate rGO-COOH is a promising candidate as a self-activated channel material because of its merits of being independent of linking reagents, free from polymer residue and compatible with rapidly developed print-electronic technology.

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Xie, Lu, Huilong Zhu, Yongkui Zhang, Xuezheng Ai, Guilei Wang, Junjie Li, Anyan Du, et al. "Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium." Nanomaterials 10, no. 9 (August 29, 2020): 1715. http://dx.doi.org/10.3390/nano10091715.

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With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

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KISHI, Hiroki, Ken SUZUKI, and Hideo MIURA. "116 Development of in-line evaluation measurement method of the change of the residual stress in nano-scale transistor structures during manufacturing." Proceedings of Conference of Tohoku Branch 2010.45 (2010): 34–35. http://dx.doi.org/10.1299/jsmeth.2010.45.34.

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Ghosal, Subhro, Madhabi Ganguly, and Debarati Ghosh. "A Study on Sensitivity of Some Switching Parameters of JLT to Structural Parameters." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 433–46. http://dx.doi.org/10.2174/2210681209666190905124818.

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Background: The stringent technological constraints imposed by the requirement of ultra-sharp doping profiles associated with the sub-30 nm regime has led to the search for alternatives to the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). An obvious alternative is a device whose architecture does not have any junctions in the sourcechannel- drain path. One such device is the Junctionless transistor comprising of an isolated ultrathin highly doped semiconductor layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. For widespread application in today’s high-speed circuits, a key factor would be its effectiveness as a switch. Methods: In this work we have studied the relative sensitivity of two such parameters namely the ION/IOFF ratio and gate capacitance to variations in several structural parameters of the device namely channel width, composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region and non-uniformity in the doping profile. Results: The work demonstrates through device simulations that replacement of Si with Si-Ge leads to an improvement in the performance. Conclusion: The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.

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Hao, Minru, Chenguang Liao, Qian Zhang, Yan Zhang, Min Shao, and Guoxiang Chen. "Study on the Charge Collection Mechanism of Single Event Transient Effect for Nano N-Channel Metal Oxide Semiconductor Field Effect Transistor." Journal of Nanoelectronics and Optoelectronics 15, no. 5 (May 1, 2020): 637–44. http://dx.doi.org/10.1166/jno.2020.2780.

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Based on the mechanism of charge collection, drift and diffusion, the influence of incident position, drain bias and incident particle LET (Linear Energy Transfer) value on the charge collection of NMOS devices is analyzed. It is found that the strongest electric field in drain depletion region is at 70 nm, and the maximum transient current is 3.43 mA. Drain bias affects the electric field in drain region. The higher drain bias is, the greater the electric field is, and the transient current is the larger of the peak value is, and the change of drain bias does not affect the diffusion current part; the larger the LET is, the larger the set current is, and the transient current peak value and collection charge increase linearly with the increase of LET. In addition, for a single transistor, the influence of the reduction of gate length on the bipolar amplification is analyzed, which is discovered that the reduction of gate length results in the aggravation of the single event effect. Therefore, the simulation results provide valuable reference for research on irradiation reliability and application of strained integrated circuit of Si Nano-scale NMOSFET.

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Singh, Ajay Kumar, B. Naresh Kumar, and Gan Che Sheng. "A quantum correction based model for study of quantum confinement effects in nano-scale carbon nanotube field-effect transistor (CNTFET) under inversion condition." European Physical Journal Applied Physics 78, no. 1 (April 2017): 10101. http://dx.doi.org/10.1051/epjap/2017170040.

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Kaharudin, K. E., F. Salehuddin, A. S. M. Zain, and Ameer F. Roslan. "Optimal design of junctionless double gate vertical MOSFET using hybrid Taguchi-GRA with ANN prediction." Journal of Mechanical Engineering and Sciences 13, no. 3 (September 27, 2019): 5455–79. http://dx.doi.org/10.15282/jmes.13.3.2019.16.0442.

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Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (n-JLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (Lch), pillar thickness (Tp), channel doping (Nch) and source/drain doping (Nsd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (ION), off-state current (IOFF), on-off ratio, transconductance (gm), cut-off frequency (fT) and maximum oscillation frequency (fmax), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 106, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively.

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Asyaei, Mohammad, and Farshad Moradi. "A Domino Circuit Technique for Noise-Immune High Fan-In Gates." Journal of Circuits, Systems and Computers 27, no. 10 (May 24, 2018): 1850151. http://dx.doi.org/10.1142/s0218126618501517.

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Noise immunity is an important concern in deep nano-scale technologies, especially for high fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise immunity of high fan-in gates increases while the power consumption reduces. The proposed technique is based on the comparison of two currents, which vary with respect to the voltage across the pull-down network (PDN). By comparing these currents, the voltage level of the dynamic node is pulled up or pulled down depending on the input voltages. Using this technique, the voltage swing on the PDN can be decreased to reduce the power consumption. Moreover, a diode-connected NMOS transistor is added in series with the PDN in the proposed technique. This will result in reducing the subthreshold leakage current due to the stacking effect and, as a result, the noise immunity will improve. To demonstrate the efficacy of the proposed domino design over the conventional techniques, high fan-in gates are designed and compared in 90[Formula: see text]nm CMOS technology. Simulation results exhibit at least 1.87X noise immunity improvement and 20% power consumption reduction in comparison to the standard footless domino (SFLD) circuits at the same delay.

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Martinez, Antonio, and John Barker. "Quantum Transport in a Silicon Nanowire FET Transistor: Hot Electrons and Local Power Dissipation." Materials 13, no. 15 (July 26, 2020): 3326. http://dx.doi.org/10.3390/ma13153326.

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A review and perspective is presented of the classical, semi-classical and fully quantum routes to the simulation of electro-thermal phenomena in ultra-scaled silicon nanowire field-effect transistors. It is shown that the physics of ultra-scaled devices requires at least a coupled electron quantum transport semi-classical heat equation model outlined here. The importance of the local density of states (LDOS) is discussed from classical to fully quantum versions. It is shown that the minimal quantum approach requires self-consistency with the Poisson equation and that the electronic LDOS must be determined within at least the self-consistent Born approximation. To bring in this description and to provide the energy resolved local carrier distributions it is necessary to adopt the non-equilibrium Green function (NEGF) formalism, briefly surveyed here. The NEGF approach describes quantum coherent and dissipative transport, Pauli exclusion and non-equilibrium conditions inside the device. There are two extremes of NEGF used in the community. The most fundamental is based on coupled equations for the Green functions electrons and phonons that are computed at the atomically resolved level within the nanowire channel and into the surrounding device structure using a tight binding Hamiltonian. It has the advantage of treating both the non-equilibrium heat flow within the electron and phonon systems even when the phonon energy distributions are not described by a temperature model. The disadvantage is the grand challenge level of computational complexity. The second approach, that we focus on here, is more useful for fast multiple simulations of devices important for TCAD (Technology Computer Aided Design). It retains the fundamental quantum transport model for the electrons but subsumes the description of the energy distribution of the local phonon sub-system statistics into a semi-classical Fourier heat equation that is sourced by the local heat dissipation from the electron system. It is shown that this self-consistent approach retains the salient features of the full-scale approach. For focus, we outline our electro-thermal simulations for a typical narrow Si nanowire gate all-around field-effect transistor. The self-consistent Born approximation is used to describe electron-phonon scattering as the source of heat dissipation to the lattice. We calculated the effect of the device self-heating on the current voltage characteristics. Our fast and simpler methodology closely reproduces the results of a more fundamental compute-intensive calculations in which the phonon system is treated on the same footing as the electron system. We computed the local power dissipation and “local lattice temperature” profiles. We compared the self-heating using hot electron heating and the Joule heating, i.e., assuming the electron system was in local equilibrium with the potential. Our simulations show that at low bias the source region of the device has a tendency to cool down for the case of the hot electron heating but not for the case of Joule heating. Our methodology opens the possibility of studying thermoelectricity at nano-scales in an accurate and computationally efficient way. At nano-scales, coherence and hot electrons play a major role. It was found that the overall behaviour of the electron system is dominated by the local density of states and the scattering rate. Electrons leaving the simulated drain region were found to be far from equilibrium.

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ZHANG, YUEGANG. "CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES." International Journal of High Speed Electronics and Systems 16, no. 04 (December 2006): 959–75. http://dx.doi.org/10.1142/s0129156406004107.

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The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

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Sharma, Anjali, Harsh Sohal, and Harsimran Jit Kaur. "Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design." Journal of Circuits, Systems and Computers 28, no. 12 (November 2019): 1950197. http://dx.doi.org/10.1142/s0218126619501974.

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This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

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Kim, Jae Seon, and Chung Kun Song. "Textile Display with AMOLED Using a Stacked-Pixel Structure on a Polyethylene Terephthalate Fabric Substrate." Materials 12, no. 12 (June 22, 2019): 2000. http://dx.doi.org/10.3390/ma12122000.

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An active-mode organic light-emitting diode (AMOLED) display on a fabric substrate is expected to be a prominent textile display for e-textile applications. However, the large surface roughness of the fabric substrate limits the aperture ratio—the area ratio of the organic light-emitting diode (OLED) to the total pixel area. In this study, the aperture ratio of the AMOLED panel fabricated on the polyethylene terephthalate fabric substrate was enhanced by applying a stacked-pixel structure, in which the OLED was deposited above the organic thin-film transistor (OTFT) pixel circuit layer. The stacked pixels were achieved using the following three key technologies. First, the planarization process of the fabric substrate was performed by sequentially depositing a polyurethane and photo-acryl layer, improving the surface roughness from 10 μm to 0.3 μm. Second, a protection layer consisting of three polymer layers, a water-soluble poly-vinyl alcohol, dichromated-polyvinylalcohol (PVA), and photo acryl, formed by a spin-coating processes was inserted between the OTFT circuit and the OLED layer. Third, a high mobility of 0.98 cm2/V∙s was achieved at the panel scale by using hybrid carbon nano-tube (CNT)/Au (5 nm) electrodes for the S/D contacts and the photo-acryl (PA) for the gate dielectric, enabling the supply of a sufficiently large current (40 μA @ VGS = −10 V) to the OLED. The aperture ratio of the AMOLED panel using the stacked-pixel structure was improved to 48%, which was about two times larger than the 19% of the side-by-side pixel, placing the OLED just beside the OTFTs on the same plane.

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Horsell, D. W., A. K. Savchenko, Y. M. Galperin, V. I. Kozub, and V. M. Vinokur. "Phonon-electric effect in nano-scale transistors." physica status solidi (c) 2, no. 8 (May 2005): 3047–50. http://dx.doi.org/10.1002/pssc.200460723.

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Tsukagoshi, Kazuhito, Iwao Yagi, and Yoshinobu Aoyagi. "Nano-scale interface controls for future plastic transistors." Science and Technology of Advanced Materials 7, no. 3 (January 2006): 231–36. http://dx.doi.org/10.1016/j.stam.2006.01.001.

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Medina-Bailon, Cristina, Tapas Dutta, Ali Rezaei, Daniel Nagy, Fikru Adamu-Lema, Vihar P. Georgiev, and Asen Asenov. "Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework." Micromachines 12, no. 6 (June 10, 2021): 680. http://dx.doi.org/10.3390/mi12060680.

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The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.

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Xiong, Shiying, Tsu-Jae King, and Jeffrey Bokor. "Study of the extrinsic parasitics in nano-scale transistors." Semiconductor Science and Technology 20, no. 6 (May 6, 2005): 652–57. http://dx.doi.org/10.1088/0268-1242/20/6/029.

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Lee, Jun-Ha. "A Study on Parasitic Resistance in Nano-Scale Transistors." Journal of Computational and Theoretical Nanoscience 6, no. 11 (November 1, 2009): 2437–41. http://dx.doi.org/10.1166/jctn.2009.1304.

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Li, Junjie, Yongliang Li, Na Zhou, Wenjuan Xiong, Guilei Wang, Qingzhu Zhang, Anyan Du, et al. "Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors." Nanomaterials 10, no. 4 (April 20, 2020): 793. http://dx.doi.org/10.3390/nano10040793.

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Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

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Shekar, B. Chandar, S. Sathish, and R. Sengoden. "Spin Coated Nano Scale PMMA Films for Organic Thin Film Transistors." Physics Procedia 49 (2013): 145–57. http://dx.doi.org/10.1016/j.phpro.2013.10.021.

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Villis, B. J., A. O. Orlov, X. Jehl, G. L. Snider, P. Fay, and M. Sanquer. "Defect detection in nano-scale transistors based on radio-frequency reflectometry." Applied Physics Letters 99, no. 15 (October 10, 2011): 152106. http://dx.doi.org/10.1063/1.3647555.

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Radamson, Henry H., Huilong Zhu, Zhenhua Wu, Xiaobin He, Hongxiao Lin, Jinbiao Liu, Jinjuan Xiang, et al. "State of the Art and Future Perspectives in Advanced CMOS Technology." Nanomaterials 10, no. 8 (August 7, 2020): 1555. http://dx.doi.org/10.3390/nano10081555.

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Joester, Derk, Andrew Hillier, Yi Zhang, and Ty J. Prosa. "Organic Materials and Organic/Inorganic Heterostructures in Atom Probe Tomography." Microscopy Today 20, no. 3 (May 2012): 26–31. http://dx.doi.org/10.1017/s1551929512000260.

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Nano-scale organic/inorganic interfaces are key to a wide range of materials. In many biominerals, for instance bone or teeth, outstanding fracture toughness and wear resistance can be attributed to buried organic/inorganic interfaces. Organic/inorganic interfaces at very small length scales are becoming increasingly important also in nano and electronic materials. For example, functionalized inorganic nanomaterials have great potential in biomedicine or sensing applications. Thin organic films are used to increase the conductivity of LiFePO4 electrodes in lithium ion batteries, and solid electrode interphases (SEI) form by uncontrolled electrolyte decomposition. Organics play a key role in dye-sensitized solar cells, organic photovoltaics, and nano-dielectrics for organic field-effect transistors. The interface between oxide semiconductors and polymer substrates is critical in emergent applications, for example, flexible displays.

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Journal articles on the topic 'Nano-scale transistor'

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