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Khakifirooz, Ali. "Transport enhancement techniques for nanoscale MOSFETs." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/42907.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 155-183).<br>Over the past two decades, intrinsic MOSFET delay has been scaled commensurate with the scaling of the dimensions. To extend this historical trend in the future, careful analysis of what determines the transistor performance is required. In this work, a new delay metric is first introduced that better captures the interplay of the main technology parameters, and employed to study the historical trends of the performance scaling and to quantify the requirements for the continuous increase of the performance in the future. It is shown that the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. A roadmapping exercise is presented and it is shown that new channel materials are needed to lever carrier velocity beyond what is achieved with uniaxially strained silicon, along with dramatic reduction in the device parasitics. Such innovations are needed as early as the 32-nm node to avoid the otherwise counter-scaling of the performance. The prospects and limitations of various approaches that are being pursued to increase the carrier velocity and thereby the transistor performance are then explored. After introducing the basics of the transport in nanoscale MOSFETs, the impact of channel material and strain configuration on electron and hole transport are examined. Uniaixal tensile strain in silicon is shown to be very promising to enhance electron transport as long as higher strain levels can be exerted on the device. Calculations and analysis in this work demonstrate that in uniaxially strained silicon, virtual source velocity depends more strongly on the mobility than previously believed and the modulation of the effective mass under uniaxial strain is responsible for this string dependence.<br>(cont) While III-V semiconductors are seriously limited by their small quantization effective mass, which limits the available inversion charge at a given voltage overdrive, germanium is attractive as it has enhanced transport properties for both electrons and holes. However, to avoid mobility degradation due to carrier confinement as well as L - interband scattering, and to achieve higher ballistic velocity, (111) wafer orientation should be used for Ge NFETs. Further analysis in this work demonstrate that with uniaixally strained Si, hole 3 ballistic velocity enhancement is limited to about 2x, despite the fact that mobility enhancement of about 4x has been demonstrated. Hence, further increase of the strain level does not seem to provide major increase in the device performance. It is also shown that relaxed germanium only marginally improves hole velocity despite the fact that mobility is significantly higher than silicon. Biaxial compressive strain in Ge, although relatively simple to apply, offers only 2x velocity enhancement over relaxed silicon. Only with uniaxial compressive strain, is germanium able to provide significantly higher velocities compared to state-of-the-art silicon MOSFETs. Most recently, germanium has manifested itself as an alternative channel material because of its superior electron and hole mobility compared to silicon. Functional MOS transistors with relatively good electrical characteristics have been demonstrated by several groups on bulk and strained Ge. However, carrier mobility in these devices is still far behind what is theoretically expected from germanium. Very high density of the interface states, especially close to the conduction band is believed to be responsible for poor electrical characteristics of Ge MOSFETs. Nevertheless, a through investigation of the transport in Ge-channel MOSFETs and the correlation between the mobility and trap density has not been undertaken in the past.<br>(cont) Pulsed I -V and Q-V measurement are performed to characterize near intrinsic transport properties in Ge-channel MOSFETs. Pulsed measurements show that the actual carrier mobility is at least twice what is inferred from DC measurements for Ge NFETs. With phosphorus implantation at the Ge-dielectric interface the difference between DC and pulsed measurements is reduced to about 20%, despite the fact that effects of charge trapping are still visible in these devices. To better understand the dependence of carrier transport on charge trapping, a method to directly measure the inversion charge density by integrating the S/D current is proposed. The density of trapped charges is measured as the difference between the inversion charge density at the beginning and end of pulses applied to the gate. Analysis of temporal variation of trapped charge density reveals that two regimes of fast and slow charge trapping are present. Both mechanisms show a logarithmic dependence on the pulse width, as observed in earlier literature charge-pumping studies of Si MOSFETs with high- dielectrics. The correlation between mobility and density of trapped charges is studied and it is shown that the mobility depends only on the density of fast traps. To our knowledge, this is the first investigation in which the impact of the fast and slow traps on the mobility has been separated. Extrapolation of the mobility-trap relationship to lower densities of trapped charges gives an upper limit on the available mobility with the present gate stack if the density of the fast traps is reduced further. However, this analysis demonstrates that the expected mobility is still far below what is obtained in Si MOSFETs. Further investigations are needed to analyze other mechanisms that might be responsible for poor electron mobility in Ge MOSFETs and thereby optimize the gate stack by suppressing these mechanisms.<br>by Ali Khakifirooz.<br>Ph.D.
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Holtij, Thomas. "ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS." Doctoral thesis, Universitat Rovira i Virgili, 2014. http://hdl.handle.net/10803/284038.
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L’objectiu principal d’aquest treball és el desenvolupament d’un model compacte per a MOSFETs de múltiple porta d’escala nanomètrica, que sigui analític, basat en la física del dispositiu, i predictiu per a simulacions AC i DC. Els dispositius investigats són el MOSFET estàndar en mode d’inversió, a més d’un nou dispositiu anomenat “junctionless MOSFET” (MOSFET sense unions).
El model es va desenvolupar en una formulació compacta amb l’ajuda de l’equació de Poisson i la tècnica de la transformación conforme de Schwarz-Cristoffel. Es varen obtenir les equacions del voltatge llindar i el pendent subllindar. Usant la funció W de Lambert, a més d’una funció de suavització per a la transcició entre les regions de depleció i acumulació, s’obté un model unificat de la densitat de càrrega, vàlid per a tots els modes d’operació del transistor. S’estudien també les dependències entre els paràmetres físics del dispositiu i el seu impacte en el seu rendiment. Es tenen en compteefectes importants de canal curt i de quantització. Es discuteixen també la simetria al voltant de Vds= 0 V, i la continuïtat del corrent de drenador en les derivades d’ordre superior. El model va ser validat mitjançant simulacions TCAD numèriques i mesures experimentals.<br>El objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones).
El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.<br>The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET.
The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data.
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Iqbal, M. M. H. "On the static performance of lateral high voltage MOSFETs and novel nanoscale accumulation mode MOSFETs." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604944.
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This research relates to static performance assessment of high voltage lateral MOSFETs and novel nanoscale accumulation mode MOSFETs. The static performance of the power semiconductor devices refers to breakdown voltage (BV) and specific on-resistance (sRon). Devising a relation or a power law between BV and sRon is absolutely crucial, as it determines the design criteria, the scaling of a technology with a voltage rating, the cost and ultimately the wider applicability of the technology in market. Here a technology-specific power law is proposed, which is applied to different Reduced SURface Field (RESURF) technologies for lateral power MOSFETs. The proposed power law introduces two technology-specific parameters, α and β, which are coupled with Baliga’s power law. Whilst in Baliga’s power law, parameters α and β are constant, here it will be demonstrated via comprehensive numerical simulations that parameters α and β can be different in various RESURF technologies. The numerical analysis also includes the variations of parameters α and β at maximum junction temperature of 125°C. First order 1D analytical models are proposed to examine the dependence of parameters α and β on technological process parameters and technology dictated material properties. A close match between the experimental data from the literature and the numerical-analytical results, establishes the validity of the newly proposed sRon vs. BV power law. This work takes into account that state-of-the-art RESURF technologies, i.e. single-, double-, triple-RESURF, partial SOI and linearly graded thin film SOI LDMOSFETs. The static performance of a nanoscale accumulation mode MOSFET incorporates to on-current, off-current, on-off ratio, threshold voltage, and subthreshold swing. A novel nanoscale transistor named Accumulation Metal Oxide Semiconductor Field Effect Transistor (AMOSFET) is proposed and experimentally demonstrated, which reveals excellent static performance. The AMOSFET is a very simple configuration that can have high performance transistors on thin films, a silicon-on-insulator (SOI) and nanowires (NWs). The configuration only requires a single doping type as the active layer, ohmic source and drain contacts spaced at minimum required distance from the gate, a minimum length gate, and a nanoscale dimension perpendicular to the gate. The nanoscale depth dimension forces the current path through an accumulated (on-state) or depleted (off-state) region. The numerical simulation study describes the static state operation, the role of gate capacitance and the importance of contacts’ ohmicity. Furthermore, the optimum device design considerations are also examined in numerical study. It is revealed in numerical study that the drain current has a weak dependence on the magnitude of the gate capacitance and the drive current is closely proportional to the mobility-doping density product.
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Holen, Åsmund. "Compact Modeling of the Current through Nanoscale Double-Gate MOSFETs." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9918.
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<p>In this thesis a compact drain current model for nanoscale double-gate MOSFETs is presented. The model covers all operation regimes and bias voltages up to 0.4V. The modeling is done using conformal mapping techniques to solve the 2D Laplace equation in sub-threshold, and using a long channel model in strong-inversion. In near threshold, a quasi-Fermi level model which uses empirical constants is used to find the current. A continuous model is found by expressing asymptotes in the sub-threshold and strong inversion regimes, and combining them using a interpolation function. The interpolation function uses a parameter that is decided analytically from the near threshold calculations. The model shows good agreement with numerical simulations for bias voltages below 0.4V and channel lengths bellow 50nm.</p>
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Bufler, Fabian M. "Full-band Monte Carlo simulation of nanoscale strained-silicon MOSFETs /." Konstanz : Hartung-Gorre, 2003. http://www.loc.gov/catdir/toc/fy0604/2004441049.html.
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Ting, Darwin Ta-Yueh. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.
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Kolberg, Sigbjørn. "Modeling of Electrostatics and Drain Current in Nanoscale Double-Gate MOSFETs." Doctoral thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1729.
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<p>This work comprises a new technique for 2D compact modeling of short-channel, nanoscale, double-gate MOSFETs. In low-doped devices working in the subthreshold regime, the potential distribution is dominated by the capacitive coupling between the body contacts. This 2D potential is determined by an analytical solution of the Laplace equation for the body using the technique of conformal mapping. Near threshold, where the spatial inversion charge becomes important, a self-consistent solution is applied. In sufficiently strong inversion, the electronic charge will dominate the potential profile in central parts of the channel. For this case, an analytical solution of the 1D Poisson’s equation is used. Based on the modeled barrier topography, the drain current is calculated for the drift-diffusion transport mechanism. The results compare favorably with numerical simulations. A parametrized model for drain current, with all parameters extracted from the modeling framework, is presented as an example of a compact model suitable for inclusion in circuit simulators.</p>
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Wu, Qian. "A nanoscale study of MOSFETs reliability and Resistive Switching in RRAM devices." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/402233.
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El continuo escalado de la tecnología CMOS ha supuesto un gran reto en cuanto a la fiabilidad de dispositivos MOSFET se refiere debido al aumento del campo eléctrico en su interior, el cual ha dado lugar a la aparición de diferentes mecanismos de fallo. Entre los más importantes, destacan los que afectan al stack de puerta tales como Bias Temperature Instabilities (BTI) y channel hot carrier degradation (CHC). Por otro lado, la reversibilidad en la formación de filamentos conductores (CF) en dieléctricos de puerta ha demostrado ser una alternativa muy importante para aplicaciones de memoria no volátiles futuras, como por ejemplo la tecnología RRAM (Resistive Random Acces Memory), basada en el fenómeno de Resistive Switching (RS). Sin embargo, todavía queda por resolver numerosos retos tecnológicos, como los asociados a los electrodos, dado que el mecanismo de RS se ve fuertemente influenciado por las propiedades de sus materiales. Debido a sus excelentes propiedades, el uso de grafeno como electrodo podría ofrecer grandes ventajas. Sin embargo, la variabilidad y fiabilidad de los dispositivos basados en grafeno es todavía un tema pendiente de resolver. El objetivo de esta tesis es el estudio a la nanoescala de la fiabilidad de transistores MOSFET y del RS apra aplicaciones de memoria. Concretamente se han estudiado los siguientes tópicos. En primer lugar, se ha analizado el impacto de los estresses Bias Temperature Instability (BTI) y Channel Hot Carriers (CHC) en stacks de puerta de transistores MOSFET con CAFM. El CAFM ha demostrado que la degradación inducida durante un estrés NBTI es homogénea a lo largo del canal, mientras que el estrés CHC induce diferentes niveles de degradación, siendo mayor cerca del drenador y la fuente. En segundo lugar, se ha estudiado el impacto de estreses NBTI y CHC en MOSFETs mecánicamente estresados con SiGe en las regiones de drenador y fuente. Los resultados muestran que, aunque los dispositivos estresados mecánicamente tienen una mayor movilidad, son más sensibles a los estreses eléctricos CHC y NBTI. Este efecto se ha observado en mayor medida en dispositivos de canal corto. En los dispositivos estresados por CHC, esta mayor susceptibilidad al estrés eléctrico se ha relacionado con una densidad de defectos mayor cerca de las difusiones, de acuerdo con los datos obtenidos con CAFM. En tercer lugar, se han estudiado spots individuales a la nanoescala y a diferentes temperaturas en capas de SiON sin previo estrés eléctrico. Se han observado conmutaciones RTN entre dos estados de conductividad, que se han asociado a la captura/emisión de cargas en los defectos presentes en el dieléctrico. En cuarto lugar, se ha analizado a la nanoescala filamentos conductores (CFs) en estructuras Ni/HfO2/Si con Resistive Switching mediante CAFM. Se han observado diferencias en la conductividad del CF dependiendo del estado resistivo del dispositivo. Además, para los dos estados resistivos, la conducción a través del CF ha mostrado ser no homogénea. Finalmente, se ha estudiado las propiedades eléctricas y variabilidad de estructuras MIS capacitivas con grafeno como capa interficial entre el dieléctrico de HfO2 y el electrodo de puerta (dispositivos MGIS), así como su viabilidad como dispositivos RRAM. Se ha observado que, con la presencia de la capa interficial de grafeno, es posible medir varios ciclos de RS, mientras que en las estructuras MIS sin grafeno este comportamiento no se detectó. El análisis con CAFM ha mostrado que el grafeno evita la destrucción completa del dieléctrico durante el proceso de formación del CF, confirmando la función protectora del grafeno en estructuras MGIS.<br>The continuous scaling down of CMOS technology has stood for a big challenge for reliability researchers, mainly due to the persistent increase of the electric fields in nanoscale devices, which can trigger different failure mechanisms. Among them, those related to the MOSFET gate dielectric such as Bias Temperature Instabilities (BTI) and channel hot carrier degradation (CHC), have a special relevance. On the other hand, the reversibility in the conductive filaments formation in dielectrics has demonstrated to be very promising for future non-volatile memory applications, as Resistive Random Access Memory (RRAM) technology, which is based on the Resistive Switching (RS) phenomenon. However, many technological issues are still open as those related to the electrodes, since the RS mechanism is strongly influenced by the electrode properties. Due to its special properties, graphene used as electrode in RRAM devices could offer great advantages. However, the graphene-based devices still suffer reliability and variability issues. This thesis addresses a nanoscale study of MOSFETs reliability and Resistive Switching in RRAM applications. The following are the main topics of the study. First, the gate oxide of MOSFETs has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses with CAFM. The CAFM explicitly shows that while the degradation induced along the channel by a negative BTI stress is homogeneous, after a CHC stress different degradation levels can be distinguished, being higher close to source and drain. Second, strained MOSFETs with SiGe at the source/drain regions and different channel lengths have been studied, before and after CHC and NBTI stresses. The results show that although strained devices have a larger mobility, they are more sensitive to CHC and NBTI stresses. This effect has been observed to be larger in short channel devices. In CHC stressed devices, the higher susceptibility of strained MOSFETs to the stress has been related to a larger density of defects close to the diffusions, as suggested by CAFM data. Third, a CAFM has been used to study individual leaky spots at the nanoscale and at different temperatures on as-grown SiON layers. Switching between different conduction states have been measured in the form of Random Telegraph Noise during Constant Voltage Tests, which has been related to the trapping/detrapping of single charges in the defects present in the dielectric. The measurement of current maps at different Temperatures suggests that the detected leaky sites correspond to defects, whose activation depends on Temperature and that are randomly distributed in the gate area. Fourth, conductive filaments (CFs) in Ni/HfO2/Si resistive switching structures have been analyzed at the nanoscale by means of Conductive Atomic Force Microscopy (CAFM). Differences in the CF conductivity were measured depending on the resistive state of the device. Moreover, for both resistance states, non-homogeneous conduction across the CF area is observed, in agreement with a tree-shaped CF. Finally, the electrical properties and variability of capacitive MIS structures with graphene as interfacial layer between the HfO2 dielectric and the top electrode (MGIS devices), have been studied at device level and at the nanoscale. Their feasibility as RRAM devices was also evaluated. It was observed that, when graphene is present as an intercalated layer, several resistive switching cycles can be measured meanwhile the standard MIS structures cannot be switched. CAFM analysis showed that the graphene layer prevents the complete structural damage of the material during a forming process, confirming the protective role of graphene in a MGIS structure.
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Darbandy, Ghader. "Compact modeling of gate tunneling leakage current in advanced nanoscale soi mosfets." Doctoral thesis, Universitat Rovira i Virgili, 2012. http://hdl.handle.net/10803/97215.
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En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos.
Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral.
Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales.
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Weidemann, Michaela Patricia. "Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets." Doctoral thesis, Universitat Rovira i Virgili, 2011. http://hdl.handle.net/10803/52800.
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In this thesis the pinch-off behavior in nanoscale Multi-Gate MOSFETs was reviewed and with compact models described. For this a 2D approach with Schwarz-Christoffel conformal mapping technique was used. A model to calculate the current in single gate MOSFETs was derived and compared to device simulations from TCAD Sentaurus down to 50nm. For the DoubleGate MOSFET a new way to define the saturation point was found. A fully 2D closed-form model to locate this point was created. It was also found that with quantum mechanics effects a pinch-off point can occur and can be described with the same model. Furthermore the model was extended to describe the coupled pinch-off points in an asymmetrical biased DoubleGate MOSET with an even an odd mode. Also the saturation point behavior in FinFETs was examinated.
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Akturk, Akin. "Thermal and performance modeling of nanoscale MOSFETS, carbon nanotube devices and integrated circuits." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/3726.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2006.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Towie, Ewan Alexander. "Extended models of Coulomb scattering for the Monte Carlo simulation of nanoscale silicon MOSFETs." Thesis, University of Glasgow, 2010. http://theses.gla.ac.uk/1900/.
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The International Technology Roadmap for Semiconductors (ITRS) specifies that MOSFET logic devices are to be scaled to sub-10nm dimensions by the year 2020, with 32nm bulk devices ready for production and double-gate FinFET devices demonstrated down to 5nm channel lengths. Future device generations are expected to have lower channel doping in order to reduce variability in devices due to the discrete nature of the channel dopants. Accompanying the reduced channel doping is a corresponding increase in the screening length, which is even now comparable with the channel length. Under such conditions, Coulomb scattering mechanisms become increasingly complex as the scattering potential interacts with a larger proportion of the device. Ionized impurity scattering within the channel is known to be an important Coulombic scattering mechanism within MOSFETs. Those channel impurities located close to the heavily doped source and drain or both, will induce a polarisation charge within the source and drain. These polarisation charge effects are shown in this work to increase the net screening of the channel impurities, due to the inclusion of remote screening effects, and significantly decrease the scattering rate associated with ionized impurity scattering. Remote screening can potentially reduce the control by ionized channel impurities over channel transport properties, leading to an increased sub-threshold current. A potential model has been obtained that is based on an exact solution of Poisson’s equation for an ionized impurity located close to one or both of these highly doped contact regions. The model shows that remote screening effects are evident within a few channel screening lengths of the highly doped contact regions. The resultant scattering model developed from this potential, which is based on the Born approximation, is implemented within a Monte Carlo simulator and is applied to MOSFET device simulation. The newly developed ionized impurity scattering model, which allows for remote screening, is applied in the simulation of two representative MOSFET devices: the first device being a bulk MOSFET device developed for the 32nm technology generation; the second device is an Ultra-Thin-Body Double Gate (UTB DG) MOSFET developed for the forthcoming 22nm technology generation. Thorough investigative simulations show that for both the bulk MOSFET and the UTB DG MOSFET, that remote screening of channel impurities in these devices is not a controlling effect. These results prove that the current model for ionized impurity scattering employed in Monte Carlo simulations is sufficient to model devices scaled to at least the 22nm technology node, predicted to be in production in the year 2012.
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Alsibiani, Sameer Ali. "MODELING QUANTUM AND COULOMB EFFECTS IN NANOSCALE ENHANCEMENT-MODE TRI-GATE III-V MOSFETs." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/dissertations/1005.
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The limited benefits of strain engineering in extremely scaled silicon devices and a lack of demonstrated gain in performance at the product level in nanowires, nanotubes, graphene, and other exotic channel materials give good reason to continue semiconductor device scaling using high-transport III-V (such as InGaAs and InAsSb) channel materials beyond the year 2020. Novel process techniques, such as ALD, layer transfer, high-k dielectrics, and metal gates are now being used to explore these MOSFETs. III-V materials are also being investigated for possible use in quantum-mechanical devices (such as tunnel transistors), in spin-FET devices, and in qubits and memory cells. However, there are several challenges (such as, low ION/IOFF ratio) associated with III-V MOSFETs that prohibit their use in high- performance and low-power logic applications. To address some of these challenges, in this work, we investigate the performance of tri-gate III-V FETs (with 18nm and 9nm channel lengths) as compared to the single-gate counterparts, and show how quantum size-quantization and random dopant fluctuations (RDF) affect the tri-gate FET characteristics and how to curb these issues. For this purpose, a 3-D fully atomistic quantum-corrected Monte Carlo device simulator has been integrated and used in this work. The size-quantiza¬tion effects have been accounted for via a param¬eter-free effec¬tive potential scheme and benchmarked against the NEGF approach in the ballistic limit. To study the RDF effects and treat full Coulomb (electron-ion and electron-electron) interactions in the real-space and beyond the Poisson picture, the simulator implements a corrected Coulomb electron dynamics (QC-ED) approach. The essential bandstructure and scattering parameters (bandgap, effective masses, and the density-of-states) have been computed using a 20-band nearest-neighbour sp3d5s* tight-binding scheme. Among various III-V materials studied in this work (such as GaAs, GaSb, InAs, InSb, and InAsSb), InAs0.7Sb0.3, when used with appropriately engineered gate metal workfunction, was found to deliver the largest ION/IOFF ratio. As for the gate oxide, per the recipe of several experimental groups, to overcome the direct tunnel leakage current that accrues with using oxide thicknesses less than 2nm, SiO2 has been replaced with HfO2. From the simulation results, ION with HfO2 was found to be approximately two times higher than that with SiO2. For 18-nm channel length, the trigate architecture, as compared to the single-gate counterpart, offered better sub-threshold swing, higher (~2×) ON current, and reduced off-current at VDS = 0.5V. Of the various scattering mechanisms considered in the simulations, surface roughness was found to be most critical, which degraded the drive current by almost 34% and 22% in the single-gate and trigate devices, respectively. However, the effect of surface roughness diminishes drastically as the channel length is scaled down to 9 nm. On the flip side, small effective masses as observed in these material systems, although preferred for high mobility and injection velocity, results in a significant reduction in inversion layer charge. Additionally, small effective mass, especially in reduced dimensionality (nanowire) structures, leads to strong quantum mechanical effects and further degradation in the drive current. With regard to the intrinsic parameter fluctuation, it was found that, although both the planer and the tri-gate transistors experience some fluc¬tuation in threshold voltage due to randomness in the chan¬nel region, this deviation is smaller in the trigate architecture. Finally, the random dopant fluctuation (RDF) effect was found to be weaker in a 9-nm channel device than the 18-nm counterpart.
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Chowdhury, Murshed M. "Physical analysis, modeling, and design of nanoscale double-gate MOSFETs with gate-source/drain underlap." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015675.
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Nayfeh, Hasan M. (Hasan Munir) 1974. "Investigation of the electron transport and electrostatics of nanoscale strained Si/Si/Ge heterostructure MOSFETs." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/7998.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Includes bibliographical references (p. 125-138).<br>This thesis presents work aimed at investigating the possible benefit of strained-Si/SiGe heterostructure MOSFETs designed for nanoscale (sub-50-nm) gate lengths with the aid of device fabrication and electrical measurements combined with computer simulation. MOSFET devices fabricated on bulk-Si material are scaled in order to achieve gains in performance and integration. However, as device dimensions continue to scale, physical constraints are being reached that may limit continued scaling and/or the gains in performance from scaling. In order to continue the benefits of scaling, a possible solution is to change to a strained-Si/SiGe material system where enhanced electron mobility of 1.7-2X has been demonstrated for long-channel n-type devices. The electron mobility enhancement observed for long channel length devices may not be the same for devices with nanoscale gate length. In particular, increased channel doping, which is required to control short-channel effects can result in degraded transport characteristics. In this work, the impact of high channel doping on mobility enhancements in strained-Si n-MOSFETs is investigated experimentally. Increased channel doping will increase Coulomb scattering interactions increasing its influence on the overall mobility. Electron transport models were calibrated using experimental data for both strained and un-strained Si devices for various channel doping concentrations. The transport models were then used to investigate, by computer simulation, the performance enhancement of nanoscale strained Si devices for equivalent off-current.<br>by Hasan M. Nayfeh.<br>Ph.D.
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Laha, Soumyasanta. "Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.
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Gangadharan, Divya. "Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226530654.
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Børli, Håkon. "Modeling of Drain Current and Intrinsic Capacitances in Nanoscale Double-Gate and Gate-All-Around MOSFETs." Doctoral thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-4997.
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Shah, Nirav. "Stress modeling of nanoscale MOSFET." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0012221.
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SONI, HARSHIT. "DESIGN AND STUDY OF NANOSCALE TRENCHED GATE MOSFET." Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18379.
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This Project presents T-CAD simulation of buffered trench gate MOSFET (BTG-MOSFET),
and GaN buffered trench gate MOSFET (GaN-BTG MOSFET). The electrical attributes of
the devices are contrasted with conventional trench gate MOSFET (CTG-MOSFET). A
comparative study between various performance factors, for example, electric field, electron
velocity, electron mobility, the threshold voltage (Vth), and sub-threshold swing (SS) of the
devices has been performed. Results uncover a 43.85% improvement in SS and 9.83%
decrement in Vth for GaN-BTG-MOSFET. Further in this report, GaN-BTG-MOSFET’s
parameters are concentrated with variation in channel length, Effective Oxide thickness (tox),
and Doping concentration. Thermal reliability of GaN- BTG-MOSFET for application in
Integrated Circuits (ICs) at high temperatures (300K to 600 K) is examined. An intensive
near examination of electrical characteristics GaN-BTG-MOSFET has been carried out.
GaN-BTG MOSFET acts as a promising structure for further downsizing of the trenched gate
MOSFET and guarantees better performance for sub-micrometer MOSFET.
Thermal reliability of GaN-BTG-MOSFET for application in Integrated Circuits
(ICs) at high temperatures (300K to 600K). An intensive relative investigation of electrical
characteristics, for example, transconductance, transfer characteristics, leakage current, and
the electric field of the designed devices have been performed using the TCAD Atlas tool. A
detailed discussion is introduced on the thermal stability of the device at high temperatures
(300-600K). Report additionally presents the performance factors, for example, On-
Resistance (Ron), leakage current, and threshold voltage (Vth). Results recommend that the
introduction of GaN instead of silicon in a trenched gate structure not just improves the
device’s performance at room temperature (300K) yet additionally enhances the thermal
stability of the device. The performance of GaN-BTG-MOSFET at high temperatures when
contrasted with CTG MOSFET suggests that it tends to be utilized in ICs and shows
preferred thermal stability than silicon-based devices.
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Hussin, Razaidi. "A statistical study of time dependent reliability degradation of nanoscale MOSFET devices." Thesis, University of Glasgow, 2017. http://theses.gla.ac.uk/8052/.
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Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin.
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Couso, Fontanillo Carlos. "Analysis of impact of nanoscale defects on variability in mos structures." Doctoral thesis, Universitat Autònoma de Barcelona, 2018. http://hdl.handle.net/10803/650408.
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En los últimos años, la información y su análisis se han convertido en la piedra angular del crecimiento de nuestra sociedad, permitiendo la economía compartida, la globalización de productos y conocimientos, etc. Grandes compañías como Amazon, Facebook, Google... que son conscientes del potencial de estos recursos, están desarrollando infraestructuras con el fin de extraer toda la información posible sobre nuestro entorno (Internet de las cosas) o sobre nosotros mismos (redes sociales, teléfonos inteligentes ...), procesar esta información (Big Data Centers) y transmitirla rápidamente y entre cualquier parte del mundo. Sin embargo, la construcción de esta infraestructura requiere cada vez mejores dispositivos electrónicos, que no pueden desarrollarse utilizando las técnicas de escalado convencionales, porque las dimensiones de los dispositivos han alcanzado el rango atómico. Entre las diferentes fuentes de variabilidad, las trampas de interfaz (IT), las distribuciones de dopantes aleatorios (RDD) y la rugosidad de borde de línea (LER) se han identificado como las más destacadas. En consecuencia, la comunidad científica está explorando nuevas soluciones mediante sofisticadas técnicas experimentales o software de simulación, con el fin de superar los problemas de escalado. En este contexto, esta tesis estructurada en 7 capítulos, intentará contribuir a resolver este problema, analizando el impacto de las trampas de la interfaz y los defectos en la variabilidad de dispositivos.
Para presentar al lector los conceptos fundamentales aplicados en esta tesis, en el capítulo 1 se explica la teoría del transporte de carga a través de una unión Schottky y el transistor de efecto de campo semiconductor de metal-óxido (MOSFET). Además, también se presentan el concepto de variabilidad y diferentes fuentes de variabilidad.
En el segundo capítulo, se describen en detalle las técnicas de caracterización avanzada, como la microscopía de fuerza atómica conductiva (CAFM) para obtener información a nanoescala. Después de eso, se explica el simulador TCAD de dispositivos ATLAS y sus limitaciones, el cual es usado en esta tesis.
El tercer capítulo está dedicado a describir el impacto de los defectos (threading dislocations) en la conducción a través de un contacto Schottky. Aquí, diferentes mecanismos de conducción que están asociados a la conducción a través de áreas con TD y sin TD son analizados demostrando que el área con alta densidad de TD muestra mayor corriente de fuga.
En el capítulo cuatro, las técnicas de caracterización explicadas en el capítulo 2 se utilizan para obtener información a nanoescala. Para introducir esta información al simulador TCAD, se desarrollaron dos herramientas de software que son explicadas. Finalmente, la variabilidad de dispositivos MOSFET se estudia teniendo en cuenta los datos experimentales a nanoescala.
En el capítulo cinco, se analiza la influencia de las trampas de interfaz en la variabilidad del dispositivo. En primer lugar, se estudia el impacto de las cargas fijas discretas de la interfaz en dispositivos MOSFET de tecnología de 65 nm con diferentes dimensiones (variabilidad tiempo-cero), donde una desviación de la ley de Pelgrom se prueba mediante datos experimentales y de simulación TCAD. A continuación, el comportamiento dinámico de las trampas se analiza mediante las simulaciones transitorias TCAD, con el fin de estimar sus parámetros físicos de trampas a partir de parámetros empíricos.
El último capítulo de resultados está dedicado a estudiar el compromiso entre el rendimiento y el consumo de potencia en (Silicon On Insulator) SOI MOSFET cuando se opera en un voltaje cercano al umbral. Además, también se analiza el impacto de las trampas de interfaz en el rendimiento y el consumo de potencia del dispositivo.
Finalmente, en el último capítulo, se destacan las conclusiones más relevantes de esta tesis.<br>Over the last years, the information and its analysis have become in the corner stone of growth of our society allowing the sharing economy, globalization of products and knowledge, block-chain technology etc. Huge companies such as: Amazon, Facebook, Google... which were aware of the potential of these resources, are developing vast infrastructures in order to extract as much information as possible about our environment (Internet of Things) or ourselves (social media, smart-phones...), process this information (Big Data Centers) and transmit it quickly all over the world. However, this challenge requires electronic devices with higher performance and low power consumption, which cannot be developed using the conventional scaling techniques because the dimensions of devices have reached the atomic range. In this range of dimensions, the impact of the discrete of matter and charge increases inevitably the variability of devices. Among different variability sources, Interface traps (IT), Random Dopant Distributions (RDD), Line Edge Roughness (LER) and Poly Gate Granularity (PGG) have been identified as the most prominent ones. Consequently, the scientific community is exploring new solutions such as, alternative device materials and/or structures, in order to overcome the different issues owing to the scaling. In this context, this thesis, which is structure in 7 chapters, will try to contribute to solve this problem, analyzing the impact of interface traps and defects on device variability.
In order to introduce to the reader, in chapter 1 the charge transport theory through a semiconductor and metal junction (Schottky contact) and the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device are explained. Besides, the concept of variability and different sources of variability are also presented.
In the second chapter, advanced characterization techniques, such as, Conductive Atomic Force Microscopy (CAFM) and Kelvin Prove Force Microscopy (KPFM) used to obtain nanoscale information are described in detail. After that, the TCAD device simulator called ATLAS is explained. Here, the models and their limitations to simulate the electronic devices are discussed.
Third chapter is devoted to describe the impact of threading dislocation (TD) defects on the conduction through a schottky contact formed by a III-V semiconductor material (InGaAs) and a metal. Here, different conduction mechanisms, Poole Frenkel (PF) and Thermionic Emission (TE), have been associated to the conduction through areas with TD and without TD, respectively, proving that III-V materials with high density of TD showing higher leakage current.
In chapter four, the development of a simulator called (NAnoscale MAp Simulator (NAMAS)) to generate automatically topography and density charge maps from inputs obtained from CAFM measurements (topography and current maps) of a given sample is explained. From the generated maps, the impact of the oxide thickness and the charge density fluctuations on MOSFET variability is studied.
In chapter five, the impact of interface traps in the gate oxide on device variability is analyzed. Firstly, the impact of interface discrete fixed charges on 65 nm technology MOSFET devices with different dimensions is studied (time-zero variability), where a deviation of Pelgrom's law is proved by experimental and TCAD simulation data. Next, the dynamic behavior of traps is analyzed by TCAD transient simulation in order to estimate their physical parameters of traps from empiric parameters.
Chapter six is devoted to study the performance and power consumption trade-off in Ultra-thin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FDSOI) MOSFET when it is operated in near-threshold voltage. Besides, the impact of traps in gate oxide / channel and in buried oxide / channel interfaces on the performance and power consumption of device is also analyzed.
Finally, the more relevant conclusions are highlighted.
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Borzdov, A. V., V. M. Borzdov, D. V. Pozdnyakov, and F. F. Komarov. "Influence of Impact Ionization Process on Current-Voltage Characteristics of Nanoscale Silicon n-Channel MOSFET." Thesis, Sumy State University, 2013. http://essuir.sumdu.edu.ua/handle/123456789/35371.
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The current-voltage characteristics of nanoscale silicon n-channel MOSFET with 50 nm channel length are calculated in the present study. Both the electron and hole transport are simulated by means of the en-semble Monte Carlo method. The importance of electron impact ionization process in the transistor chan-nel for drain biases higher than 1 V is shown.
When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35371
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Chou, Cha-Hon, and 周佳弘. "Matching Properties of Nanoscale MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/31045443999825508335.
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碩士<br>國立交通大學<br>電子工程系所<br>96<br>This thesis investigates the current mismatch and derives a physical model. First, we have discussed the back-gate bias control on subthreshold circuit mismatch. We have measured the MOSFETs operated in subthreshold region with different gate widths and lengths. These MOSFETs were characterized with back-gate reverse and forward biases. We have observed that the devices operating in subthreshold region exhibited larger mismatch than those in above-threshold region. The is due to the exponential dependence of current on gate and bulk voltages as well as process variations. In the case of back-gate reverse bias, we have found that current mismatch increases as the magnitude of back-gate reverse bias increases. On the other hand, with the supply of back-gate forward bias, the current mismatch decreases with increasing the back-gate forward bias. The improvement in match is due to the gated lateral bipolar action in low level injection. We have also statistically derived an analytical model that has successfully reproduced the mismatch data in weak inversion for different back-gate biases and different device dimensions. With this model, the current mismatch can be expressed as a function of the variations in process parameters. The extracted variations are shown to follow the inverse square root of the device area.
In the following work, we have used the results of extraction for different parameters. We also pay more attention to the threshold voltage fluctuation compared to different models. The substrate bias dependence of threshold voltage standard deviation was also discussed. On the other hand, we have found that drain voltage bias caused the effect of DIBL.
To reconfirm the reliability of our model, we have taken some parameters into account. In order to obtain the effective channel length, we have used the edge direct tunneling (EDT) model to gain the overlap length. On the other hand, the source/drain series resistance is also an important pole in our model. By incorporating the constant mobility criterion into the current equation under different bias conditions, the series resistance can be easily achieved.
In the beginning, we have discussed the devices operated in the subthreshold region. In the end, we have discussed the current mismatch in above-threshold regions and derived a physical model based on backscattering theory. Due to the backscattering theory, we have discussed the devices operated in saturation region. We have also derived a backscattering based mismatch model with key parameters, DIBL, threshold voltage, and backscattering coefficient. The effective channel length and series resistance were also taken into consideration to confirm the validity of the mismatch model. We have achieved that the backscattering coefficient mismatch model was feasible for our data. We have also successfully used the new mismatch model to reproduce the experimental current mismatch.
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Yi-Tang, Lin, and 林以唐. "Strained Silicon Physics in Nanoscale MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/44317602205044227873.
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碩士<br>國立交通大學<br>電子工程系所<br>96<br>In this work, by using the deformation potential theory for conduction band and the k•p framework (6 6 Luttinger Hamiltonian) for valence band, the strain-altered band structure (E-k relation), the strain-induced band edge shift, the constant energy surface, and the 2D energy contour have been calculated for various stress conditions on three conventional wafer orientations, (100), (110), and (111). Moreover, the influences of the additional transverse or normal strain have been examined as well.
Next, utilizing the calculated E-k relation, the conventional physical parameters including the quantization effective mass, the 2D DOS Effective mass, and 3D DOS effective mass have been also extracted under uniaxial and biaxial stress on (001) wafer. Then, using the DOS effective masses and strain-induced band edge shifts, the Fermi energy of bulk silicon can be determined as a function of stress and doping concentration. These parameters are significant in calculating the subband energy and carrier density in the channel inversion layer of MOSFETs. In addition, we also evaluated the intrinsic carrier density of bulk silicon under uniaxial and biaxial stress from zero to 3GPa.
Furthermore, we extended and modified the previously developed triangular potential approximation, a self-consistent method that takes the quantum confinement effect in the inversion layer and the conservation of electric flux at the SiO2/Si interface into consideration, for the unstrained MOSFETs to construct the band diagram and physical model for strained counterparts. The method has also been applied to both nMOSFETs and pMOSFETs with corresponding revisions of the physical model. In our model, the stresses for poly gate and channel are allowed to have different magnitude and type.
Finally, applying our model and the extracted physical parameters, we can calculate the interface electric field, subband energy, inversion carrier density, substrate band bending, etc., with various stress conditions, applied voltage and device parameters as inputs. Then, utilizing the WKB approximation, the transmission probability and gate direct tunneling current for various stress conditions can also be evaluated. The simulated results agree with the experimental data of the former works.
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Huang, Kuo-Chuan, and 黃國荃. "Nanoscale MOSFETs Channel Backscattering Theory and Experiment." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/24532089888759189473.
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碩士<br>國立交通大學<br>電子工程系<br>90<br>A simple channel backscattering theory of the silicon MOSFET is introduced. Current—voltage (I-V) characteristics are expressed in terms of scattering parameters rather than mobility. For long-channel transistors, the results reduce to conventional drift-diffusion theory, but they do apply to devices in which the channel length is comparable to or even shorter than the mean-free-path.
We perform temperature experiment (-40 oC to 25 oC and 25 oC to 75 oC) on MOSFETs down to 75-nm mask gate length and also build a temperature version of channel backscattering theory. In such way, we are able to extract backscattering parameter, which is expressed as a function of both gate length and drain voltage and is found to be independent of gate voltage. The resulting relation does find the origin in the framework of backscattering theory, and is very helpful in projecting performance limit of nanoscale MOSFETs. Comparisons with published values of backscattering coefficients are carried out as well.
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Chen, Rong-Ting, and 陳榮挺. "Nanoscale MOSFETs Channel kBT Layer Backscattering Experiment." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/08734823076136701217.
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碩士<br>國立交通大學<br>電子工程系所<br>93<br>Currently a widely recognized channel backscattering theory finds potential applications in the areas of nanoscale FETs. The theory prevails over the channel quasi-equilibrium layer, a critical zone near the thermal reservoir source. However, the role of the layer width, as well as its promising potentials, has not been fully explored yet. In this study, a series of experiments are conducted to decouple the channel backscattering coefficients in a 68-nm gate length bulk n-channel MOSFET into two distinct components: the quasi-equilibrium mean free path for backscattering and the width of the layer. The layer widths obtained from various temperatures are transformed into near-source channel conduction-band profiles for different gate voltages and different drain voltages. The strictly confirmed conduction-band profiles are of value in the areas of channel backscattering. They straightforwardly furnish guidelines not reported before, leading to a new compact model for the kBT layer width l: (i) l is a weak function of gate voltage in linear region; (ii) in saturation region l follows the amount of injected carriers while the drain voltage tends to shift the l versus gate voltage curve; and (iii) l �f (kBT/q)d with the power exponent d (�l 0.5) independent of temperature, gate voltage, and drain voltage. Experimental I-V characteristics are also reproduced as well.
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Wei, Sih-Yun, and 魏思勻. "Probing long-range Coulomb interactions in nanoscale MOSFETs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21372155625778236236.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>Electron mobility degradation is currently frequently encountered in highly scaled devices. This means that additional scattering mechanisms exist and will become profoundly important in the next-generation of devices. We have recently experimentally probed long-range Coulomb interactions due to plasmons in polysilicon gate of long-channel (1 m) MOSFETs. In this paper, we further probe those due to plasmons in the highly-doped source and drain. Test vehicles include four more samples from the same manufacturing process but with small channel lengths (down to 33 nm). I-V’s of devices are measured at two drain voltages of 0.05 and 1 V, in a temperature range of 292 to 380 K. Inverse modeling technique is applied to furnish calibrated doping profiles. The inversion-layer electron effective mobility is thereby extracted, showing a decreasing trend with decreasing channel length. Such differences reflect more additional scatterers in the shorter devices. Mobility components limited by these additional scatterers are assessed using Matthiessen’s rule. Extracted temperature dependencies reveal that the strength of source/drain plasmons increases with decreasing channel length. Corroborative evidence is given as well.
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Agarwal, Pramod Kumar. "Modeling & Simulation of High Performance Nanoscale MOSFETs." Thesis, 2013. http://ethesis.nitrkl.ac.in/5311/1/211EE1323.pdf.
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Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications.A new type of transistor without junctions and no doping concentration gradients is analysed and demonstrated. These device structures address the challenge of short channel effects (SCEs) resulting with scaling of transistor dimensions and higher performance for deep submicron VLSI integration. Recent experimental studies have invigorated interest in partially depleted (PD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. SELBOX structure offer an alternative way of suppressing kink effect and self heating effects in PD-SOI devices with a proper selection of oxide gap length. Also in order to mitigate the difficulties in fabrication of ultra thin devices for the semiconductor industry, resulting from scaling of gate length in MOSFET, a new device structure called junctionless (JL) transistors have recently been reported as an alternative device. In conclusion, extensive numerical simulation studies were used to explore and compare the electrical characteristics of SELBOX SOI MOSFET with a conventional single-material gate (SMG) bulk MOSFET. The proposed work investigates the DC and AC characteristics of the junctionless transistors. Also the performance analysis of JL transistors is compared and presented with the conventional DG MOSFET structure. The results presented in this work are expected to provide incentive for further experimental exploration.
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Si-HuaChen and 陳思樺. "NEGF Simulation of Nanoscale MOSFETs with Anisotropic Si Permittivity." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/brm6j2.
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碩士<br>國立成功大學<br>奈米積體電路工程碩士學位學程<br>107<br>CMOS scaling has led to several issues that are necessary to be investigated further. In this thesis, the transport behavior of electrons in a nanoscale double-gate (DG) MOSFET is modeled by solving Schrödinger equation in non-equilibrium Green’s function (NEGF) formalism which is solved self-consistently with the Poisson equation to obtain the potential profile, electron density, transmission coefficient and thus, the drain current versus gate voltage (I_DS-V_GS) curves.
In addition to quantum effects which have been taken into account in the transport equation, the reduction of permittivity in the surface region and the anisotropic permittivity that influence the electrical properties are investigated and their influences on the electrical characteristics of MOSFETs are discussed.
It is shown that the reduction of permittivity in the surface region slightly improves the subthreshold swing and slightly increases the threshold voltage due to the increase of the potential barrier for electrons in the transport direction. This suggests the better immunity to SCEs for materials of the channel with smaller permittivity. In the case of anisotropic permittivity, the subthreshold swing degrades and the off-leakage current becomes higher as the permittivity in the confinement direction becomes smaller due to the decrease of the potential barrier in the transport direction. This suggests the better immunity to SCEs for materials of the channel with larger permittivity in the confinement direction.
For long channel devices, the variation in permittivity barely changes the potential barrier in the transport direction. Therefore, the variation in the permittivity has neglecting effects on the (I_DS-V_GS) characteristic.
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Liu, Keng-ming. "Schrödinger equation Monte Carlo-3D for simulation of nanoscale MOSFETs." 2008. http://hdl.handle.net/2152/17934.
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A new quantum transport simulator -- Schrödinger Equation Monte Carlo in Three Dimensions (SEMC-3D) -- has been developed for simulating the carrier transport in nanoscale 3D MOSFET geometries. SEMC-3D self-consistently solves: (1) the 1D quantum transport equations derived from the SEMC method with open boundary conditions and rigorous treatment of various scattering processes including phonon and surface roughness scattering, (2) the 2D Schrödinger equations of the device cross sections with close boundary conditions to obtain the spatially varying subband structure along the conduction channel, and (3) the 3D Poisson equation of the whole device. Therefore, SEMC-3D can provide a physically accurate and electrostatically selfconsistent approach to the quantum transport in the subbands of 3D nanoscale MOSFETs. SEMC-3D has been used to simulate Si nanowire (NW) nMOSFETs to both demonstrate the capabilities of SEMC-3D, itself, and to provide new insight into transport phenomena in nanoscale MOSFETs, particularly with regards to interplay among scattering, quantum confinement and transport, and strain.<br>text
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Chan, Kuo-Chih, and 詹國志. "Analysis of Temperature Dependences of Impact Ionization for Nanoscale MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/99184580073106680101.
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碩士<br>國立宜蘭大學<br>電子工程學系碩士班<br>96<br>This thesis presents the temperature dependence of impact ionization in nanoscale MOSFETs via analytical study and numerical simulation. As the devices continue to scale, the electric field increases and the electrons in the channel more likely get excited, resulting in impact ionization. As a result, the excessive electron and hole pairs are created. In this paper, we focus on the temperature dependence of such effect, especially for highly scaled devices, using numerical simulation with Chynoweth and Valdinoci models. The temperature dependence of impact ionization is shown to be opposite to the result from conventional carrier transport when energy balance is accounted for. Our results could provide useful implications for advanced device scaling.
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Tsai, Ming-Fu, and 蔡明甫. "Design and Characterization of SRAM in Nanoscale Multi-Gate MOSFETs." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/55623769640043718316.
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碩士<br>國立交通大學<br>電子研究所<br>101<br>This thesis contains two topics and is organized as follows. First, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Second, a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs is proposed in TCAD platform. The simple description of above two topics is arranged in the second and third paragraph separately.
In the first work, extensive simulations suggest the proposed CLSAs are robust against random offset errors. The proposed structures feature significant offset suppression capabilities with σoffset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.
In the second study in NW MOSFETs, the proposed approach predicts the device characteristic and variations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.
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Lu, Li-Fang, and 呂立方. "Nanoscale MOSFETs Channel Backscattering: Monte Carlo Simulation and Physical Model." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/82774370880546621535.
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碩士<br>國立交通大學<br>電子工程系所<br>96<br>Through the scattering matrix approach, the backscattering coefficient is derived and it is verified by Monte Carlo simulations. Two important parameters, kBT layer's width and mean-free-path, constituting the channel backscattering have been taken into account. A parabolic barrier oriented compact model has been physically derived for kBT layer's width. The validity of this compact model has been corroborated experimentally and by Monte Carlo simulation results. As for mean-free-path, the carrier heating as the origin of reduced mean-free-path is inferred on the basis of the simulated carrier velocity distribution at the injection point. Strikingly, for the parabolic potential case, the mean-free-paths remain consistent: apparent mean-free-path = mean-free-path. This indicates the absence or weakening of the carrier heating in the layer of interest, valid only for a parabolic potential barrier
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Lin, Tsung-Ching, and 林宗慶. "Experimental Determination of the Ballistic Transport Characteristics of Nanoscale Trigate MOSFETs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/05644566406298849227.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>As channel length continues scaling down below 100 nm, the short channel effects, such as Vth variation and DIBL leakage, become increasingly important. To overcome these challenges, high-k gate dielectric layers, silicided source/drain, super halo doping, and 3D structures are the most possible solutions. Among all these new structures, the trigate MOSFET devices exhibit excellent I-V characteristics and manufacturing ability, which is believed to be able to continue Moore’s law down to 10 nm and beyond.
The ballistic theory has been extended to explore the transport efficiency in quasi-ballistic regime. In this thesis, we explicitly clarified quasi-ballistic transport theory and the physical meanings of each transport parameters, such as Bsat and vinj. Then, we outlined the advance devices used in this study and demonstrated the performance of tested devices. The results show that trigate CMOS devices are immune to short channel effects down to 40 nm and are superior to its planar ones. Furthermore, we applied Velocity Saturation Model (VSM) to trigate devices to examine the ballistic transport parameters experimentally. By using VSM to analyze ballistic transport property, we found that trigate devices show high injection velocity, which results from double gate operation that boosts the mobility of trigate device. On the other hand, planar device shows higher ballistic efficiency, which is attributed to stronger charge sharing ability of its drain. Finally, we examined the transport property of trigate devices under body bias conditions. It reveals that even when fin width is about 50nm, body bias is still effective in tuning the threshold voltage and transport property.
Several salient results are achieved: (1) we have successfully used VSM to extract ballistic transport parameters experimentally; (2) the injection velocity shows a more important role in the device overall performance, and it is limited by scatterings near the drain side; and (3) the body bias is effective in tuning Vth and affects transport property. When forward body bias is applied, the inversion charge centroid will be pushed away from the interface between oxide and channel, resulting in high mobility. These results will be helpful and valuable for the design of the next generation trigate CMOS devices beyond 20 nm.
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Yadav, Manoj Kumar. "Analytical Modeling of Nanoscale 4H-SiC MOSFETs for High Power Applications." Thesis, 2016. http://ethesis.nitrkl.ac.in/8231/1/2016_MT_214EE1223_Analytical.pdf.
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Threshold voltage instability was investigated for 4H-SiC MOSFETs with SiO2, Si3N4 and HFO2 gate oxides. Threshold voltage changes observed in the drain current Vs. gate voltage (ID-VG) characteristics was determined using various gate voltage sweeps at room temperature. Three types of MOSFETs show different instability characteristics. Depending on gate voltage, many difficulties come up with 4H-SiC MOSFETs, such as low mobility and poor reliability. The characteristics like channel potential, field distribution and the threshold voltage of the proposed models of MOSFETs, 4H-SiC and SOI-4H-SiC were compared with simulator results to validate the models. Short channel effects (SCEs) were also investigated and compared with the existing nanoscale silicon MOSFETs The surface potential model is calculated by using the two-dimensional Poisson equation. The specification of the model are examined by several MOSFET parameters such as body doping concentration, metal gate work function, silicon carbide layer thickness, thickness of metal gate oxide layer, buried oxide thickness, drain to source voltage, and gate to source voltage. The outcomes of modeling and simulation of 4H-SiC MOSFETs model show that the proposed models can reduce short channel effects more than the Silicon MOSFETs. Proposed models highly reduces the drain-induced-barrier-lowering (DIBL) to meet the performance fullfilmant in Nano electronic applications when compared to silicon MOSFETs. Establishing the results, we have noticed that this model can be utilized as a useful tool for the characterization and design of high-efficiency 4H-SiC nanoscale MOSFETs. By matching the two-dimensional device simulation results with analytical modeling, the validity of the recommended models are proven.
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Lai, Shiou-Yi, and 賴修翊. "Modeling the Switching Magnitude of Random Telegraph Signals in Subthreshold Nanoscale MOSFETs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/34889201893875831058.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>With the technology generation down-scaling trend of
metal-oxide-semiconductor field effect transistors (MOSFETs), random telegraph signals (RTS) turn into an essential issue in device development. These signals take place through the carrier capture-emission process via a defect at the silicon/oxide interface or in the oxide layer. The capture-emission behavior of the defect causes the witching of source/drain current between high and low level. The switching magnitude may have negative impact on device performance of MOSFETs, and it can be displayed by calculating ΔId/Id as an index to analyze the characteristic of RTS.
In the experiment, it is not easy to observe the two-level switching magnitude of source/drain current. Besides, it usually appears in terms of more than two levels. Multiple levels would make the issue more complicated, which is not the major issue in this thesis. Most important of
all, dealing with all the parameters, which may affect RTS phenomenon, such as the substrate doping concentration, the device size, and the IV position of defect into control through experiment, are quite difficult. However, we can easily modify these parameters by building all kinds of
device characteristics in TCAD simulations. A conventional RTS magnitude model was derived in flat potential
distribution across the whole channel, but now fails in subthreshold region. The reason is that the potential barrier is highly localized in the middle of channel under a small gate voltage. In this thesis, we establish a new model taking the local barrier into account, which is shown as
conduction band energy along channel length and channel width direction. To obtain RTS index ΔId/Id, we run two cases in device simulations: one of a defect at the silicon/oxide interface or in the oxide layer, and one of
no defect. Then, corresponding drain terminal currents are simulated to determine ΔId/Id.
In our previous work, the switching magnitudes of source/drain current measured in both subthreshold and above-threshold regions were separately transformed into the effective size of the affected region and the effective area of the percolation path. In this work, many of well-known RTS models are considered, by taking into account the defect
position factor ηs1 and the random discrete doping coefficient (percolation effect) ηs2 and ηc.
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Teng, An-Shun, and 鄧安舜. "The Carrier Transport and Channel Backscattering Characteristics of Nanoscale Schottky-Barrier MOSFETs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/27151385660472349230.
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碩士<br>國立交通大學<br>電子工程系所<br>98<br>In advanced VLSI devices, a lot of new structures have been brought up for enhancing drain current such as strained-Si channel, high-κ dielectric, metal gate and metal source/drain. In the nanoscale channel length, the channel backscattering theory has been applied to predict the scaling-limitations of these structures successfully. Nowadays, the Schottky-barrier MOSFETs have aroused much more attention because some optimized processes become feasible. Hence, the carrier transport mechanism of Schottky-barrier MOSFETs from source to drain becomes the most popular topic in researches.
In the thesis, first, we will focus on finding the effective Schottky-barrier height from the activation energy method. We can describe the effective Schottky-barrier height versus carrier transport mechanism relationship from this method. A negative effective Schottky-barrier height is found in the ON-state of the Schottky-barrier MOSFETs so that the channel backscattering theory can be used for extracting the carrier ballistic rate. In the past, the ballistic coefficient is extracted by temperature dependent method. However, the major carrier transport mechanism in the Schottky-barrier MOSFET is field emission, the temperature dependent method is failed. We practiced the effective ballistic mobility which is from mobility degradation in short channel devices. We may directly obtain the ballistic coefficient and thermal injection velocity in the linear region. Then, we derive the carrier average velocity versus thermal injection velocity relations in ON-state. By the two velocity components, the ballistic probability of the Schottky-barrier MOSFET can be extracted easily.
Based on the results of this work, it was concluded that: (1) the backscattering theory is practicable from the negatively effective Schottky-barrier height, (2) the backscattering probability in the source side of Schottky-barrier is smaller than that in the conventional MOSFETs due to non-local tunneling, (3) the strained technology affects the backscattering coefficient lightly but it affects the thermal injection velocity drastically, (4) the drift-diffusion model is still workable in quasi-ballistic region. Thus, Schottky-barrier MOSFET with dopant segregation implantation and CESL(Contact-Etched Stoped Layer) can enhance the ballistic rate and thermal injection velocity that produced high speed operation in Schottky-barrier MOSFETs.
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Orouji, Ali Asghar. "Modelling and simulation of novel multigate nanoscale SOI mosfets and polysilicon TFTs." Thesis, 2006. http://localhost:8080/xmlui/handle/12345678/5574.
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Lee, Wei, and 李維. "Experimental Study of Carrier Transport and Important Device Parameters for Nanoscale Si MOSFETs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/35790524874817411141.
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博士<br>國立交通大學<br>電子工程系所<br>97<br>This thesis provides a comparative study of carrier transport characteristics for multiple-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with and without the non-overlapped gate to source/drain structure. For the overlapped devices, we observed the Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the non-overlapped devices, however, we found insensitive temperature dependence for drain current in both subthreshold and inversion regimes. Our low-temperature measurements indicate that the inter-subband scattering is the dominant carrier transport mechanism for narrow overlapped multiple-gate SOI MOSFETs (MuGFETs). For the non-overlapped MuGFETs, the voltage-controlled potential barriers in the non-overlapped regions are crucial and may give rise to the conductance reduction and fluctuation.
Besides, we systematically present controlled single-electron effects in the non-overlapped MuGFETs with various gate length, fin width, gate bias and temperature. Our study indicates that using the non-overlapped gate to source/drain structure as an approach of the single-electron transistor (SET) in MOSFETs is promising. Combining the advantage of gate control and the constriction of high source/drain resistances, single-electron effects are further enhanced using the multiple-gate architecture. From the presented results, downsizing MuGFETs is needed for future room-temperature SET applications. Besides, the tunnel barriers and access resistances may need to be further optimized. Since single-electron effects can be achieved in state-of-the-art MOSFETs, it is beneficial to build SETs in low-power complementary metal-oxide-semiconductor (CMOS) circuits for the ultrahigh-density purpose.
In addition, we have assessed the validity, limitation, and application of experimental channel backscattering extraction. Our study indicates that the difficulty of the temperature-dependent method lies in accurate determination of the temperature sensitivity of low-field mobility (μ0), critical length (l) and thermal velocity (υtherm). Through our proposed self-consistent approach, channel backscattering can be extracted without assuming λ = (2kBTμ0/qυtherm), l = kBT length, μ0 = low-field mobility, and the non-degenerate limit. Using the generalized temperature-dependent method, we have clarified that channel backscattering of nanoscale p-type MOSFETs can be reduced by the uniaxially compressive strain. Moreover, we have experimentally extracted the electrostatic potential of the source-channel junction barrier with accurate strain and gate voltage dependence. We have demonstrated that the strain technology can improve the drain current variation as well as the mismatch properties through the enhanced ballistic efficiency.
Moreover, we have investigated anomalous inversion capacitance-voltage (C−V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C−V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. Our reconstructed C−V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method, and agree well with the NCSU CVC (C−V analysis software developed by the North Carolina State University) simulation results. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.
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Mohapatra, Sushanta Kumar. "Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications." Thesis, 2015. http://ethesis.nitrkl.ac.in/7434/1/2015_SKMohapatra_PhD-511EE306.pdf.
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Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate
leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate
work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications.
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Kuo, Jyun-Yan Jack, and 郭俊延. "Investigation and Analysis of Drain Current Mismatch and Low Frequency Noise for Nanoscale MOSFETs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/38664025478182080568.
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博士<br>國立交通大學<br>電子研究所<br>100<br>This dissertation investigates and analyzes the drain current mismatch and low frequency noise properties for nanoscale MOSFETs. Through a comparison of the input-referred noise and the trap density of the gate dielectric/semiconductor interface between co-processed strained and unstrained pMOSFETs, it is found that the tunneling attenuation length λ for channel carriers penetrating into the gate dielectric is reduced by uniaxial strain. This reduced λ may result in smaller carrier-number-fluctuations origin low frequency noise, which represents an intrinsic advantage of low frequency noise performance stemming from process-induced strain. On the other hand, it is found that the normalized drain current noise of the strained device in the high gate overdrive (Vgst) regime is larger than its control counterpart. In addition, the enhanced carrier-mobility-fluctuations origin 1/f noise for the strained device in the high |Vgst| regime indicates that the carrier mobility in the strained device is more phonon-limited, which represents an intrinsic strain effect on the low frequency noise.
Impact of uniaxial strain on drain current mismatch and its temperature dependence under various operation conditions are investigated systematically. With the adoption of uniaxial compressive strained silicon, drain current mismatch for the strained device in the low |Vgst| regime is enhanced while the threshold voltage mismatch of the strained device is nearly identical to that of the control one. The increased drain current mismatch for the strained device can be attributed to the enhanced gm/Id. In the high |Vgst| linear region, the smaller drain current mismatch for the strained device results from its smaller current factor mismatch σ(Δβ)/β. In the high |Vgst| saturation regime, the improvement in drain current mismatch for the strained device is further enhanced because of the strain-reduced electric field for velocity saturation (Esat).
Regarding the temperature dependence of the device mismatching properties, our result indicates that the drain current mismatch versus temperature trend for the strained device is different from the unstrained one. In the high |Vgst| linear regime, the compressively-strained device shows smaller increment in drain current mismatch than the unstrained counterpart as temperature decreases. In the high |Vgst| saturation region, opposite to the unstrained case, the drain current mismatch of the compressively-strained device decreases with temperature. The underlying mechanism is the larger temperature sensitivity of carrier mobility for the strained device.
The mismatching properties in nanoscale MOSFETs with symmetric/asymmetric halo implant are also investigated. We show that the threshold voltage mismatch is mainly determined by the RDF in the halo-implanted region, and the threshold voltage mismatch for the asymmetric device is larger than that of the symmetric one.
Impact of self-heating on drain current mismatching properties for SOI devices are investigated. It is found that self-heating induces a feedback effect and reduces the drain current mismatch. A drain current mismatch model considering the self-heating induced feedback effect is proposed. The accuracy of the new model has been verified with experimental data. This effect needs to be considered when one-to-one comparisons between SOI and bulk devices regarding the variability are made. In addition, impact of source/drain series resistance on the drain current mismatch is investigated. The impact of source/drain series resistance on the drain current mismatch will become increasingly important for devices with scaled channel length.
Since subthreshold circuits are increasingly important for low power applications, subthreshold drain current mismatch modeling is crucial. To model the subthreshold drain current mismatch more physically and accurately, our study suggests the constant-current method instead of the maximum slope method should be used for the determination of threshold voltage. Our study indicates that the subthreshold swing mismatch is important for devices with small geometries. It is also found that the correlation between the threshold voltage mismatch and the subthreshold swing mismatch needs to be considered in the subthreshold drain current mismatch modeling especially for long channel devices.
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Yau, Kenneth Hoi Kan. "On the Metrology of Nanoscale Silicon Transistors above 100 GHz." Thesis, 2011. http://hdl.handle.net/1807/31984.
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This thesis presents the theoretical and experimental framework for the development of accurate on-wafer S-parameter and noise parameter measurements of silicon devices in the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and validated up to 170 GHz. In the absence of accurate foundry models in this frequency range, the experimental findings of this thesis have been employed by other graduate students to design the first noise and input impedance matched W- and D-band low-noise amplifiers in nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter characterization techniques and of the new Y-parameter based noise model have been used by STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band.
In the first half of the thesis, theoretical analysis indicates that, for current silicon devices, distributive effects in test structure parasitics will become significant only beyond 300 GHz. This conclusion is supported by experiments which compare the lumped-element based open-short and the transmission line based split-thru de-embedding techniques to the multiline thru-reflect-line (TRL) network analyzer calibration algorithm.
Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for microstrip transmission lines with metal ground plane placed above the silicon substrate, the line capacitance per unit length remains a weak function of frequency. Based on this observation, the multiline TRL algorithm has been modified to include a dummy short de-embedding structure. This allowed for the first time to perform single step calibration and de-embedding of silicon devices using on-silicon calibration standards. The usefulness of the proposed method was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOSFET model parameters, including transcondutance delay, tau, gate resistance, source resistance, drain-source capacitance, and channel resistance, Ri.
Building on the small-signal characterization technique developed in the first half, a new Y-parameter based noise model for SiGe HBTs, that includes the correlation between the base and collector shot noise currents, is proposed in the second half of the thesis along with a method to extract the noise transit time parameter. With this model, the high frequency noise parameters of a SiGe HBT can be calculated from the measured Y-parameters, without requiring any noise figure measurements.
Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter measurement systems were designed and measured in the W- and D-bands. The systems enable millimetre-wave noise parameter measurements with the multi-impedance method by integrating the impedance tuner and an entire millimetre-wave noise receiver on the same die as the device-under-test. Good agreement was obtained between the noise parameters calculated from the Y-parameter measurements and those obtained from direct noise figure measurements with the integrated systems. The results indicate that the minimum noise figure of state-of-the-art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable for a variety of commercial products in this frequency range.
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Chuang, Li-Yang, and 莊禮陽. "Modeling the Statistical Variability of Random Telegraph Signals Induced Threshold Voltage Shifts in Nanoscale MOSFETs and FinFETs." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/vyav52.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>The trapping and de-trapping of single electron at the Si/SiO2 interface of planar bulk metal -oxide-semiconductor field effect transistors (MOSFETs) and fin-shape field effect transistors (FinFETs), which is called random telegraph signals (RTSs), has been a well-known issue for the reliability of the nanoscale device. In this work, we proposed a novel graphical method to enable the analysis of the MOSFET or FinFET threshold voltage shift Vth induced by RTS-trap in a percolative channel. First, according to the Mueller-Schulz’s percolation theory and through the help of 3D-technology aided design (TCAD) simulation with no percolation, both a minimum Vth and a critical curve in a mloc-loc plot are produced. Here, mloc and loc are the mean and standard deviation, respectively, of a normal distribution. The critical mloc-loc curve divides the plot into the allowed region and the forbidden region. Then, Vth contours in the allowed region are graphically created. By comparing existing experimental or simulated Vth statistical distributions, we are able to extract paired mloc and loc which represent a particular percolation pattern. Furthermore, through 3D-TCAD simulation, we derive a computationally efficient model which can be applied for constructing the FinFET Vth statistical distribution in a percolation-free channel. Last but not least, bias and temperature instability (BTI) condition is added to RTSs discussion.
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KHALID, USMAN. "RELIABILITY ESTIMATION TECHNIQUES FOR NANOSCALE MOSFETS AND FINFETS CIRCUITS IN THE PRESENCE OF NOISE, VARIABILITY AND AGING." Doctoral thesis, 2016. http://hdl.handle.net/11573/935766.
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High yield, reliability, and increasing number of functions in single Integrated Circuit (IC) have been the continuing demand of the market for IC fabrication. However, the uninterrupted scaling of CMOS and FinFET technologies to nano-scale level leads to fallouts in reliability due to the variability of process parameters and the aging caused by Bias Temperature Instability (BTI). Such issues ultimately become responsible for a weakening of noise immunity in digital circuits which translate in higher logic error probability and higher average power consumption. Various types of failures take part in the degradation of circuit reliability when CMOS and FinFET technologies are scaling to nano meter regime. Failures such as input voltage signal fluctuations in presence of additive noise or crosstalk noise within the circuit topology, variations in process parameters of device itself and different aging mechanisms over the lifetime of circuit, can hugely detoriate the reliability of circuit.
In this thesis work, several novel modeling techniques such as analytical, semi-analytical and approximation, are introduced in order to quantify failure-probability for both combinational and sequential circuits, in the presence of input voltage noise in conjunction with process variations and aging. Furthermore, an analysis on the impact of noise-induced voltage pulses on the static power consumption of nano-CMOS circuits is implemented by using an approximation model scheme. Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This part of research work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and approximation approaches in comparison with SPICE Monte-Carlo verification approach.
Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. The prproposed semi-analytical scheme brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.
Furthermore, the assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis.
Last but not least research devoted to the occurrence of noise pulses on the input signals of idle digital cells has been typically associated to reliability issues, such as transient or permanent logic errors. The wide range of possible noise sources in nano-scale circuits, associated to the variability of process parameters, makes it interesting to explore the impact of random voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised by the noise. This part of the thesis proposes a simple yet effective model to characterize the shift in static energy consumption associated to input voltage pulses in logic cells. The characterization scheme allows a fast calculation of the statistical distribution of the energy shift in multi-cell circuits affected by random noise pulses and considering the impact of device statistical variability. The accuracy and effectiveness of the approach have been tested against SPICE simulation, reaching a four orders of magnitude speedup in run time. All of the above proposed techniques were verified against state of the art SPICE Monte Carlo Simulations and results in over 10E4 faster run time with respect to SPICE evaluation.
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Wang, Huan-Hsiang, and 王煥翔. "Modeling the Statistical Distribution of Random Telegraph Signals Magnitudes and Induced Threshold Voltage Shifts in Subthreshold Nanoscale MOSFETs." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/40247914553609396967.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>103<br>The trapping and detrapping of an electron at the SiO2/Si interface of metal-oxide-semiconductor field effect transistor (MOSFET), which is known as random telegraph signals (RTS), has been an important issue for the variability of the nanoscale device. Recently, 3D-technology aided design (TCAD) simulations have been widely used for RTS topics. The trap positions in the channel will have its corresponding ΔId/Id magnitude in the subthreshold region at a low drain voltage. There are two distinct ΔId/Id distributions: a headed one for the percolation-free channel and a tail one for the percolative channel. The tail distribution can be described by using a literature formula 〖∆I〗_d/I_d =(I_loc/I_d )^2, where Iloc is the local current around the trap. Our proposed model can reproduce headed distribution through few 3D-TCAD simulations on 35x35 nm2 channel to obtain the Id/Id for each trap position. The model is in closed form, and the key criteria are drawn from the model for the use of I_loc/I_d formula. Furthermore, the threshold voltage shift distributions can be transformed from the tail distributions, from subthreshold to inversion. The channel width effect can be included through applying the width effect into our headed distributions. Importantly, the use of the analytic model can overcome the disadvantage of statistical experiments or simulations.
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Liao, Chen-Hsuan, and 廖晨瑄. "Modeling the Statistical Variability of Process and Random Telegraph Signals Induced Threshold Voltage Shifts in Nanoscale MOSFETs and FinFETs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/33925910257458133100.
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碩士<br>國立交通大學<br>電子研究所<br>105<br>The trapping and de-trapping of a single electron at the Si-SiO2 interface of planar bulk metal -oxide-semiconductor field effect transistors (MOSFETs) and fin-shape field effect transistors (FinFETs), which is called random telegraph signals (RTSs), has been a well-known issue for the reliability of the nanoscale device. In this work, with the help of Matlab and 3-D technology-aided design (TCAD), we not only reproduce RTS experimental data but also make a prediction of possible worst case threshold-voltage fluctuation amplitude in both MOSFETs and FinFETs. We also propose a mloc-σloc boundary where mloc and σloc are the mean and the standard deviation, respectively, of the channel local current density. The critical mloc-loc curve divides the plot into the allowed and forbidden region. The allowed region includes all possible (mloc, σloc) sets that help us to reproduce experimental data. Furthermore, we take metal gate granularity (MGG) percolation into account. RTS under MGG percolation causes the device threshold-voltage fluctuating more serious. Necessarily, a large number of simulation tasks are carried out to investigate it. Different device sizes and different average metal grain sizes are considered in this work. By statistics, we can finely reproduce Intel’s data and even give a next-generation guide-line for circuit designers.
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Ou, Jyun-Rong, and 歐俊榮. "New Methods for Intrinsic Parasitic RLC Extraction and Small signal Equivalent Circuit Models for High Frequency and RF Noise Simulation in 3T and 4T Nanoscale Multi-finger MOSFETs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3j8eev.
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碩士<br>國立交通大學<br>電子研究所<br>106<br>In this thesis, an extensive investigation has been performed on the three- and four-terminal (3T and 4T) multi-finger nMOSFETs for precise extraction of intrinsic parasitic RLC and development of truly accurate intrinsic MOSFET model aimed at high frequency and RF noise simulation for nano-CMOS RF circuits design. Gate resistance (Rg), source resistance (Rs,int), and gate sidewall as well as finger-end fringing capacitances (Cof and Cf(poly-end)) appear as most important intrinsic parasitic RC with critical impact on high frequency performance and RF noise, and bring tough challenges to the conventional extraction methods when applied to 3T and 4T multi-finger MOSFETs. For the first time, a new extraction flow has been established for precise determination of the intrinsic parasitic source and drain resistances (Rs,int and Rd,int) and channel resistance (Rch) in 3T and 4T multi-finger MOSFETs and enable accurate prediction of the asymmetric gate to source/drain capacitances, i.e. Cgs≠Cgd at VDS=0 with critical dependence on Rs,int, Rd,int, and Rch. Afterwards, a new method and analytical model have been derived for accurate extraction of Rg and prediction of Rg@Y-method incorporating the Rs,int and Rd,int coupled through the intrinsic gate to source and drain capacitances (Cgs,i and Cgd,i). In this thesis, one more innovation creates new structures, namely multi-finger field devices for direct and precise extraction of Cof and Cf(poly-end) from high frequency measurement, without resort to 3-D interconnect RC simulation like Raphael. The mentioned innovations lead to successful extraction of intrinsic parasitic RC with complicated layout dependence and the integration with intrinsic device parameters determined by our proprietary high precision device parameters extraction method (US patent 8,691,599 B2) can realize the actual intrinsic MOSFET model for 3T and 4T multi-finger MOSFETs with proven accuracy for layout dependent effects and sensitivity to lot-to-lot and die-to-die variations.
The actual intrinsic MOSEFT model has been extensively verified and the accuracy is proven by good agreement with high frequency Y-parameters after openM1 and shortM1 deembedding for 3T and 4T nMOSFETs with various multi-finger layouts. Furthermore, the intrinsic device parameters and parasitic RLC with proven accuracy, when applied to analytical models can reach accurate prediction of the high frequency performance like fT and fMAX associated with various multi-finger layouts and facilitate layout optimization. One of the important findings and conclusions is that 4T multi-finger MOSFETs with sufficient freedom for various circuit topologies like common source, common gate, and common drain (CS, CG, and CD) under various body biases, generally suffer significant degradation of fT and fMAX due to drastic increase of Rs,int and Ls,int. The mentioned achievements provide a useful and efficient solution for high frequency simulation and design, without resort to BSIM-4 with limited accuracy for specified sample layouts.
Finally, the actual intrinsic MOSFET models can be further integrated with our proprietary lossy substrate model to build up a full equivalent circuit model, which can accurately simulate the high frequency S-, Y- and noise parameters, prior to deembedding. Furthermore, the lossy substrate deembedding method can be applied to both 3T and 4T multi-finger MOSFETs as a reliable solution for accurate extraction of intrinsic RF noise, which can eliminate the problems of conventional noise correlation matrix method and successfully identify the layout dependent effects in the truly intrinsic RF noise for multi-finger MOSFETs optimization aimed at low noise circuits design.
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Liang, Yu-Tang, and 梁育堂. "New Methods for Accurate Extraction of Intrinsic RF and AC Performance and Equivalent Circuit Models for High Frequency and RF Noise Simulation in Nanoscale MOSFETs with Various Layouts." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/5shvua.
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碩士<br>國立交通大學<br>電子研究所<br>106<br>In this thesis, one of our new proprietary structures, namely multi-finger field device has been designed and implemented in nanoscale CMOS processes like TN90GUTM and TN40G to realize direct and precise extraction of the gate sidewall and finger-end fringing capacitances, denoted as Cof and Cf(polyend). For the first time, the experimental Cof and Cf(polyend) can be achieved to serve as useful database for a serious calibration on the 3-D interconnect RC simulation like Raphael. Moreover, the multi-finger field devices can enable another innovative application, such as a truly clean deembedding of the Cof and Cf(polyend), namely field deembedding for the extraction of ideally intrinsic device parameters and high frequency performance parameters like fT and fMAX. For TN90GUTM and TN40G devices with gate length (Lg) pushed to the scales of 50 nm and 30nm, how to precisely separate and extract the intrinsic channel length (Lch) and source/drain extension (SDE) to gate overlap length (LSDE) becomes a very challenging work. Unfortunately, the original approach based on openM1 deembedding and Raphael simulation led to the abnormal results, such as signficant variation of LSDE and Lch associated with various finger width (WF), and the trend of shorter LSDE but longer Lch corresponding to the smaller WF i.e. the larger NF (finger number). In this thesis, the adoption of field deembedding method can eliminate the mentioned problem and achieve nearly constant LSDE among various WF and NF, i.e. nearly independent of WF and NF. It becomes an important progress to realize accurate extraction of the effective mobility associated with the intrinsic (inversion) channel and SDE (accumulation) regions, such as eff,ch and eff,acc, respectively. Furthermore, the ideal intrinsic Y- and H-parameters achieved after field deembedding can yield the ideally intrinsic gm, Cgg, and Cgd, and more importantly the ideal intrinsic fT and gate delay, int. For TN90GUTM nMOSFET, the ideal intrinsic peak fT can reach 227 GHz, which is around 27.5% higher than the actual intrinsic peak fT of 178 GHz. As For TN40G nMOSFET, there is around 75~100% enhancement of the peak fT compared to that of TN90GUTM, for actual and ideal intrinsic conditions. The ideal intrinsic peak fT can reach up to 473GHz, which is around 52% higher than the actual intrinsic peak fT of 312 GHz. The results reveal dramatic impact from the intrinsic parasitic RC on the high frequency performance and the impact increases in more advanced technology with further scaled devices.
Multi-OD (MOD) MOSFETs have been designed and fabricated in TN90RF as a potential solution for effective reduction of STI compressive transverse stress ⊥ and source resistance (RS), aimed at the increase of eff and gm and eventually fT improvement compared to the multi-finger MOSFETs with the same channel width (WOD). In this thesis, a new extraction flow has been developed for MOD MOSFETs with various WOD and NOD at the same WF=WOD×NOD and NF as those of multi-finger MOSFETs. The new features specific to MOD MOSFETs can be summarized as a new component of gate sidewall fringing capacitance originated from the gate on STI between adjacent OD (Cof,STI) and steeper STI sidewall profile due to the minimum OD-OD space, i.e. STI width. The basic device parameters extracted from the MOD MOSFETs indicate major differences in Lg and W and apparently smaller W compared to that of multi-finger MOSFETs, which is very critical for accurate determination of effective channel width (Weff) and extraction of eff. Through an extensive DC and RF characterization, the MOD nMOSFETs demonstrate some attractive features, such as the higher eff, smaller RS, larger gm, and most importantly the higher fT compared with the multi-finger MOSFETs with the same WOD. However, the MOD MOSFETs reveal two major drawbacks, such as larger DIBL and lower fMAX in comparison with the multi-finger MOSFETs. The former can be understood through an analysis of the finger-end and inter-OD fringing capacitances, i.e. Cf(poly-end) and Cof,STI, achieved from Raphael simulation. The results indicate that the significant increase of Cf(poly-end)NF in multi-finger MOSFETs with large NF becomes the dominant factor responsible for the effective suppression of DIBL. In comparison, the MOD MOSFET even with the addition of Cof,STINODNF but the combination of Cf(poly-end)NF and Cof,STINODNF with NF fixed at the minimum always keeps smaller than Cf(poly-end)NF with much larger NF and it leads to less suppression of DIBL. As for the much lower fMAX suffered by MOD MOSFETs even with higher fT, it accounts for the critical impact from the significant increase of gate resistance (Rg) and tough challenge to simultaneous optimization of fT and fMAX.
Full equivalent circuit models have been established with the actual intrinsic MOSFET models for multi-finger and MOD MOSFETs by adopting intrinsic parasitic RLC and lossy substrate RLC network for accurate simulation of high frequency characteristics and RF noise. The actual intrinsic MOSFET models including layout dependent device parameters and parasitic RLC with proven accuracy for various layouts can fix the problem of conventional compact model like BSIM-4 with limited accuracy for specific sample layouts in the PDK but severe deviation for the customer designed layouts beyond the PDK. RF noise simulation and intrinsic noise extraction appear as one more serious challenge to the conventional compact model. In this thesis, our developed equivalent circuit model can provide an effective solution for accurate simulation of the RF noise prior to deembedding and precise extraction of the actual intrinsic noise by using lossy substrate deembedding. Finally, the simulation by equivalent circuit model can facilitate the development of analytical models for quick calculation of intrinsic RF noise and assessment of layout dependent effects associated with multi-finger and MOD devices and impact from the parasitic RLC.
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周益欽. "Extraction of Channel Backscattering Coefficients in Nanoscale MOSFET." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/7h5yrs.
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碩士<br>國立交通大學<br>電子工程系所<br>92<br>Channel backscattering coefficients in the kBT layer (near the source) of 1.65-nm thick gate oxide n-channel MOSFETs are systematically separated into two distinct components: the quasi-thermal-equilibrium mean-free-path for backscattering and the width of the kBT layer. Evidence to confirm the validity of the separation procedure is further produced: (i) the near-source channel conduction-band profile; and (ii) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.