Relevant bibliographies by topics / Network on Chip (NoC)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Network on Chip (NoC)'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 June 2025

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Journal articles on the topic "Network on Chip (NoC)"

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Pradeep kumar, A., Y. Devendar Reddy, T. Srinivas Reddy, and K. Jamal. "An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method." Journal of Physics: Conference Series 2089, no. 1 (2021): 012069. http://dx.doi.org/10.1088/1742-6596/2089/1/012069.

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Abstract Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.
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Wang, Xin, and Jari Nurmi. "Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network." VLSI Design 2007 (April 5, 2007): 1–14. http://dx.doi.org/10.1155/2007/18372.

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Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL) in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.
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Charles, Subodha, and Prabhat Mishra. "A Survey of Network-on-Chip Security Attacks and Countermeasures." ACM Computing Surveys 54, no. 5 (2021): 1–36. http://dx.doi.org/10.1145/3450964.

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With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-Chip (SoC) architectures to cater to their communication requirements. NoC has received significant attention from both attackers and defenders. The increased usage of NoC and its distributed nature across the chip has made it a focal point of potential security attacks. Due to its prime location in the SoC coupled with connectivity with various components, NoC can be effectively utilized to implement security countermeasures to protect the SoC from potential attacks. There is a wide variety of existing literature on NoC security attacks and countermeasures. In this article, we provide a comprehensive survey of security vulnerabilities in NoC-based SoC architectures and discuss relevant countermeasures.
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Jiang, Zhan Peng, Rui Xu, Chang Chun Dong, and Lin Hai Cui. "Design of Router Supporting Multiply Routing Algorithm for NoC." Advanced Materials Research 981 (July 2014): 431–34. http://dx.doi.org/10.4028/www.scientific.net/amr.981.431.

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Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.
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AGYEMAN, MICHAEL O., ALI AHMADINIA, and ALIREZA SHAHRABI. "HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350016. http://dx.doi.org/10.1142/s0218126613500163.

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.
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R, Anala M., Amit N. Subrahmanya, and Allbright D’Souza. "Performance Analysis of Mesh-based NoC’s on Routing Algorithms." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3368. http://dx.doi.org/10.11591/ijece.v8i5.pp3368-3373.

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The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus – based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm.
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Latif, Khalid, Amir-Mohammad Rahmani, Tiberiu Seceleanu, and Hannu Tenhunen. "Cluster Based Networks-on-Chip." International Journal of Adaptive, Resilient and Autonomic Systems 4, no. 3 (2013): 25–41. http://dx.doi.org/10.4018/jaras.2013070102.

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Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.
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Guz, Zvika, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, and Avinoam Kolodny. "Network Delays and Link Capacities in Application-Specific Wormhole NoCs." VLSI Design 2007 (April 23, 2007): 1–15. http://dx.doi.org/10.1155/2007/90941.

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Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.
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Tan, Junyan, and Chunhua Cai. "An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning." Journal of Circuits, Systems and Computers 28, no. 05 (2019): 1950075. http://dx.doi.org/10.1142/s0218126619500750.

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Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.
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MOADELI, MAHMOUD, ALI SHAHRABI, WIM VANDERBAUWHEDE, and MOHAMED OULD-KHAOUA. "AN ANALYTICAL COMPARISON OF THE SPIDERGON AND RECTANGULAR MESH NoCs." Journal of Interconnection Networks 10, no. 01n02 (2009): 167–88. http://dx.doi.org/10.1142/s0219265909002492.

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Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.
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Dissertations / Theses on the topic "Network on Chip (NoC)"

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Bhojwani, Praveen Sunder. "Communication synthesis of networks-on-chip (noc)." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2022.

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Gkalea, Salvator. "Fault-Tolerant Nostrum NoC on FPGA for theForSyDe/NoC System Generator Tool Suite." Thesis, KTH, Elektronik och Inbyggda System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-163426.

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Moore’s law is the observation that over the years, the transistor density will increase,allowing billions of transistors to be integrated on a single chip. Over the lasttwo decades, Moore’s law has enabled the implementation of complex systems on asingle chip(SoCs). The challenge of the System-on-Chip(SoC) era was the demandof an efficient communication mechanism between the growing number of processingcores on the chip. The outcome established an new interconnection scheme (amongothers, like crossbars, rings, buses) based on the telecommunication networks andthe Network- on-Chip(NoC) appeared on the scene.The NoC has been developed not only to support systems embedded into asingle processor, but also to support a set of processors embedded on a singlechip.Therefore, the Multi-Processors System on Chip(MPSoC) has arisen, whichincorporate processing elements, memories and I/O with a fixed interconnection infrastructurein a complete integrated system. In such systems, the NoC constitutesthe backbone of the communication architecture that targets future SoC composedby hundred of processing elements. Besides that, together with the deep sub-microntechnology progress, some drawbacks have arisen. The communication efficiencyand the reliability of the systems rely on the proper functionality of NoC for onchipdata communication. A NoC must deal with the susceptibility of transistors tofailure that indicates the demand for a fault tolerant communication infrastructure.A mechanism that can deal with the existence of different classes of faults(transient,intermittent and permanent [11]) which can occur in the communication network.In this thesis, different algorithms are investigated that implement fault toleranttechniques for permanent faults in the NoC. The outcome would be to deliver a faulttolerantmechanism for the NoC System Generator Tool [29] which is a researchin Network-on-Chip carried out at the Royal Institute of Technology. It will beexplicitly described the fault tolerant algorithm that is implemented in the switchin order to achieve packet rerouting around the faulty communication links.
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Bhojwani, Praveen Sunder. "Mapping multimode system communication to a network-on-a-chip (NoC)." Texas A&M University, 2003. http://hdl.handle.net/1969.1/299.

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Decisions regarding the mapping of system-on-chip (SoC) components onto a NoC become more difficult with increasing complexity of system design. These complex systems capable of providing multiple functionalities tend to operate in multiple modes of operation. Modeling the system communication in these multimodes aids in efficient system design. This research provides a heuristic that gives a flexible mapping solution of the multimode system communications onto the NoC topology of choice. The solution specifies the immediate neighbors of the SoC components and the routes taken by all communications in the system. We validate the mapping results with a network-on-chip simulator (NoCSim). This thesis also investigates the cost associated with the interfacing of the components to the NoC. With the goal of reducing communication latency, we examine the packetization strategies in the NoC communication. Three schemes of implementations were analyzed, and the costs in terms of latency, and area were projected through actual synthesis.
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KAMEI, Camila Ascendina Nunes. "Estratégia para redução de congestionamento em sistemas multiprocessadores baseados em NOC." Universidade Federal de Pernambuco, 2015. https://repositorio.ufpe.br/handle/123456789/17243.

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Submitted by Fabio Sobreira Campos da Costa (fabio.sobreira@ufpe.br) on 2016-07-01T13:03:48Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) dissertacao_Camila_Ascendina_Nunes_Kamei.pdf: 2427056 bytes, checksum: 9c4bd5bb499271557f86edce757edec2 (MD5)<br>Made available in DSpace on 2016-07-01T13:03:48Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) dissertacao_Camila_Ascendina_Nunes_Kamei.pdf: 2427056 bytes, checksum: 9c4bd5bb499271557f86edce757edec2 (MD5) Previous issue date: 2015-08-07<br>CNPq<br>Duas questões são críticas em sistemas com paralelismo de memória em rede NoC baseados em MPSoC, a ordem de entrega da mensagem e o congestionamento da rede. Os congestionamentos são frequentes em NoC quando as demandas de pacotes excedem a capacidade dos recursos da rede e a ordem das mensagens precisam ser mantidas para que a informação de coerência de cache tenha signi cado para as memórias. Assim, métodos de controle de congestionamento são necessários para estes sistemas e devem lidar com o congestionamento da rede, enquanto mantém a ordem das transações. Este trabalho propõe uma técnica de roteamento baseada no algoritmo de roteamento Odd-Even associado ao conceito de congestionamento local e global da rede para a escolha do melhor caminho de encaminhamento dos pacotes de comunicação. Desta forma se objetiva a redução dos gargalos de comunicação da rede para os sistemas NoC baseado em MPSoC. Nos experimentos realizados para 16 núcleos, a técnica proposta alcançou a redução de 13,35% da energia consumida, 25% de redução de latência de envio de pacotes em comparação o algoritmo XY e 23% de redução de latência de envio de pacotes em comparação o algoritmo Odd-Even sem modi cação.<br>Two issues are critical in systems with memory parallelism network NoC-based MPSoC, the delivery order of messages and network congestion. The congestions are frequent in NoC when the packages demands exceed the capacity of the network resources and the order of the messages need to be maintained so that the cache coherency information is meaningful to the memories. Thus, congestion control methods are needed to deal with network congestion while they keep the order of the transactions. This paper proposes the use of the routing algorithm Odd-Even associated with the concept of local and global network congestion to choose the best routing path of communication packages. In this way it aims to reduce the network communication bottlenecks for NoC systems based on MPSoC. In experiments conducted for 16 cores, the proposed technique has achieved the reduction of 13.35 % of energy consumption, 25% of latency compared with the XY algorithm and 23% of latency compared with the Odd-Even algorithm without the modi cation.
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Ali, Baraa Saeed. "HIGH LEVEL SYNTHSIS FOR A NETWORK ON CHIP TOPOLOGY." OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1079.

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Network on chips (NoCs) have emerged as a panacea to solve many intercommunication issues that are imposed by the fast growing of VLSI design. NOC have been deployed as a solution for the communication delay between cores, area overhead, power consumption, etc. One of the leading parameters of speeding up the performance of system on chips (SOCs) is the efficiency of scheduling algorithms for the applications running on a SOC. In this thesis we are arguing that a global scheduling view can significantly improve latency in NoCs. This view can be achieved by having the NoC nodes communicate with each other in a predefined application-based fashion; by calculating in advance how many clock cycles the nodes need to execute and transmit packets to the network and how many clock cycles are needed for the packets to travel all the way to the destination through routers (including queuing delay). By knowing that, we could keep some of the cores stay in "Hold-On" state until the right time comes to start transmitting. This technique could lead to reduced congestion and it may guarantee that the cores do not suffer from severe resource contention, e.g. accessing memory. This task is achieved by using a network simulator (such as OPNET) and gathering statistics, so the worst case latency can be determined. Therefore, if NoC nodes can somehow postpone sending packets in a way that does not violate the deadline of their tasks, packet dropping or livelock can be avoided. It is assumed that the NoC nodes here need buffers of their own in order to hold the ready-to-transmit packets and this can be the cost of this approach.
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Flórez, Martha Johanna Sepúlveda. "Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.

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The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.<br>The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
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MAZUMDAR, SOMNATH. "An Efficient NoC-based Framework To Improve Dataflow Thread Management At Runtime." Doctoral thesis, Università di Siena, 2017. http://hdl.handle.net/11365/1011261.

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This doctoral thesis focuses on how the application threads that are based on dataflow execution model can be managed at Network-on-Chip (NoC) level. The roots of the dataflow execution model date back to the early 1970’s. Applications adhering to such program execution model follow a simple producer-consumer communication scheme for synchronising parallel thread related activities. In dataflow execution environment, a thread can run if and only if all its required inputs are available. Applications running on a large and complex computing environment can significantly benefit from the adoption of dataflow model. In the first part of the thesis, the work is focused on the thread distribution mechanism. It has been shown that how a scalable hash-based thread distribution mechanism can be implemented at the router level with low overheads. To enhance the support further, a tool to monitor the dataflow threads’ status and a simple, functional model is also incorporated into the design. Next, a software defined NoC has been proposed to manage the distribution of dataflow threads by exploiting its reconfigurability. The second part of this work is focused more on NoC microarchitecture level. Traditional 2D-mesh topology is combined with a standard ring, to understand how such hybrid network topology can outperform the traditional topology (such as 2D-mesh). Finally, a mixed-integer linear programming based analytical model has been proposed to verify if the application threads mapped on to the free cores is optimal or not. The proposed mathematical model can be used as a yardstick to verify the solution quality of the newly developed mapping policy. It is not trivial to provide a complete low-level framework for dataflow thread execution for better resource and power management. However, this work could be considered as a primary framework to which improvements could be carried out.
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Kilinc, Ismail Ozsel. "Fpga Implementation Of A Network-on-chip." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613635/index.pdf.

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This thesis aims to design a Network-on-Chip (NoC) that performs wormhole flow control method and source routing and aims to describe the design in VHDL language and implement it on an FPGA platform. In order to satisfy the diverse needs of different network traffic, the thesis aims to design the NoC in such a way that it can be modified via a user interface, which changes the descriptions in the VHDL source code. Network topology, number of router ports, number of virtual channels, buffer size and flit size are the features of the designed NoC that can be modified. In this thesis, interfaces and operations of the blocks in the NoC are defined through block diagrams and algorithmic state machines. Verification of these blocks is performed not only on computer environment via simulations tools, but also in real world. To achieve this, source nodes generating dummy flits are also designed which communicate with our user interface via RS-232 generating flits according to the information provided by the user and monitoring the received flits from other source nodes in real-time.
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SWAMINATHAN, VIJAY. "PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922.

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Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC<br>Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
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Books on the topic "Network on Chip (NoC)"

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Nicopoulos, Chrysostomos, Vijaykrishnan Narayanan, and Chita R. Das. Network-on-Chip Architectures. Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-3031-3.

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Bergman, Keren, Luca P. Carloni, Aleksandr Biberman, Johnnie Chan, and Gilbert Hendry. Photonic Network-on-Chip Design. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4419-9335-9.

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Mishra, Prabhat, and Subodha Charles, eds. Network-on-Chip Security and Privacy. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8.

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Dimitrakopoulos, Giorgos, Anastasios Psarras, and Ioannis Seitanidis. Microarchitecture of Network-on-Chip Routers. Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-4301-8.

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Fu, Bo, and Paul Ampadu. Error Control for Network-on-Chip Links. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4419-9313-7.

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Krief, Francine. Communicating embedded systems: Network applications. ISTE, 2010.

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Krief, Francine. Communicating embedded systems: Network applications. ISTE, 2010.

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Krief, Francine. Communicating embedded systems: Network applications. ISTE, 2010.

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Yoo, Hoi-Jun. Low-power NoC for high-performace SoC design. Taylor & Francis, 2008.

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Yoo, Hoi-Jun. Low-Power NoC for High-Performance SoC Design. Taylor and Francis, 2008.

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Book chapters on the topic "Network on Chip (NoC)"

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Fu, Bo, and Paul Ampadu. "Networks-on-Chip (NoC)." In Error Control for Network-on-Chip Links. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9313-7_3.

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Chen, Sao-Jie, Ying-Cherng Lan, Wen-Chung Tsai, and Yu-Hen Hu. "Bidirectional Noc Architecture." In Reconfigurable Networks-on-Chip. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9341-0_6.

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Gundi, Noel Daniel, Prabal Basu, Sanghamitra Roy, and Koushik Chakraborty. "Design of Reliable NoC Architectures." In Network-on-Chip Security and Privacy. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8_14.

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Schwaderer, W. David. "Benchmarking Network-on-Chip (NoC) Designs." In Introduction to Open Core Protocol. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0103-2_12.

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Rout, Sidhartha Sankar, Mitali Sinha, and Sujay Deb. "NoC Post-Silicon Validation and Debug." In Network-on-Chip Security and Privacy. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8_13.

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Tatas, Konstantinos, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch. "NoC-Based System Integration." In Designing 2D and 3D Network-on-Chip Architectures. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4274-5_5.

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Tatas, Konstantinos, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch. "NoC Verification and Testing." In Designing 2D and 3D Network-on-Chip Architectures. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4274-5_6.

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Charles, Subodha, and Prabhat Mishra. "Trust-Aware Routing in NoC-Based SoCs." In Network-on-Chip Security and Privacy. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8_5.

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Cota, Érika, Alexandre de Morais Amory, and Marcelo Soares Lubaszewski. "NoC Basics." In Reliability, Availability and Serviceability of Networks-on-Chip. Springer US, 2011. http://dx.doi.org/10.1007/978-1-4614-0791-1_2.

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Tatas, Konstantinos, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch. "NoC Modeling and Topology Exploration." In Designing 2D and 3D Network-on-Chip Architectures. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4274-5_2.

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Conference papers on the topic "Network on Chip (NoC)"

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"Network on chip (NoC)." In 2016 International Conference on Field-Programmable Technology (FPT). IEEE, 2016. http://dx.doi.org/10.1109/fpt.2016.7929520.

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Cidon, Israel. "NoC: Network or Chip?" In First International Symposium on Networks-on-Chip. IEEE, 2007. http://dx.doi.org/10.1109/nocs.2007.33.

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Swarbrick, Ian, Dinesh Gaitonde, Sagheer Ahmad, et al. "Versal Network-on-Chip (NoC)." In 2019 IEEE Symposium on High-Performance Interconnects (HOTI). IEEE, 2019. http://dx.doi.org/10.1109/hoti.2019.00016.

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Zoni, Davide, and William Fornaciari. "NBTI-aware design of NoC buffers." In the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip. ACM Press, 2013. http://dx.doi.org/10.1145/2482759.2482766.

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Shalaby, Ahmed, Yaswanth Tavva, Trevor E. Carlson, and Li-Shiuan Peh. "Sentry-NoC." In NOCS '21: International Symposium on Networks-on-Chip. ACM, 2021. http://dx.doi.org/10.1145/3479876.3481595.

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Shalaby, Ahmed, Yaswanth Tavva, Trevor E. Carlson, and Li-Shiuan Peh. "Sentry-NoC." In NOCS '21: International Symposium on Networks-on-Chip. ACM, 2021. http://dx.doi.org/10.1145/3479876.3481595.

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Ortín, Marta, Alexandra Ferrerón, Jorge Albericio, et al. "Characterization and cost-efficient selection of NoC topologies for general purpose CMPs." In the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip. ACM Press, 2013. http://dx.doi.org/10.1145/2482759.2482765.

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Lokananta, Felix, S. W. Lee, M. S. Ng, Z. N. Lim, and C. M. Tang. "UTAR NoC: Adaptive Network on Chip architecture platform." In 2015 3rd International Conference on New Media (CONMEDIA). IEEE, 2015. http://dx.doi.org/10.1109/conmedia.2015.7449147.

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Chen, Kun-Chih (Jimmy), Masoumeh Ebrahimi, Ting-Yi Wang, and Yuch-Chi Yang. "NoC-based DNN accelerator." In NOCS '19: International Symposium on Networks-on-Chip. ACM, 2019. http://dx.doi.org/10.1145/3313231.3352376.

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Grammatikakis, Miltos D., Voula Piperaki, and Antonis Papagrigoriou. "Multilayer NoC firewall services." In NOCS '21: International Symposium on Networks-on-Chip. ACM, 2021. http://dx.doi.org/10.1145/3479876.3481598.

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Reports on the topic "Network on Chip (NoC)"

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Trembeczki, Zsolt. Blue Chip Networks: Two Case Studies of Countering the Belt and Road Initiative. Külügyi és Külgazdasági Intézet, 2021. http://dx.doi.org/10.47683/kkielemzesek.ke-2021.65.

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While debates over China’s Belt and Road Initiative (BRI) dominate the discourse over global infrastructure development, countries sceptical of the purpose or potential of the BRI have launched multiple alternative initiatives. This analysis compares two case studies: the Asia-Africa Growth Corridor (AAGC) launched by Japan and India in 2017, in part building on Japan’s Quality Infrastructure concept, and the G7’s 2021 Build Back Better World (B3W) plan, which is effectively a follow-up on the Blue Dot Network announced by the United States, Japan, and Australia in 2019. The paper concludes that the set of high financial and project quality standards of these initiatives may lead to better overall return but also prohibitive initial costs, while admirable goals like gender equity or digitised governance may not always respond adequately to the infrastructure priorities of developing countries. Furthermore, while these initiatives rely heavily on mobilising private capital, the literature clearly shows that infrastructure projects, especially in developing regions, are typically rather unattractive for private investors. Nevertheless, with a staggering USD 15 trillion gap in projected needs and actual spending on global infrastructure by 2040, there is no reason for a zero-sum competition between Chinese and Western connectivity programmes. Thus, Hungary should remain open to all and not commit exclusively to any of these initiatives.
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Raychev, Nikolay. Can human thoughts be encoded, decoded and manipulated to achieve symbiosis of the brain and the machine. Web of Open Science, 2020. http://dx.doi.org/10.37686/nsrl.v1i2.76.

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This article discusses the current state of neurointerface technologies, not limited to deep electrode approaches. There are new heuristic ideas for creating a fast and broadband channel from the brain to artificial intelligence. One of the ideas is not to decipher the natural codes of nerve cells, but to create conditions for the development of a new language for communication between the human brain and artificial intelligence tools. Theoretically, this is possible if the brain "feels" that by changing the activity of nerve cells that communicate with the computer, it is possible to "achieve" the necessary actions for the body in the external environment, for example, to take a cup of coffee or turn on your favorite music. At the same time, an artificial neural network that analyzes the flow of nerve impulses must also be directed at the brain, trying to guess the body's needs at the moment with a minimum number of movements. The most important obstacle to further progress is the problem of biocompatibility, which has not yet been resolved. This is even more important than the number of electrodes and the power of the processors on the chip. When you insert a foreign object into your brain, it tries to isolate itself from it. This is a multidisciplinary topic not only for doctors and psychophysiologists, but also for engineers, programmers, mathematicians. Of course, the problem is complex and it will be possible to overcome it only with joint efforts.
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Michelogiannakis, George, and John Shalf. Variable-Width Datapath for On-Chip Network Static Power Reduction. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1164909.

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García Zaballos, Antonio, Maribel Dalio, Jesús Garran, Enrique Iglesias Rodriguez, Pau Puig Gabarró, and Ricardo Martínez Garza Fernández. Estructuración de un centro de operación de redes (NOC). Banco Interamericano de Desarrollo, 2022. http://dx.doi.org/10.18235/0004520.

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El desarrollo de la tecnología 5G nos permitirá descubrir cosas que hasta ahora no podíamos hacer tecnológicamente. Y habilitará la fusión del mundo físico (operational technology, OT) con el mundo digital (information technology, IT), abriendo nuevos mundos como son internet de las cosas (Internet of Things, IoT), metaverso, digital twin, entre otros. El centro de operaciones de red (Network Operations Center, NOC) es la herramienta que nos permite garantizar la disponibilidad y el rendimiento de las redes. En particular, el NOC será responsable de monitorizar, identificar, investigar, priorizar, resolver o escalar incidentes en la red, que pueden afectar o que están afectando su disponibilidad o rendimiento. Esta publicación presenta y desarrolla la hoja de ruta para diseñar y poner en marcha un NOC que contribuya al éxito de la implementación de la estrategia nacional de conectividad y garantice el funcionamiento correcto de la infraestructura digital, facilitando la conectividad de comunidades e instituciones.
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Chung, Haera. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.997.

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Henderson, Tim, Vincent Santucci, Tim Connors, and Justin Tweet. National Park Service geologic type section inventory: Sonoran Desert Inventory & Monitoring Network. National Park Service, 2022. http://dx.doi.org/10.36967/2294374.

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Type sections are one of several kinds of stratotype. A stratotype is the standard (original or subsequently designated), accessible, and specific sequence of rock for a named geologic unit that forms the basis for the definition, recognition, and comparison of that unit elsewhere. Geologists designate stratotypes for rock exposures that are illustrative and representative of the map unit being defined. Stratotypes ideally should remain accessible for examination and study by others. In this sense, geologic stratotypes are similar in concept to biological type specimens; however, they remain in situ as rock exposures rather than curated in a repository. Therefore, managing stratotypes requires inventory and monitoring like other geologic heritage resources in parks. In addition to type sections, stratotypes also include type localities, type areas, reference sections, and lithodemes, all of which are defined in this report. The goal of this project is to consolidate information pertaining to stratotypes that occur within NPS-administered areas, in order that this information is available throughout the NPS to inform park managers and to promote the preservation and protection of these important geologic heritage resources. This effort identified six stratotypes designated within four park units of the Sonoran Desert Inventory &amp; Monitoring Network (SODN): Chiricahua National Monument (CHIR) has three type areas; Coronado National Memorial (CORO) has one type area; Gila Cliff Dwellings National Monument (GICL) has one type area; and Saguaro National Park (SAGU) has one type area. Table 1 provides information regarding the six stratotypes currently identified within SODN parks. There are currently no designated stratotypes within Casa Grande Ruins National Monument (CAGR), Fort Bowie National Historic Site (FOBO), Montezuma Castle National Monument (MOCA), Organ Pipe Cactus National Monument (ORPI), Tonto National Monument (TONT), Tumacácori National Historical Park (TUMA), or Tuzigoot National Monument (TUZI). However, CHIR, MOCA, SAGU, and TUZI contain important rock exposures that could be considered for formal stratotype designation as discussed in the “Recommendations” section. The inventory of geologic stratotypes across the NPS is an important effort in documenting these locations so that NPS staff may recognize and protect these areas for future studies. The focus adopted for completing the baseline inventories throughout the NPS has centered on the 32 inventory and monitoring (I&amp;M) networks established during the late 1990s. Adopting a network-based approach to inventories worked well when the NPS undertook paleontological resource inventories for the 32 I&amp;M networks and was therefore adopted for the stratotype inventory. The Greater Yellowstone I&amp;M Network (GRYN) was the pilot network for initiating this project (Henderson et al. 2020). Methodologies and reporting strategies adopted for the GRYN have been used in the development of this report for the SODN. This report includes a recommendation section that addresses outstanding issues and future steps regarding park unit stratotypes. These recommendations will hopefully guide decision-making and help ensure that these geoheritage resources are properly protected and that proposed park activities or development will not adversely impact the stability and condition of these geologic exposures.
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Wang, Lili, Xuesong Wang, Yin Wu, Lingxiao Ye, Yahua Zheng, and Rui Fan. The Effects of Non-Pharmacological Therapies for Psychological State of Medical Staff in the Post-epidemic Era: A Protocol Network Meta-Analysis. INPLASY - International Platform of Registered Systematic Review and Meta-analysis Protocols, 2022. http://dx.doi.org/10.37766/inplasy2022.2.0080.

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Review question / Objective: To compare and rank the clinical effects of Non-Pharmacological Therapies for Psychological State of Medical Staff in the Post-epidemic Eradifferent. Eligibility criteria: The published randomized controlled trials (RCT) of non-Pharmacological Therapies for Psychological State of Medical Staff in the Post-epidemic Era, regardless of age and gender. Patients had clear diagnostic criteria to be diagnosed. Interventions in the treatment group included were various types of non-pharmacological therapies, including various types of acupuncture therapies (such as simple acupuncture, electroacupuncture, warm acupuncture, acupuncture catgut embedding, Auricular therapy, or the combination of acupuncture and other Non-Pharmacological Therapies), meditation, Baduanjin, Tai Chi, aerobic exercise, yoga, psychotherapy, music therapy, etc.; the control group was conventional treatment groups or different non-pharmacological therapies compared with each other. The results of the report are required to include at least one of the following outcome indicators: The self-Rating Anxiety Scale (SAS), the Self-Rating Depression Scale (SDS), the Pittsburgh sleep quality index (PSQI), and effectiveness rate. The language of the publication is limited to Chinese or English.
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Henderson, Tim, Vincent Santucci, Tim Connors, and Justin Tweet. National Park Service geologic type section inventory: Southern Plains Inventory & Monitoring Network. National Park Service, 2022. http://dx.doi.org/10.36967/nrr-2293756.

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Type sections are one of several kinds of stratotypes. A stratotype is the standard (original or subsequently designated), accessible, and specific sequence of rock for a named geologic unit that forms the basis for the definition, recognition, and comparison of that unit elsewhere. Geologists designate stratotypes for rock exposures that are illustrative and representative of the map unit being defined. Stratotypes ideally should remain accessible for examination and study by others. In this sense, geologic stratotypes are similar in concept to biological type specimens, however, they remain in situ as rock exposures rather than curated in a repository. Therefore, managing stratotypes requires inventory and monitoring like other geologic heritage resources in parks. In addition to type sections, stratotypes also include type localities, type areas, reference sections, and lithodemes, all of which are defined in this report. The goal of this project is to consolidate information pertaining to stratotypes that occur within NPS-administered areas, in order that this information is available throughout the NPS to inform park managers and to promote the preservation and protection of these important geologic heritage resources. This effort identified two stratotypes designated within two park units of the Southern Plains Inventory &amp; Monitoring Network (SOPN): Alibates Flint Quarries National Monument (ALFL) has one type locality; and Capulin Volcano National Monument (CAVO) contains one type area. There are currently no designated stratotypes within Bent’s Old Fort National Historic Site (BEOL), Chickasaw National Recreation Area (CHIC), Fort Larned National Historic Site (FOLS), Fort Union National Monument (FOUN), Lake Meredith National Recreation Area (LAMR), Lyndon B. Johnson National Historical Park (LYJO), Pecos National Historical Site (PECO), Sand Creek Massacre National Historic Site (SAND), Waco Mammoth National Monument (WACO), and Washita Battlefield National Historic Site (WABA). The inventory of geologic stratotypes across the NPS is an important effort in documenting these locations in order that NPS staff recognize and protect these areas for future studies. The focus adopted for completing the baseline inventories throughout the NPS has centered on the 32 inventory and monitoring (I&amp;M) networks established during the late 1990s. Adopting a network-based approach to inventories worked well when the NPS undertook paleontological resource inventories for the 32 I&amp;M networks and was therefore adopted for the stratotype inventory. The Greater Yellowstone I&amp;M Network (GRYN) was the pilot network for initiating this project (Henderson et al. 2020). Methodologies and reporting strategies adopted for the GRYN have been used in the development of this report for the SOPN. This report includes a recommendation section that addresses outstanding issues and future steps regarding park unit stratotypes. These recommendations will hopefully guide decision-making and help ensure that these geoheritage resources are properly protected and that proposed park activities or development will not adversely impact the stability and condition of these geologic exposures.
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Peng, ciyan, jing Chen, lei Yang, et al. Comparative Efficacy of 13 CHIs Combined with TP regimen chemotherapy for patients Non-small Cell Lung Cancer: A Bayesian Network Meta-Analysis of Randomized Controlled Trials. INPLASY - International Platform of Registered Systematic Review and Meta-analysis Protocols, 2022. http://dx.doi.org/10.37766/inplasy2022.10.0093.

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Barg, Rivka, Erich Grotewold, and Yechiam Salts. Regulation of Tomato Fruit Development by Interacting MYB Proteins. United States Department of Agriculture, 2012. http://dx.doi.org/10.32747/2012.7592647.bard.

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Background to the topic: Early tomato fruit development is executed via extensive cell divisions followed by cell expansion concomitantly with endoreduplication. The signals involved in activating the different modes of growth during fruit development are still inadequately understood. Addressing this developmental process, we identified SlFSM1 as a gene expressed specifically during the cell-division dependent stages of fruit development. SlFSM1 is the founder of a class of small plant specific proteins containing a divergent SANT/MYB domain (Barg et al 2005). Before initiating this project, we found that low ectopic over-expression (OEX) of SlFSM1 leads to a significant decrease in the final size of the cells in mature leaves and fruits, and the outer pericarp is substantially narrower, suggesting a role in determining cell size and shape. We also found the interacting partners of the Arabidopsis homologs of FSM1 (two, belonging to the same family), and cloned their tomato single homolog, which we named SlFSB1 (Fruit SANT/MYB–Binding1). SlFSB1 is a novel plant specific single MYB-like protein, which function was unknown. The present project aimed at elucidating the function and mode of action of these two single MYB proteins in regulating tomato fruit development. The specific objectives were: 1. Functional analysis of SlFSM1 and its interacting protein SlFSB1 in relation to fruit development. 2. Identification of the SlFSM1 and/or SlFSB1 cellular targets. The plan of work included: 1) Detailed phenotypic, histological and cellular analyses of plants ectopically expressing FSM1, and plants either ectopically over-expressing or silenced for FSB1. 2) Extensive SELEX analysis, which did not reveal any specific DNA target of SlFSM1 binding, hence the originally offered ChIP analysis was omitted. 3) Genome-wide transcriptional impact of gain- and loss- of SlFSM1 and SlFSB1 function by Affymetrix microarray analyses. This part is still in progress and therefore results are not reported, 4) Search for additional candidate partners of SlFSB1 revealed SlMYBI to be an alternative partner of FSB1, and 5) Study of the physical basis of the interaction between SlFSM1 and SlFSB1 and between FSB1 and MYBI. Major conclusions, solutions, achievements: We established that FSM1 negatively affects cell expansion, particularly of those cells with the highest potential to expand, such as the ones residing inner to the vascular bundles in the fruit pericarp. On the other hand, FSB1 which is expressed throughout fruit development acts as a positive regulator of cell expansion. It was also established that besides interacting with FSM1, FSB1 interacts also with the transcription factor MYBI, and that the formation of the FSB1-MYBI complex is competed by FSM1, which recognizes in FSB1 the same region as MYBI does. Based on these findings a model was developed explaining the role of this novel network of the three different MYB containing proteins FSM1/FSB1/MYBI in the control of tomato cell expansion, particularly during fruit development. In short, during early stages of fruit development (Phase II), the formation of the FSM1-FSB1 complex serves to restrict the expansion of the cells with the greatest expansion potential, those non-dividing cells residing in the inner mesocarp layers of the pericarp. Alternatively, during growth phase III, after transcription of FSM1 sharply declines, FSB1, possibly through complexing with the transcription factor MYBI serves as a positive regulator of the differential cell expansion which drives fruit enlargement during this phase. Additionally, a novel mechanism was revealed by which competing MYB-MYB interactions could participate in the control of gene expression. Implications, both scientific and agricultural: The demonstrated role of the FSM1/FSB1/MYBI complex in controlling differential cell growth in the developing tomato fruit highlights potential exploitations of these genes for improving fruit quality characteristics. Modulation of expression of these genes or their paralogs in other organs could serve to modify leaf and canopy architecture in various crops.
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