Academic literature on the topic 'Network-on-chips'
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Journal articles on the topic "Network-on-chips"
BAHN, JUN HO, JUNG SOOK YANG, WEN-HSIANG HU, and NADER BAGHERZADEH. "PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 255–69. http://dx.doi.org/10.1142/s0218126609005046.
Full textLouri, Ahmed, and Avinash Kodi. "Special Issue on Network-on-Chips (NoCs)." Journal of Parallel and Distributed Computing 70, no. 1 (January 2010): 69. http://dx.doi.org/10.1016/j.jpdc.2009.10.007.
Full textSzu, Harold, Jung Kim, and Insook Kim. "Live neural network formations on electronic chips." Neurocomputing 6, no. 5-6 (October 1994): 551–64. http://dx.doi.org/10.1016/0925-2312(94)90006-x.
Full textHe, Yuan, Hiroki Matsutani, Hiroshi Sasaki, and Hiroshi Nakamura. "Adaptive Data Compression on 3D Network-on-Chips." IPSJ Online Transactions 5 (2012): 13–20. http://dx.doi.org/10.2197/ipsjtrans.5.13.
Full textChen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips." Journal of Software 10, no. 2 (February 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.
Full textZhang, Kunwei, and Thomas Moscibroda. "Twist-Routing Algorithm for Faulty Network-on-Chips." Journal of Computer and Communications 04, no. 14 (2016): 1–10. http://dx.doi.org/10.4236/jcc.2016.414001.
Full textLi, Feihui, Guangyu Chen, Mahmut Kandemir, and Ibrahim Kolcu. "Profile-driven energy reduction in network-on-chips." ACM SIGPLAN Notices 42, no. 6 (June 10, 2007): 394–404. http://dx.doi.org/10.1145/1273442.1250779.
Full textChen, Yuechen, and Ahmed Louri. "An Approximate Communication Framework for Network-on-Chips." IEEE Transactions on Parallel and Distributed Systems 31, no. 6 (June 1, 2020): 1434–46. http://dx.doi.org/10.1109/tpds.2020.2968068.
Full textGeppert, L. "The new chips on the block [network processors]." IEEE Spectrum 38, no. 1 (January 2001): 66–68. http://dx.doi.org/10.1109/6.901145.
Full textHamdi, Doaa A., Samy Ghoniemy, Yasser Dakroury, and Mohammed A. Sobh. "A Scalable Software Defined Network Orchestrator for Photonic Network on Chips." IEEE Access 9 (2021): 35371–81. http://dx.doi.org/10.1109/access.2021.3058238.
Full textDissertations / Theses on the topic "Network-on-chips"
Xiang, Xiyue. "Contention Alleviation in Network-on-Chips." Thesis, University of Louisiana at Lafayette, 2017. http://pqdtopen.proquest.com/#viewpdf?dispub=10272587.
Full textIn a network-on-chip (NoC) based system, the NoC is a shared resource among multiple processor cores. Requests generated by different applications running on different cores can create severe contention in NoCs. This contention can jeopardize the system performance and power efficiency in many different formats. First and foremost, we discover that the contention in NoCs can induce inter-application interference, leading to overall system performance degradation, prevent fair-progress of different applications, and cause starvation of unfairly-treated applications. We propose the NoC Application Slowdown (NAS) Model, the first online model that accurately estimates how much network delays due to interference contribute to the overall stall time of each application. We use NAS to develop Fairness-Aware Source Throttling (FAST), a mechanism that employs slowdown predictions to control the network injection rates of applications in a way that minimizes system unfairness. Furthermore, although removing buffers from the constituent routers can reduce power consumption and hardware complexity, the bufferless NoC is subject to the growing deflection caused by contention, leading to severe performance degradation and squandering power-saving potential. we then propose Deflection Containment (DeC) for the bufferless NoC to address its notorious shortcoming of excessive deflection for performance improvement and power reduction. With a link added to each router for bridging subnetworks (whose aggregated link width equals a give value, say, 128b), DeC lets a contending flit in one subnetwork be forwarded to another subnetwork instead of deflected, yielding extraordinary deflection reduction and greatly enriching path diversity. In addition, router microarchitecture under DeC is rectified to shorten the critical path and lift network bandwidth. Last but not least, beside 1-to-1 flow, the growing core counts urgently requires effective hardware support to alleviate the contention caused by 1-to-many and many-to-1 flow. We propose Carpool, the very first bufferless NoC optimized for 1-to-many and many-to-1 traffic. Carpool adaptively forks new flit replicas and performs traffic aggregation at appropriate intermediate routers to lessen bandwidth demands and reduce contention. We propose the microarchitecture of Carpool routers and develop parallel port allocation which supports multicast and reduces critical paths to improve network bandwidth.
Kwa, Jimmy Williamchingyuan. "Optimizing network-on-chips for FPGAs." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44343.
Full textBakhoda, Ali. "Designing network-on-chips for throughput accelerators." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/46423.
Full textPattabiraman, Aishwariya. "Heterogeneous Cache Architecture in Network-on-Chips." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1321371508.
Full textSarkar, Souradip. "Multiple clock domain synchronization for network on chips." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/S_Sarkar_112907.pdf.
Full textAlshraiedeh, Juman. "Wear-out Leveling in Network on Chips (NoCs)." Ohio University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1492677926079357.
Full textBhardwaj, Kshitij. "Aging-Aware Routing Algorithms for Network-on-Chips." DigitalCommons@USU, 2012. https://digitalcommons.usu.edu/etd/1319.
Full textZhang, Yixuan. "High-Performance Crossbar Designs for Network-on-Chips (NoCs)." Ohio University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1282056856.
Full textBoraten, Travis Henry. "Hardware Security Threat and Mitigation Techniques for Network-on-Chips." Ohio University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173.
Full textBoraten, Travis H. "Runtime Adaptive Scrubbing in Fault-Tolerant Network-on-Chips (NoC) Architectures." Ohio University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488496.
Full textBooks on the topic "Network-on-chips"
Fayez, Gebali, Elmiligi Haytham, and El-Kharashi Mohamed Watheq, eds. Networks-on-chips: Theory and practice. Boca Raton: Taylor & Francis, 2009.
Find full textservice), SpringerLink (Online, ed. Designing Reliable and Efficient Networks on Chips. Dordrecht: Springer Netherlands, 2009.
Find full textPower-Efficient Network-on-Chips: Design and Evaluation. Elsevier, 2022. http://dx.doi.org/10.1016/s0065-2458(22)x0002-8.
Full textGebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2017.
Find full textGebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2011.
Find full textGebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2009.
Find full textMurali, Srinivasan. Designing Reliable and Efficient Networks on Chips. Springer, 2010.
Find full textBook chapters on the topic "Network-on-chips"
Shruthi, R., H. R. Shashidhara, and M. S. Deepthi. "Comprehensive Survey on Wireless Network on Chips." In Algorithms for Intelligent Systems, 203–18. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-5747-4_18.
Full textFriederich, Stephanie, Niclas Lehmann, and Jürgen Becker. "Adaptive Bandwidth Router for 3D Network-on-Chips." In Lecture Notes in Computer Science, 352–60. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30481-6_30.
Full textSilva, Luneque, Nadia Nedjah, Luiza de Macedo Mourelle, and Fábio Gonçalves Pessanha. "ACO-Based Static Routing for Network-on-Chips." In Computational Science and Its Applications – ICCSA 2012, 113–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31125-3_9.
Full textNedjah, Nadia, and Luiza de Macedo Mourelle. "Routing in Network-on-Chips Using Ant Colony Optimization." In Hardware for Soft Computing and Soft Computing for Hardware, 173–98. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03110-1_11.
Full textUrkude, Vijaykumar R. "Design Optimization and Fault Tolerance in Network-On-Chips." In Algorithms for Intelligent Systems, 511–19. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6307-6_51.
Full textFrieb, Martin, Alexander Stegmeier, Jörg Mische, and Theo Ungerer. "Lightweight Hardware Synchronization for Avoiding Buffer Overflows in Network-on-Chips." In Lecture Notes in Computer Science, 112–26. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77610-1_9.
Full textRunge, Armin, and Reiner Kolla. "An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips." In Architecture of Computing Systems – ARCS 2016, 48–59. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_4.
Full textCai, Yuan, and Xiang Ji. "ASA-routing: A-Star Adaptive Routing Algorithm for Network-on-Chips." In Algorithms and Architectures for Parallel Processing, 187–98. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-05054-2_14.
Full textLi, Jiazheng, Guozhi Song, Yue Ma, Cheng Wang, Baohui Zhu, Yan Chai, and Jieqi Rong. "Bat Algorithm Based Low Power Mapping Methods for 3D Network-on-Chips." In Communications in Computer and Information Science, 277–95. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6893-5_21.
Full textDai, Fei, Yawen Chen, Zhiyi Huang, and Haibo Zhang. "Performance Comparison of Multi-layer Perceptron Training on Electrical and Optical Network-on-Chips." In Parallel and Distributed Computing, Applications and Technologies, 129–41. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-96772-7_13.
Full textConference papers on the topic "Network-on-chips"
Diguet, Jean-Philippe. "Self-Adaptive Network On Chips." In the 27th Symposium. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2660540.2660992.
Full textEbrahimi, Masoumeh, Masoud Daneshtalab, N. P. Sreejesh, Pasi Liljeberg, and Hannu Tenhunen. "Efficient network interface architecture for network-on-chips." In 2009 NORCHIP. IEEE, 2009. http://dx.doi.org/10.1109/norchp.2009.5397837.
Full textBahn, Jun Ho, Jungsook Yang, and Nader Bagherzadeh. "Parallel FFT Algorithms on Network-on-Chips." In 2008 Fifth International Conference on Information Technology: New Generations (ITNG). IEEE, 2008. http://dx.doi.org/10.1109/itng.2008.55.
Full textJoseph, Jan Moritz, Dominik Ermel, Lennart Bamberg, Alberto Garcia Oritz, and Thilo Pionteck. "System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips." In 2019 IEEE 37th International Conference on Computer Design (ICCD). IEEE, 2019. http://dx.doi.org/10.1109/iccd46524.2019.00064.
Full textKendaganna Swamy S, Anil N, Anand Jatti, and Uma B V. "Platform level design for Network on Chips." In 2015 IEEE International Advance Computing Conference (IACC). IEEE, 2015. http://dx.doi.org/10.1109/iadcc.2015.7154676.
Full textPereñíguez-García, Fernando, and José L. Abellán. "Secure communications in wireless network-on-chips." In AISTECS '17: 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3073763.3073768.
Full textGaoMing Du, DuoLi Zhang, YongSheng Yin, Liang Ma, LuoFeng Geng, and YuKung Song. "FPGA prototype design of Network on Chips." In 2008 2nd International Conference on Anti-counterfeiting, Security and Identification. IEEE, 2008. http://dx.doi.org/10.1109/iwasid.2008.4688413.
Full textXiang, Xi-Yue, and Nian-Feng Tzeng. "Deflection Containment for Bufferless Network-on-Chips." In 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2016. http://dx.doi.org/10.1109/ipdps.2016.17.
Full textSarihi, Amin, Ahmad Patooghy, Mahdi Hasanzadeh, Mostafa Abdelrehim, and Abdel-Hameed A. Badawy. "Securing network-on-chips via novel anonymous routing." In NOCS '21: International Symposium on Networks-on-Chip. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3479876.3481592.
Full textSarihi, Amin, Ahmad Patooghy, Mahdi Hasanzadeh, Mostafa Abdelrehim, and Abdel-Hameed A. Badawy. "Securing network-on-chips via novel anonymous routing." In NOCS '21: International Symposium on Networks-on-Chip. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3479876.3481592.
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