Relevant bibliographies by topics / Network-on-chips

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Network-on-chips'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 September 2023

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Journal articles on the topic "Network-on-chips"

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BAHN, JUN HO, JUNG SOOK YANG, WEN-HSIANG HU, and NADER BAGHERZADEH. "PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 255–69. http://dx.doi.org/10.1142/s0218126609005046.

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This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.
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Louri, Ahmed, and Avinash Kodi. "Special Issue on Network-on-Chips (NoCs)." Journal of Parallel and Distributed Computing 70, no. 1 (January 2010): 69. http://dx.doi.org/10.1016/j.jpdc.2009.10.007.

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Szu, Harold, Jung Kim, and Insook Kim. "Live neural network formations on electronic chips." Neurocomputing 6, no. 5-6 (October 1994): 551–64. http://dx.doi.org/10.1016/0925-2312(94)90006-x.

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He, Yuan, Hiroki Matsutani, Hiroshi Sasaki, and Hiroshi Nakamura. "Adaptive Data Compression on 3D Network-on-Chips." IPSJ Online Transactions 5 (2012): 13–20. http://dx.doi.org/10.2197/ipsjtrans.5.13.

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Chen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips." Journal of Software 10, no. 2 (February 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.

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Zhang, Kunwei, and Thomas Moscibroda. "Twist-Routing Algorithm for Faulty Network-on-Chips." Journal of Computer and Communications 04, no. 14 (2016): 1–10. http://dx.doi.org/10.4236/jcc.2016.414001.

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Li, Feihui, Guangyu Chen, Mahmut Kandemir, and Ibrahim Kolcu. "Profile-driven energy reduction in network-on-chips." ACM SIGPLAN Notices 42, no. 6 (June 10, 2007): 394–404. http://dx.doi.org/10.1145/1273442.1250779.

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Chen, Yuechen, and Ahmed Louri. "An Approximate Communication Framework for Network-on-Chips." IEEE Transactions on Parallel and Distributed Systems 31, no. 6 (June 1, 2020): 1434–46. http://dx.doi.org/10.1109/tpds.2020.2968068.

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Geppert, L. "The new chips on the block [network processors]." IEEE Spectrum 38, no. 1 (January 2001): 66–68. http://dx.doi.org/10.1109/6.901145.

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Hamdi, Doaa A., Samy Ghoniemy, Yasser Dakroury, and Mohammed A. Sobh. "A Scalable Software Defined Network Orchestrator for Photonic Network on Chips." IEEE Access 9 (2021): 35371–81. http://dx.doi.org/10.1109/access.2021.3058238.

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Dissertations / Theses on the topic "Network-on-chips"

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Xiang, Xiyue. "Contention Alleviation in Network-on-Chips." Thesis, University of Louisiana at Lafayette, 2017. http://pqdtopen.proquest.com/#viewpdf?dispub=10272587.

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In a network-on-chip (NoC) based system, the NoC is a shared resource among multiple processor cores. Requests generated by different applications running on different cores can create severe contention in NoCs. This contention can jeopardize the system performance and power efficiency in many different formats. First and foremost, we discover that the contention in NoCs can induce inter-application interference, leading to overall system performance degradation, prevent fair-progress of different applications, and cause starvation of unfairly-treated applications. We propose the NoC Application Slowdown (NAS) Model, the first online model that accurately estimates how much network delays due to interference contribute to the overall stall time of each application. We use NAS to develop Fairness-Aware Source Throttling (FAST), a mechanism that employs slowdown predictions to control the network injection rates of applications in a way that minimizes system unfairness. Furthermore, although removing buffers from the constituent routers can reduce power consumption and hardware complexity, the bufferless NoC is subject to the growing deflection caused by contention, leading to severe performance degradation and squandering power-saving potential. we then propose Deflection Containment (DeC) for the bufferless NoC to address its notorious shortcoming of excessive deflection for performance improvement and power reduction. With a link added to each router for bridging subnetworks (whose aggregated link width equals a give value, say, 128b), DeC lets a contending flit in one subnetwork be forwarded to another subnetwork instead of deflected, yielding extraordinary deflection reduction and greatly enriching path diversity. In addition, router microarchitecture under DeC is rectified to shorten the critical path and lift network bandwidth. Last but not least, beside 1-to-1 flow, the growing core counts urgently requires effective hardware support to alleviate the contention caused by 1-to-many and many-to-1 flow. We propose Carpool, the very first bufferless NoC optimized for 1-to-many and many-to-1 traffic. Carpool adaptively forks new flit replicas and performs traffic aggregation at appropriate intermediate routers to lessen bandwidth demands and reduce contention. We propose the microarchitecture of Carpool routers and develop parallel port allocation which supports multicast and reduces critical paths to improve network bandwidth.

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Kwa, Jimmy Williamchingyuan. "Optimizing network-on-chips for FPGAs." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44343.

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As larger System-on-Chip (SoC) designs are attempted on Field Programmable Gate Arrays (FPGAs), the need for a low cost and high performance Network-on-Chip (NoC) grows. Virtual Channel (VC) routers provide desirable traits for an NoC such as higher throughput and deadlock prevention but at significant resource cost when implemented on an FPGA. This thesis presents an FPGA specific optimization to reduce resource utilization. We propose sharing Block RAMs between multiple router ports to store the high logic resource consuming VC buffers and present the Block RAM Split (BRS) router architecture that implements the proposed optimization. We evaluate the performance of the modifications using synthetic traffic patterns on mesh and torus networks and synthesize the NoCs to determine overall resource usage and maximum clock frequency. We find that the additional logic to support sharing Block RAMs has little impact on Adaptive Logic Module (ALM) usage in designs that currently use Block RAMs while at the same time decreasing Block RAM usage by as much as 40%. In comparison to CONNECT, a router design that does not use Block RAMs, a 71% reduction in ALM usage is shown to be possible. This resource reduction comes at the cost of a 15% reduction in the saturation throughput for uniform random traffic and a 50% decrease in the worst case neighbour traffic pattern on a mesh network. The throughput penalty from the neighbour traffic pattern can be reduced to 3% if a torus network is used. In all cases, there is little change in network latency at low load. BRS is capable of running at 161.71 MHz which is a decrease of only 4% from the base VC router design. Determining the optimum NoC topology is a challenging task. This thesis also proposes initial work towards the creation of an analytical model to assist with finding the best topology to use in an FPGA NoC.
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Bakhoda, Ali. "Designing network-on-chips for throughput accelerators." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/46423.

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Physical limits of power usage for integrated circuits have steered the microprocessor industry towards parallel architectures in the past decade. Modern Graphics Processing Units (GPU) are a form of parallel processor that harness chip area more effectively compared to traditional single threaded architectures by favouring application throughput over latency. Modern GPUs can be used as throughput accelerators: accelerating massively parallel non-graphics applications. As the number of compute cores in throughput accelerators increases, so does the importance of efficient memory subsystem design. In this dissertation, we present system-level microarchitectural analysis and optimizations with an emphasis on the memory subsystem of throughput accelerators that employ Bulk-Synchronous-Parallel programming models such as CUDA and OpenCL. We model the whole throughput accelerator as a closed-loop system in order to capture the effects of complex interactions of microarchitectural components: we simulate components such as compute cores, on-chip network and memory controllers with cycle-level accuracy. For this purpose, the first version of GPGPU-Sim simulator that was capable of running unmodified applications by emulating NVIDIA's virtual instruction set was developed. We use this simulator to model and analyze several applications and explore various microarchitectural tradeoffs for throughput accelerators to better suit these applications. Based on our observations, we identify the Network-on-Chip (NoC) component of memory subsystem as our main optimization target and set out to design throughput effective NoCs for future throughput accelerators. We provide a new framework for NoC researchers to ensure the optimizations are "throughput effective", namely, parallel application-level performance improves per unit chip area. We then use this framework to guide the development of several optimizations. Accelerator workloads demand high off-chip memory bandwidth resulting in a many-to-few-to-many traffic pattern. Leveraging this observation, we reduce NoC area by proposing a checkerboard NoC which utilizes routers with limited connectivity. Additionally, we improve performance by increasing the terminal bandwidth of memory controller nodes to better handle frequent read-reply traffic. Furthermore, we propose a double checkerboard inverted NoC organization which maintains the benefits of these optimizations while having a simpler routing mechanism and smaller area and results in a 24.3% improvement in average application throughput per unit area.
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Pattabiraman, Aishwariya. "Heterogeneous Cache Architecture in Network-on-Chips." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1321371508.

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Sarkar, Souradip. "Multiple clock domain synchronization for network on chips." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/S_Sarkar_112907.pdf.

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Alshraiedeh, Juman. "Wear-out Leveling in Network on Chips (NoCs)." Ohio University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1492677926079357.

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Bhardwaj, Kshitij. "Aging-Aware Routing Algorithms for Network-on-Chips." DigitalCommons@USU, 2012. https://digitalcommons.usu.edu/etd/1319.

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Network-on-Chip (NoC) architectures have emerged as a better replacement of the traditional bus-based communication in the many-core era. However, continuous technology scaling has made aging mechanisms, such as Negative Bias Temperature Instability (NBTI) and electromigration, primary concerns in NoC design. In this work, a novel system-level aging model is proposed to model the effects of aging in NoCs, caused due to (a) asymmetric communication patterns between the network nodes, and (b) runtime traffic variations due to routing policies. This work observes a critical need of a holistic aging analysis, which when combined with power-performance optimization, poses a multi-objective design challenge. To solve this problem, two different aging-aware routing algorithms are proposed: (a) congestion-oblivious Mixed Integer Linear Programming (MILP)-based routing algorithm, and (b) congestion-aware adaptive routing algorithm and router micro-architecture. After extensive experimental evaluations, proposed routing algorithms reduce aging-induced power-performance overheads while also improving the system robustness.
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Zhang, Yixuan. "High-Performance Crossbar Designs for Network-on-Chips (NoCs)." Ohio University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1282056856.

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Boraten, Travis Henry. "Hardware Security Threat and Mitigation Techniques for Network-on-Chips." Ohio University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173.

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Boraten, Travis H. "Runtime Adaptive Scrubbing in Fault-Tolerant Network-on-Chips (NoC) Architectures." Ohio University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488496.

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Books on the topic "Network-on-chips"

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Fayez, Gebali, Elmiligi Haytham, and El-Kharashi Mohamed Watheq, eds. Networks-on-chips: Theory and practice. Boca Raton: Taylor & Francis, 2009.

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service), SpringerLink (Online, ed. Designing Reliable and Efficient Networks on Chips. Dordrecht: Springer Netherlands, 2009.

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Power-Efficient Network-on-Chips: Design and Evaluation. Elsevier, 2022. http://dx.doi.org/10.1016/s0065-2458(22)x0002-8.

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Gebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2017.

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Gebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2011.

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Gebali, Fayez, Haytham Elmiligi, and Mohamed Watheq El-Kharashi. Networks-on-Chips: Theory and Practice. Taylor & Francis Group, 2009.

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Murali, Srinivasan. Designing Reliable and Efficient Networks on Chips. Springer, 2010.

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Book chapters on the topic "Network-on-chips"

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Shruthi, R., H. R. Shashidhara, and M. S. Deepthi. "Comprehensive Survey on Wireless Network on Chips." In Algorithms for Intelligent Systems, 203–18. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-5747-4_18.

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Friederich, Stephanie, Niclas Lehmann, and Jürgen Becker. "Adaptive Bandwidth Router for 3D Network-on-Chips." In Lecture Notes in Computer Science, 352–60. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30481-6_30.

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Silva, Luneque, Nadia Nedjah, Luiza de Macedo Mourelle, and Fábio Gonçalves Pessanha. "ACO-Based Static Routing for Network-on-Chips." In Computational Science and Its Applications – ICCSA 2012, 113–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31125-3_9.

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Nedjah, Nadia, and Luiza de Macedo Mourelle. "Routing in Network-on-Chips Using Ant Colony Optimization." In Hardware for Soft Computing and Soft Computing for Hardware, 173–98. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03110-1_11.

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Urkude, Vijaykumar R. "Design Optimization and Fault Tolerance in Network-On-Chips." In Algorithms for Intelligent Systems, 511–19. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6307-6_51.

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Frieb, Martin, Alexander Stegmeier, Jörg Mische, and Theo Ungerer. "Lightweight Hardware Synchronization for Avoiding Buffer Overflows in Network-on-Chips." In Lecture Notes in Computer Science, 112–26. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77610-1_9.

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Runge, Armin, and Reiner Kolla. "An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips." In Architecture of Computing Systems – ARCS 2016, 48–59. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_4.

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Cai, Yuan, and Xiang Ji. "ASA-routing: A-Star Adaptive Routing Algorithm for Network-on-Chips." In Algorithms and Architectures for Parallel Processing, 187–98. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-05054-2_14.

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Li, Jiazheng, Guozhi Song, Yue Ma, Cheng Wang, Baohui Zhu, Yan Chai, and Jieqi Rong. "Bat Algorithm Based Low Power Mapping Methods for 3D Network-on-Chips." In Communications in Computer and Information Science, 277–95. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6893-5_21.

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Dai, Fei, Yawen Chen, Zhiyi Huang, and Haibo Zhang. "Performance Comparison of Multi-layer Perceptron Training on Electrical and Optical Network-on-Chips." In Parallel and Distributed Computing, Applications and Technologies, 129–41. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-96772-7_13.

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Conference papers on the topic "Network-on-chips"

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Diguet, Jean-Philippe. "Self-Adaptive Network On Chips." In the 27th Symposium. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2660540.2660992.

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Ebrahimi, Masoumeh, Masoud Daneshtalab, N. P. Sreejesh, Pasi Liljeberg, and Hannu Tenhunen. "Efficient network interface architecture for network-on-chips." In 2009 NORCHIP. IEEE, 2009. http://dx.doi.org/10.1109/norchp.2009.5397837.

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Bahn, Jun Ho, Jungsook Yang, and Nader Bagherzadeh. "Parallel FFT Algorithms on Network-on-Chips." In 2008 Fifth International Conference on Information Technology: New Generations (ITNG). IEEE, 2008. http://dx.doi.org/10.1109/itng.2008.55.

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Joseph, Jan Moritz, Dominik Ermel, Lennart Bamberg, Alberto Garcia Oritz, and Thilo Pionteck. "System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips." In 2019 IEEE 37th International Conference on Computer Design (ICCD). IEEE, 2019. http://dx.doi.org/10.1109/iccd46524.2019.00064.

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Kendaganna Swamy S, Anil N, Anand Jatti, and Uma B V. "Platform level design for Network on Chips." In 2015 IEEE International Advance Computing Conference (IACC). IEEE, 2015. http://dx.doi.org/10.1109/iadcc.2015.7154676.

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Pereñíguez-García, Fernando, and José L. Abellán. "Secure communications in wireless network-on-chips." In AISTECS '17: 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3073763.3073768.

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GaoMing Du, DuoLi Zhang, YongSheng Yin, Liang Ma, LuoFeng Geng, and YuKung Song. "FPGA prototype design of Network on Chips." In 2008 2nd International Conference on Anti-counterfeiting, Security and Identification. IEEE, 2008. http://dx.doi.org/10.1109/iwasid.2008.4688413.

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Xiang, Xi-Yue, and Nian-Feng Tzeng. "Deflection Containment for Bufferless Network-on-Chips." In 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2016. http://dx.doi.org/10.1109/ipdps.2016.17.

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Sarihi, Amin, Ahmad Patooghy, Mahdi Hasanzadeh, Mostafa Abdelrehim, and Abdel-Hameed A. Badawy. "Securing network-on-chips via novel anonymous routing." In NOCS '21: International Symposium on Networks-on-Chip. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3479876.3481592.

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Sarihi, Amin, Ahmad Patooghy, Mahdi Hasanzadeh, Mostafa Abdelrehim, and Abdel-Hameed A. Badawy. "Securing network-on-chips via novel anonymous routing." In NOCS '21: International Symposium on Networks-on-Chip. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3479876.3481592.

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