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Journal articles on the topic 'Network-on-chips'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 September 2023

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1

BAHN, JUN HO, JUNG SOOK YANG, WEN-HSIANG HU, and NADER BAGHERZADEH. "PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 255–69. http://dx.doi.org/10.1142/s0218126609005046.

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This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

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2

Louri, Ahmed, and Avinash Kodi. "Special Issue on Network-on-Chips (NoCs)." Journal of Parallel and Distributed Computing 70, no. 1 (January 2010): 69. http://dx.doi.org/10.1016/j.jpdc.2009.10.007.

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3

Szu, Harold, Jung Kim, and Insook Kim. "Live neural network formations on electronic chips." Neurocomputing 6, no. 5-6 (October 1994): 551–64. http://dx.doi.org/10.1016/0925-2312(94)90006-x.

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4

He, Yuan, Hiroki Matsutani, Hiroshi Sasaki, and Hiroshi Nakamura. "Adaptive Data Compression on 3D Network-on-Chips." IPSJ Online Transactions 5 (2012): 13–20. http://dx.doi.org/10.2197/ipsjtrans.5.13.

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5

Chen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips." Journal of Software 10, no. 2 (February 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.

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6

Zhang, Kunwei, and Thomas Moscibroda. "Twist-Routing Algorithm for Faulty Network-on-Chips." Journal of Computer and Communications 04, no. 14 (2016): 1–10. http://dx.doi.org/10.4236/jcc.2016.414001.

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7

Li, Feihui, Guangyu Chen, Mahmut Kandemir, and Ibrahim Kolcu. "Profile-driven energy reduction in network-on-chips." ACM SIGPLAN Notices 42, no. 6 (June 10, 2007): 394–404. http://dx.doi.org/10.1145/1273442.1250779.

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8

Chen, Yuechen, and Ahmed Louri. "An Approximate Communication Framework for Network-on-Chips." IEEE Transactions on Parallel and Distributed Systems 31, no. 6 (June 1, 2020): 1434–46. http://dx.doi.org/10.1109/tpds.2020.2968068.

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9

Geppert, L. "The new chips on the block [network processors]." IEEE Spectrum 38, no. 1 (January 2001): 66–68. http://dx.doi.org/10.1109/6.901145.

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10

Hamdi, Doaa A., Samy Ghoniemy, Yasser Dakroury, and Mohammed A. Sobh. "A Scalable Software Defined Network Orchestrator for Photonic Network on Chips." IEEE Access 9 (2021): 35371–81. http://dx.doi.org/10.1109/access.2021.3058238.

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11

Ge, Mengke, Xiaobing Ni, Xu Qi, Song Chen, Jinglei Huang, Yi Kang, and Feng Wu. "Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–30. http://dx.doi.org/10.1145/3480961.

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Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this article, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. First, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired network-on-chips (NoCs) generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.

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12

Mak, Terrence, Peter Y. K. Cheung, Kai-Pui Lam, and Wayne Luk. "Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network." IEEE Transactions on Industrial Electronics 58, no. 8 (August 2011): 3701–16. http://dx.doi.org/10.1109/tie.2010.2081953.

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13

Dehyadegari, Masoud, Siamak Mohammadi, and Naser Yazdani. "Distributed fair DRAM scheduling in network-on-chips architecture." Journal of Systems Architecture 59, no. 7 (August 2013): 543–50. http://dx.doi.org/10.1016/j.sysarc.2013.03.004.

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14

Abdollahi, Meisam, and Siamak Mohammadi. "Vulnerability assessment of fault-tolerant optical network-on-chips." Journal of Parallel and Distributed Computing 145 (November 2020): 140–59. http://dx.doi.org/10.1016/j.jpdc.2020.06.016.

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15

Zhang, Lei, Mei Yang, Yingtao Jiang, and Emma Regentova. "Architectures and routing schemes for optical network-on-chips." Computers & Electrical Engineering 35, no. 6 (November 2009): 856–77. http://dx.doi.org/10.1016/j.compeleceng.2008.09.010.

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16

Shafaghi, Setareh, Mohammad Shokouhifar, and Reza Sabbaghi-Nadooshan. "Swarm Intelligence Low Power Routing in Network-on-Chips." International Journal of Energy, Information and Communications 7, no. 2 (April 30, 2016): 21–40. http://dx.doi.org/10.14257/ijeic.2016.7.2.03.

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17

Kumar, MPawan, Srinivasan Murali, and Kamakoti Veezhinathan. "Network-on-chips on 3-D ICs: Past, present, and future." IETE Technical Review 29, no. 4 (2012): 318. http://dx.doi.org/10.4103/0256-4602.101313.

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18

Zhao, Jianwu, Yibing Shi, and Zhigang Wang. "Research on test strategy for hierarchical network-on-chips interconnection infrastructure." JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT 2009, no. 5 (December 9, 2009): 34–39. http://dx.doi.org/10.3724/sp.j.1187.2009.05034.

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19

Mansouri, Imen, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, and Gilles Sassatelli. "Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips." Journal of Low Power Electronics 6, no. 4 (December 1, 2010): 564–77. http://dx.doi.org/10.1166/jolpe.2010.1106.

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20

GHAREHBAGHI, Amir Masoud, and Masahiro FUJITA. "Transaction Ordering in Network-on-Chips for Post-Silicon Validation." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A, no. 12 (2012): 2309–18. http://dx.doi.org/10.1587/transfun.e95.a.2309.

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21

ZHONG, Wei, Song CHEN, Bo HUANG, Takeshi YOSHIMURA, and Satoshi GOTO. "Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96.A, no. 6 (2013): 1174–84. http://dx.doi.org/10.1587/transfun.e96.a.1174.

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22

Wang, Junshi, Letian Huang, Guangjun Li, and Axel Jantsch. "Calculation of delivery rate in fault‐tolerant network‐on‐chips." Electronics Letters 52, no. 7 (April 2016): 546–48. http://dx.doi.org/10.1049/el.2015.2803.

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23

Tan, Xianfang, Mei Yang, Lei Zhang, Yingtao Jiang, and Jianyi Yang. "A Generic Optical Router Design for Photonic Network-on-Chips." Journal of Lightwave Technology 30, no. 3 (February 2012): 368–76. http://dx.doi.org/10.1109/jlt.2011.2178019.

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24

Yintang, Yang, Guan Xuguang, Zhou Duan, and Zhu Zhangming. "A full asynchronous serial transmission converter for network-on-chips." Journal of Semiconductors 31, no. 4 (April 2010): 045007. http://dx.doi.org/10.1088/1674-4926/31/4/045007.

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25

Hassanpour, Neda, Shaahin Hessabi, and Parisa Khadem Hamedani. "Temperature control in three‐network on chips using task migration." IET Computers & Digital Techniques 7, no. 6 (November 2013): 274–81. http://dx.doi.org/10.1049/iet-cdt.2013.0016.

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26

Said, Mostafa, Ahmed Shalaby, and Fayez Gebali. "Thermal-aware network-on-chips: Single- and cross-layered approaches." Future Generation Computer Systems 91 (February 2019): 61–85. http://dx.doi.org/10.1016/j.future.2018.08.041.

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27

Shen, Xuefei, Yi Yang, Shanshan Tian, Yu Zhao, and Tao Chen. "Microfluidic array chip based on excimer laser processing technology for the construction of in vitro graphical neuronal network." Journal of Bioactive and Compatible Polymers 35, no. 3 (May 2020): 228–39. http://dx.doi.org/10.1177/0883911520918395.

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To construct a graphical neural network in vitro and explore the morphological effects of neural network structural changes on neurons, this study aimed to introduce a method for fabricating microfluidic array chips with different graphical structures based on 248-nm excimer laser one-step etching. Through the comparative analysis of the graphical neural network cultured on our microfluidic array chip with the one on the glass slide, the morphological effects of the neural network on the morphology of the neurons were studied. First, the design of the chip was completed according to the specific structure of the neurons and the simulation of the flow field. The chips were fabricated by excimer laser processing combined with the casting technology. Neurons were cultured on the chip, and a graphical neural network was formed. The growth status of the neural network was analyzed by microscopy and immunofluorescence technology, and compared with the random neural network cultured on glass slides. The results showed that the neurons on the array chips grew in microchannels, and neurites grew along the direction of the channel, interlacing to form a neural network. Furthermore, when the structure of the neural network was graphically changed, the internal neuron morphology changed: on the same culture days, the maximum length of the neurites of the graphical neural network was higher than the average length of the neurites of the random neural network. This research can provide the foundation for the exploration of the neural network mechanism of neurological diseases.

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28

Tahanian, Esmaeel, Alireza Tajary, Mohsen Rezvani, and Mansoor Fateh. "Scalable THz Network-On-Chip Architecture for Multichip Systems." Journal of Computer Networks and Communications 2020 (December 10, 2020): 1–15. http://dx.doi.org/10.1155/2020/8823938.

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While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture. In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips. Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication. The low-loss property of this waveguide lets us increase the number of chips. Each chip has a wireless node as a gateway for communicating with other chips. To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm. Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one. Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8 % , while for millimeter-wave NoC, this reduction is about 21 % . Furthermore, the average latency growth of our system is only 1 % compared with about 40 % increase for the millimeter-wave NoC.

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29

Zipf, Peter, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, and Manfred Glesner. "A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/453970.

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We present a heuristic algorithm for the run-time distribution of task sets in a homogeneous Multiprocessor network-on-chip. The algorithm is itself distributed over the processors and thus can be applied to systems of arbitrary size. Also, tasks added at run-time can be handled without any difficulty, allowing for inline optimisation. Based on local information on processor workload, task size, communication requirements, and link contention, iterative decisions on task migrations to other processors are made. The mapping results for several example task sets are first compared with those of an exact (enumeration) algorithm with global information for a processor array. The results show that the mapping quality achieved by our distributed algorithm is within 25% of that of the exact algorithm. For larger array sizes, simulated annealing is used as a reference and the behaviour of our algorithm is investigated. The mapping quality of the algorithm can be shown to be within a reasonable range (below 30% mostly) of the reference. This adaptability and the low computation and communication overhead of the distributed heuristic clearly indicate that decentralised algorithms are a favourable solution for an automatic task distribution.

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30

Remis, Luis, Maria Jesus Garzaran, Rafael Asenjo, and Angeles Navarro. "Exploiting social network graph characteristics for efficient BFS on heterogeneous chips." Journal of Parallel and Distributed Computing 120 (October 2018): 282–94. http://dx.doi.org/10.1016/j.jpdc.2017.11.003.

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31

Patooghy, Ahmad, Seyed Ghassem Miremadi, and Mahdi Fazeli. "A low-overhead and reliable switch architecture for Network-on-Chips." Integration 43, no. 3 (June 2010): 268–78. http://dx.doi.org/10.1016/j.vlsi.2010.02.003.

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32

Taassori, Mehdi, and Sener Uysal. "Power-aware Meta-heuristic Core Mapping Approaches for Network on Chips[." International Journal of Scientific and Engineering Research 6, no. 9 (September 25, 2015): 834–37. http://dx.doi.org/10.14299/ijser.2015.09.007.

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33

Karanth, Avinash, Savas Kaya, Ashif Sikder, Daniel Carbaugh, Soumyasanta Laha, Dominic DiTomaso, Ahmed Louri, Hao Xin, and Junqiang Wu. "Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies." IEEE Transactions on Sustainable Computing 4, no. 3 (July 1, 2019): 293–307. http://dx.doi.org/10.1109/tsusc.2018.2861362.

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34

Daneshtalab, M., M. Ebrahimi, S. Mohammadi, and A. Afzali-Kusha. "Low-distance path-based multicast routing algorithm for network-on-chips." IET Computers & Digital Techniques 3, no. 5 (2009): 430. http://dx.doi.org/10.1049/iet-cdt.2008.0086.

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35

Papa, David, Charles Alpert, Cliff Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, and Igor Markov. "Physical Synthesis with Clock-Network Optimization for Large Systems on Chips." IEEE Micro 31, no. 4 (July 2011): 51–62. http://dx.doi.org/10.1109/mm.2011.41.

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36

Tosun, Suleyman, Vahid B. Ajabshir, Ozge Mercanoglu, and Ozcan Ozturk. "Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 9 (September 2015): 1495–508. http://dx.doi.org/10.1109/tcad.2015.2413848.

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37

Chen, Song, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, and Feng Wu. "Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 6 (June 2020): 1191–204. http://dx.doi.org/10.1109/tcad.2019.2952134.

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38

Chen, Yuechen, and Ahmed Louri. "Learning-Based Quality Management for Approximate Communication in Network-on-Chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 11 (November 2020): 3724–35. http://dx.doi.org/10.1109/tcad.2020.3012235.

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39

Rezvani, Mohsen, Alireza Tajary, and Esmaeel Tahanian. "Game-based congestion-aware routing algorithm in wireless network on chips." International Journal of Ad Hoc and Ubiquitous Computing 42, no. 4 (2023): 258. http://dx.doi.org/10.1504/ijahuc.2023.10055687.

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40

Tahanian, Esmaeel, Alireza Tajary, and Mohsen Rezvani. "Game-based congestion-aware routing algorithm in wireless network on chips." International Journal of Ad Hoc and Ubiquitous Computing 42, no. 4 (2023): 258. http://dx.doi.org/10.1504/ijahuc.2023.130465.

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41

ZHONG, Wei, Takeshi YOSHIMURA, Bei YU, Song CHEN, Sheqin DONG, and Satoshi GOTO. "Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips." IEICE Transactions on Electronics E95-C, no. 4 (2012): 534–45. http://dx.doi.org/10.1587/transele.e95.c.534.

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42

Sarihi, Amin, Ahmad Patooghy, Ahmed Khalid, Mahdi Hasanzadeh, Mostafa Said, and Abdel-Hameed A. Badawy. "A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips." IEEE Access 9 (2021): 107625–56. http://dx.doi.org/10.1109/access.2021.3100540.

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43

Kalimuthu, A., and M. Karthikeyan. "NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 105. http://dx.doi.org/10.11591/ijres.v6.i2.pp105-110.

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<span style="font-size: 9pt; font-family: 'Times New Roman', serif;">A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique</span>

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44

Li, Jiashen, and Yun Pan. "Optimal scheduling algorithms of system chip power density based on network on chip." Izvestiya vysshikh uchebnykh zavedenii. Fizika, no. 9 (2021): 120–27. http://dx.doi.org/10.17223/00213411/64/9/120.

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The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

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45

Muthulakshmi, M., and A. James Albert. "Hybrid Adaptive Routing in Network-on-chips Using KLSA with Dijkstra Algorithm." Research Journal of Applied Sciences, Engineering and Technology 8, no. 21 (December 5, 2014): 2211–19. http://dx.doi.org/10.19026/rjaset.8.1220.

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46

Chen, Yong, Emil Matus, Sadia Moriam, and Gerhard P. Fettweis. "High Performance Dynamic Resource Allocation for Guaranteed Service in Network-on-Chips." IEEE Transactions on Emerging Topics in Computing 8, no. 2 (April 1, 2020): 503–16. http://dx.doi.org/10.1109/tetc.2017.2765825.

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47

Tan, Wei, Huaxi Gu, Yintang Yang, Meaad Fadhel, and Bowen Zhang. "Network Condition-Aware Communication Mechanism for Circuit-Switched Optical Networks-on-Chips." Journal of Optical Communications and Networking 8, no. 10 (September 30, 2016): 813. http://dx.doi.org/10.1364/jocn.8.000813.

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48

Sabbaghi-Nadooshan, Reza. "Analytical performance modeling of shuffle–exchange inspired mesh-based Network-on-Chips." Performance Evaluation 70, no. 11 (November 2013): 934–47. http://dx.doi.org/10.1016/j.peva.2013.06.002.

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49

Jafri, Syed M. A. H., Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, and Hannu Tenhunen. "Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes." Microprocessors and Microsystems 37, no. 8 (November 2013): 811–22. http://dx.doi.org/10.1016/j.micpro.2013.04.005.

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50

Sabbaghi-Nadooshan, Reza, and Ahmad Patooghy. "Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips." Microprocessors and Microsystems 39, no. 1 (February 2015): 27–36. http://dx.doi.org/10.1016/j.micpro.2014.12.002.

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