Dissertations / Theses on the topic 'Neutral-point-clamped Inverter'

Multilevel converters have seen an increasing popularity in the last years for medium- and high-voltage applications. The most popular has been the three-level neutral clamped converter and still research is going on to improve the control of it. This master thesis was a continuation of the specialization project fall 2009. The main topics of current thesis were to further investigate the DC-bus balancing issues, compare symmetrical (one sampling per triangular wave) and asymmetrical (sampling at the top and bottom of the triangular wave) modulation, derive current equations for Space Vector and Double-Signal, improve output voltage in overmodulation and be able to DC-bus balance, and to implement the methods in the laboratory. Models of the three-level converter were made in the specialization project in both PSCAD and SIMULINK and further studies of the DC-bus balance were also made in this master thesis. None of the methods showed problems to regulate the DC-bus voltage when there was different capacitor values and unsymmetrical load. A PI controller was introduced for Space Vector but it did not show better performance than a regular P regulator. Asymmetrical modulation showed a clearly better performance than symmetrical modulation when the switching frequency was low compared to the fundamental frequency, especially for Space Vector. The 1st harmonic line-to-line voltage was closer to the wanted value and the THDi was significantly lower. Simulations also showed that the THDi can vary significantly depending on at which angle the first sampling is done. This is most clear for asymmetrical Space Vector modulation, but also for the other cases this pattern occurs. By implementing an overmodulation algorithm the amplitude of the 1st harmonic output voltage was closer to what was desired. Simulations showed how important it was to have three phase sampling symmetry in overmodulation. By having a wrong switching frequency the line-to-line output voltage dropped down to 2.06 when operating in six-step, when the wanted output value should be 2.205. Hence there is a quite large mismatch and the converter is sensitive to the switching frequency when it is operating in the higher modulation area. The balancing algorithm introduced for overmodulation is able to remove an initial offset without a notable change the 1st harmonic output. Both Space Vector and Double-Signal were tested in the laboratory with two separated DC-sources. Asymmetrical and Symmetrical modulation were tested and so was also overmodulation. The laboratory results confirmed the simulated results, but since the switching was not synchronized in the laboratory, some errors occurred.

This thesis investigates a novel DC/AC resonant inverter of Induction Heating (IH) system presenting a Multilevel Neutral Point Clamped (MNPCI) topology, as a new part of power supply design. The main function of the prototype is to provide a maximum and steady state power transfer from converter to the resonant load tank, by achieving zero current switching (ZCS) with selecting the best design of load tank topology, and utilizing the advantage aspects of both the Voltage Fed Inverter (VFI) and Current Fed Inverter (CFI) kinds, therefore it can considered as a hybrid-inverter (HVCFI) category . The new design benefits from series resonant inverter design through using two bulk voltage source capacitors to feed a constant voltage delivery to the MNPCI inverter with half the DC rail voltage to decrease the switching losses and mitigate the over voltage surge occurred in inverter switches during operation which may cause damage when dealing with high power systems. Besides, the design profits from the resonant load topology of parallel resonant inverter, through using the LLC resonant load tank. The design gives the advantage of having an output current gain value of about Quality Factor (Q) times the inverter current and absorbs the parasitic components. On the contrary, decreasing inverter current means decreasing the switching frequency and thus, decreasing the switching losses of the system. This aspect increases the output power, which increases the heating efficiency. In order for the proposed system to be more reliable and matches the characteristics of IH process , the prototype is modelled with a variable LLC topology instead of fixed load parameters with achieving soft switching mode of ZCS and zero voltage switching (ZVS) at all load conditions and a tiny phase shift angle between output current and voltage, which might be neglected. To achieve the goal of reducing harmonic distortion, a new harmonic control modulation is introduced, by controlling the ON switching time to obtain minimum Total Harmonic Distortion (THD) content accompanied with optimum power for heating energy.

In this thesis, the neutral point potential drift/fluctuation of the three-level neutral point clamped inverter is analyzed and a novel control algorithm, the two-parameter PWM method is proposed to confine the neutral point potential variation to a very small range. The two-parameter PWM method provides superior neutral point potential control performance even with small DC bus capacitors. The method is based on PWM pulse pattern modification and requires no additional hardware. Detailed analytical models of the neutral point current and potential as a function of the modulation parameters are established and the neutral point potential behavior is thoroughly investigated. Based on the study, the deficiency of the known methods is illustrated and the two-parameter PWM method is developed and its superior performance demonstrated. The performance of the two-parameter PWM method is verified by means of computer simulations utilizing both the per-PWM-cycle average model and the detailed model of the inverter. The results are supported by laboratory experiments involving both an R-L load and an induction motor drive.

In this thesis, field oriented control of permanent magnet synchronous motors using three-level neutral-point-clamped inverter is studied. Permanent magnet synchronous motors are used in high performance drive applications. In this study, the permanent magnet synchronous motor is fed by three-level neutral-point-clamped inverter. For three-level neutral-point-clamped inverter different space vector modulation algorithms, which are reported in literature, are analyzed and compared via computer simulations. The voltage balance on dc-link capacitors is also analyzed and a software control method is implemented in conjunction with the space vector PWM modulation, utilized. Nonlinear effects such as dead-time, semiconductor voltage drop and delays in gate drive circuitries also present in neutral-point-clamped inverter. The effects of these nonlinearities are studied and a compensation method for these nonlinear effects is proposed. The theoretical results are supported with computer simulations and verified with experimental results.

Power inverters, used to convert DC power to AC, are often used in e.g. solar power applications. However, they tend to be impractically large and expensive; as such, power miniaturization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to identify areas of potential improvement. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped inverter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while remaining smaller than an average textbook.

Das Ziel der Arbeit war die Untersuchung eines neuartigen Phasenbausteins mit der Topologie des Dreipunkt – Neutral Point Clamped – Stromrichters mit Spannungszwischenkreis (3L-NPC-VSC) für Windkraftanwendungen. Wichtige Anforderungen an den Phasenbaustein und daraus resultierende Herausforderungen, sowie Lösungen für ausgewählte Teilprobleme werden präsentiert. Um die Vorteile des 3L-NPC-VSC für Hersteller von Windkraftanlagen zugänglich zu machen, ist es sinnvoll, einen neuartigen Phasenbaustein zu entwickeln. Der Phasenbaustein soll einfach in Systeme zu integrieren sein, in denen gegenwärtig Zweipunktstromrichter (2L-VSC) zum Einsatz kommen. Da sich Modulation, Zwischenkreisbalancierung und Kurzschlussschutz vom 2L-VSC unterscheiden, soll der Phasenbaustein diese Herausforderungen eigenständig bewältigen. Die Arbeit beschreibt die Konzeption eines solchen Phasenbausteins und behandelt insbesondere die Modulation, die Zwischenkreisbalancierung und den Kurzschlussschutz des 3L-NPC-VSC. Ein Vergleich verschiedener Modulationsverfahren wurde durchgeführt und die am besten geeigneten Verfahren für die Implementation in den Phasenbaustein ausgewählt. Eine Anforderung war, dass dieser Signale einer übergeordneten Regelung verarbeiten kann, welche für einen 2L-VSC berechnet wurden. Ein Überblick der Zwischenkreisbalancierungsverfahren zeigte, dass nahezu alle den Nachteil einer zusätzlich benötigten Strommessung haben. Die Untersuchung einer neuen an der Professur Leistungselektronik der TU Dresden entwickelten Methode ohne den Bedarf der Strommessung zeigte, dass diese anwendbar ist. Der Algorithmus wurde simuliert, implementiert und experimentell getestet und zeigte gute Resultate. Die Aufgabe eines komplett unabhängigen Kurzschlussschutzes war die schwierigste. Alle möglichen Fehler innerhalb eines Moduls wurden analysiert und kategorisiert. Einige Fehlertypen können innerhalb einer Phase behandelt werden. Entsprechende Algorithmen wurden entwickelt und getestet. Allerdings gibt es Fehlertypen, die nicht durch die Steuerung einer einzelnen Phase behandelt werden können. Eine schnelle Kommunikation zwischen den drei Phasen des Konverters wäre notwendig. Alternativ könnte eine übergeordnete Steuerung diese Fehler behandeln. Zum Schluss wurde ein Demonstrator des Phasenbausteins aufgebaut und experimentell untersucht. Einige Messergebnisse werden gezeigt, um die Funktion zu verifizieren.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
The main subject of this work is the study of a 5 levels T-Type NPC inverter topology, which is applied in photovoltaic energy processing for power generation. The grid power injection is done controlling converter current, which is injected into grid. This work presents equations, component-designs and their validation, which are necessary for the Inverter s power structure implementation. Also inverter modeling and design of implemented controllers are described. Through this study, it was possible to build a 3 kW prototype, which besides the current control, has a system to balance the differential voltage of bus capacitors. Through the prototype, experimental results were acquired.
O objeto de estudo deste trabalho é a topologia inversora NPC T-Type 5 níveis, aplicada no processamento da energia fotovoltaica, sendo o principal objetivo a geração de energia elétrica por meio do controle da corrente aplicada à rede. Este trabalho apresenta o equacionamento, projeto dos componentes e sua validação, que fazem parte da estrutura de potência do inversor, bem como a sua modelagem e projeto dos controladores implementados. Por intermédio deste estudo foi possível construir um protótipo com potência nominal de 3 kW, que além do controle da corrente, apresenta uma malha de equilíbrio da tensão diferencial do barramento. Mediante construção desse protótipo, foram extraídos os resultados experimentais.

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores
Multi-level converters have been receiving attention in the recent years and have been proposed as the best choice in a wide variety of medium voltage applications. They enable a commutation at substantially reduced voltages and an improved harmonic spectrum without a series connection of devices, which is the main advantage of a multi-level structure. The use of multi-level inverters contributes to the performances amelioration of the induction machine control. In fact, the use of three level inverter (or multilevel inverter) associated with DTC control can contribute to more reducing harmonics and the ripple torque and to have a high level of output voltage. A variation of DTC-SVM with a three level neutral point clamped inverter is proposed and discussed in the literature. The goal of this project is to study, evaluate and compare the DTC and the proposed DTC-SVM technique when applied to induction machines through simulations. The simulations were carried out using MATLAB/ SIMULINK simulation package. Evaluation was made based on the drive performance, which includes dynamic torque and flux responses, feasibility and the complexity of the systems.

Thesis (MScEng)--University of Stellenbosch, 2003.
ENGLISH ABSTRACT: The three-level neutral-point-clamped(NPC) converter, being a widely used multilevel inverter, received a lot of attention recently due to problems associated with de-link capacitor voltage balancing. There are mainly two problems associated with the neutralpoint voltage of the NPC inverter: 1. At high modulation indices a low frequency ripple occurs on the neutral-point voltage. 2. Steady-state unbalance in the neutral-point voltage may arise due to a variety of factors including component imperfections, transients and other non-idealities and imbalances. In this thesis we study the balancing problem with focus on the steady-state imbalance. This is achieved by a systematic and mathematically rigorous study of the natural balancing mechanisms of the three-level three-phase NPC inverter. Orthogonality of two sets of switching spectra in the frequency domain would imply that the DC-bus voltages balance in the steady state. This is done through mathematical analysis using Carrara's PWM strategy of alternative phase opposition disposition(APOD), phase opposition disposition( POD) and phase disposition(PD); and Bennet's geometric model for double Fourier series adapted for use with power converter systems by Bowes. The theory is verified through simulation.
AFRIKAANSE OPSOMMING: Aangesien die drie-vlak, geklemde, neutrale-punt omsetter(NPC) 'n algemene omsetter konfigurasie is, is daar onlangs baie aandag gegee aan die probleme wat geassosieer word met die balansering van die omsetter se gelykstroombuskapasitorspanning. Die twee hoof probleme wat gepaart gaan met die neutraalpuntspanning van die NPC omsetter is: 1. Met 'n ho modulasie-indeks ontstaan daar 'n lae frekwensie rippel op die neutralepuntspanning. 2. 'n Bestendige toestand wanbalans van die neutrale-puntspanning kan ontstaan as gevolg van 'n verskeidenheid faktore, onder andere komponent nie-idealiteite, oorgangs- en ander wanbalanse. In hierdie tesis word op die bestendige-toestandwanbalans gefokus. Dit word gedoen deur middel van die neutraalbalanseeringsmeganisme van die drie-vlak, drie-fase NPC omsetter, sistematies en gedetaileerd wiskundig te bestudeer. In die bestendige toestand sal orgonaliteit van twee stelle skakel spektras in die frekwensie gebied, GS-bus spanning balans impliseer. Dit word wiskundig geanaliseer deur gebruik te maak van Carrara se alternatiewe fase opposiesie disposisie (APOD), fase oposisie disposisie (POD) en fase disposisie(PD), puls-wydte modulasie strategie, asook Bennet se geometriese modelle vir die dubbel Fourier reeks wat aangepas is vir drywingsomsetters deur Bowes. Ten slotte is die teorie geverifieer deur simulasies.

Over the last several decades, there has been consistent growth in the research and development of multilevel voltage-source inverter-based adjustable speed motor drives (ASDs) as a result of low cost, high reliability power semiconductors. The three-level neutral-point-clamped (NPC) ASD is a popular multilevel inverter used in low and medium voltage applications because of its ability to produce lower levels of total harmonic distortion (THD) and withstand higher voltages while preserving the rated output power compared to two-level ASDs.

As with other voltage-source inverters, three-level NPC ASDs produce common-mode voltage (CMV) that can cause motor shaft voltages, bearing currents, and excess voltage stresses on motor windings, resulting in the deterioration of motor bearings and insulation. Furthermore, the CMV and resultant currents can generate electromagnetic interference that can hinder the operation of sensitive control electronics. In this thesis, three carrier-based, three-level pulse-width-modulation (PWM) strategies were investigated to examine the levels of CMV, common-mode current, and dv/dt produced by the three-level NPC ASD. Additionally, the effects that each PWM strategy has on the THD in the output waveforms, as well as the total switching and conduction losses were analyzed through software simulation programs using a resistive-inductive load over a range of modulation indices. The first of the three methods, in-phase disposition sub-harmonic PWM (PD-SPWM), was verified experimentally using a laboratory-scale, 7.5 kVA three-level NPC ASD prototype.

It was determined that PD-SPWM produced the highest CMV amplitude of one-third the dc bus voltage, but the lowest values of differential-mode dv/dt, THD, and drive losses. The second strategy, phase-opposition (PO)-SPWM, reduced the CMV amplitude to one-sixth the dc bus voltage, at the cost of higher THD and drive losses and a doubling of the differential-mode dv/dt. The final strategy, zero common-mode (ZCM)-SPWM, was modified (MZCM-SPWM) to accommodate IGBT dead-time by delaying the output voltage transitions based on the polarity of the output currents and the direction of the commanded voltage transitions. The MZCM-SPWM method nearly eliminated all CMV pulses while maintaining comparable levels of THD, but produced twice the switching losses compared to PD- and PO- SPWM, and twice the differential-mode dv/dt compared to PD-SPWM.

The main focus of this thesis is on the power electronic converter system challenges associated with the grid integration of variable-renewable-energy (VRE) sources like wave, marine current, tidal, wind, solar etc. Wave energy conversion with grid integration is used as the key reference, considering its high energy potential to support the future clean energy requirements and due the availability of a test facility at Uppsala University. The emphasis is on the DC-link power conditioning and grid coupling of direct driven wave energy converters (DDWECs). The DDWEC reflects the random nature of its input energy to its output voltage wave shape. Thereby, it demands for intelligent power conversion techniques to facilitate the grid connection. One option is to improve and adapt an already existing, simple and reliable multilevel power converter technology, using smart control strategies. The proposed WECs to grid interconnection system consists of uncontrolled three-phase rectifiers, three-level boost converter(TLBC) or three-level buck-boost converter (TLBBC) and a three-level neutral point clamped (TLNPC) inverter. A new method for pulse delay control for the active balancing of DC-link capacitor voltages by using TLBC/TLBBC is presented. Duty-ratio and pulse delay control methods are combined for obtaining better voltage regulation at the DC-link and for achieving higher controllability range. The classic voltage balancing problem of the NPC inverter input, is solved efficiently using the above technique. A synchronous current compensator is used for the NPC inverter based grid coupling. Various results from both simulation and hardware testing show that the required power conditioning and power flow control can be obtained from the proposed multilevel multistage converter system. The entire control strategies are implemented in Xilinx Virtex 5 FPGA, inside National Instruments’ CompactRIO system using LabVIEW. A contour based dead-time harmonic analysis method for TLNPC and the possibilities of having various interconnection strategies of WEC-rectifier units to complement the power converter efforts for stabilizing the DC-link, are also presented. An advanced future AC2AC direct power converter system based on Modular multilevel converter (MMC) structure developed at Siemens AG is presented briefly to demonstrate the future trends in this area.

Les travaux de thèse s’inscrivent dans les problématiques des travaux de recherche de l’équipe thématique : Maitrise des Energies Renouvelables et systèmes de Stockage (MERS) du laboratoire GREAH-EA3220. Ils englobent le dimensionnement des éléments constitutifs du système et la gestion optimale de l’énergie électrique pour un système hybride (Diesel à vitesse variable, Eolien, PV et Batteries) dédié aux sites isolés. Les sources de production d'énergie alimentent des charges par le biais de convertisseurs multi-niveaux d’électronique de puissance. Le groupe électrogène comportant un moteur diesel à vitesse variable est considéré comme la principale source d’énergie utilisée pour contrôler la tension continue du point de couplage. Ce type de groupe électrogène est choisi pour optimiser la consommation du carburant. Il est sollicité pour délivrer une puissance électrique compatible avec le régime du moteur qui supporte mal les variations fréquentes et rapides. Les sources d’énergie renouvelables dont on cherche à augmenter la part d’énergie pour satisfaire la demande sont pilotées de manière à extraire instantanément le maximum de puissances disponible par les ressources (ensoleillement, vent). Celles-ci imposent ainsi leurs dynamiques et leurs intermittences au point de couplage. Le pack des batteries sert à compenser les fluctuations rapides de l’énergie provenant des sources d’énergie renouvelables par rapport à une évolution plus lente prise en charge par le groupe électrogène. La gestion des interactions au sein du système électrique hybride résultant est assurée au moyen de convertisseurs statiques multi-niveaux (AC / DC, DC / DC et DC / AC). Une approche de gestion d’énergie électrique fondée sur la répartition fréquentielle des perturbations induites au point de couplage par les sources renouvelables. Une plateforme expérimentale à échelle réduite (1/22) a été développée pour valider expérimentalement les approches théoriques et les simulations. Les résultats de simulations obtenus dans l’environnement logiciel Matlab/Simulink/SimPowerSystems et ceux issus du dispositif expérimental réalisé et piloté par dSPACE-1104 prouvent l’adéquation des méthodes de contrôle proposées
The thesis works are part of the research work of the thematic team: Mastery of Renewable Energies and Storage Systems (MERS) of the GREAH-EA3220 laboratory. They include the dimensioning of the constituent elements of the system and the optimal management of electrical energy for a hybrid system (Variable speed Diesel, Wind, PV and Batteries) dedicated to isolated sites. Power sources supply loads through multi-level converters of power electronics. The generator set with a variable speed diesel engine is considered to be the main source of energy used to control the DC voltage at the coupling point. This type of generator is chosen to optimize fuel consumption. It is used to deliver an electrical power compatible with the engine speed which does not tolerate frequent and rapid variations. Renewable energy sources whose share of energy is sought to meet demand are managed so as to instantly extract the maximum power available from resources (sunshine, wind). These thus impose their dynamics and their intermittences at the coupling point. The battery pack is used to compensate for rapid fluctuations in energy from renewable energy sources compared to a slower evolution supported by the generator. Interactions within the resulting hybrid electrical system are managed by means of multi-level static converters (AC / DC, DC / DC and DC / AC). An electrical energy management approach based on the frequency distribution of disturbances induced at the coupling point by renewable sources. An experimental platform on a reduced scale (1/22) has been developed to experimentally validate theoretical approaches and simulations. The results of simulations obtained in the Matlab / Simulink / SimPowerSystems software environment and those from the experimental device produced and piloted by dSPACE-1104 prove the adequacy of the proposed control methods

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis.
In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

碩士
國立臺灣科技大學
電機工程系
104
This thesis presents the development of a 50-kilowatt three-level diode-clamp inverter. The implementation of this high power inverter includes a main power stage, modified gate-trig circuits, a DSP-based digital controller. Moreover, the thermal analysis of a forced-air-cooling sink is investigated for full-power operation. Multi-level inverters are superior to traditional two-level structures, such as less losses, lower harmonics and voltage stress, resulting in better performance. In this thesis, the inverter is designed to drive a high-power high-torque serve motor with 50-kW rated power by current control method. Thus, two current control strategies, linear current control and infinite state model predict control, are employed to achieve the control goal, in which 400Hz bandwidth and 100% over load capability are required. The two control strategies are implemented by two DSP controllers, TMS320F28069 and TMS320F28335, respectively. For dealing with the high power requirement, the layout of the main power stage is designed carefully. The inductance-free bus is used to reduce the voltage spike posed on the switches, and the modified gate-trig circuits are used to drive the high-current-rating IGBT devices properly. All these efforts prove the stability of the inverter which can operate at full power for more than two hour, even it is only a prototype. Taking the advantages of the 3-level structure, the inverter provides very high efficiency over the full operation range with the highest 98.6%. Finally, both simulation and experiment results demonstrate that the inverter not only meets the design requirement but also operates with well performance.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

碩士
清雲科技大學
電機工程研究所
93
This paper describes the theory, design, and implementation of a neutral point voltage control for a three level inverter drive system. To reduce the harmonic content of the output voltage and decrease the switch loss, the 3-level inverter is highest importance in the high power application, particularly. When the semiconductor devices are not able to operate at high switch frequency to reduce the harmonic of the output voltage, the 3-level structure is a good choose to solve this problem. Another advantage of the 3-level inverter is that the normal rated voltage of the switch devices can reduce 50%, which can cost down the inverter system. But, there are some difficulties to overcome in the 3-level inverter, the most challenge problem is the neutral-point voltage drift, which not only increase the output voltage harmonic but also make the voltage ratings of each switch device different. In this paper, we use the harmonic injection Sine-PWM to produce the control signals of the inverter. Then, derive the relationship between the neutral-point voltage and the modulation voltage and design a controller to balance the neutral-point voltage. Experiment results show the proposed method can improve the problems of 3-level inverter.

碩士
國立中山大學
電機工程學系研究所
103
Multilevel inverter technology has emerged recently as a very important alternative in the area of medium-voltage (2.3, 3.3, 4.16, and 6.9 kv) energy control. The three level neutral-point-clamped (NPC) inverter is the most extensively applied multilevel inverter topology in this area. Based on the circuit-level decoupling principle, the implementation of modulation scheme can be significantly simplified in every defined operating section through deriving the zero-sequence voltage with assuming balanced neutral-point voltage. This thesis presents a carrier-based discontinuous pulse width modulation (DPWM) strategy with zero-sequence voltage injection and neutral-point voltage balancing control for the three level NPC inverter. The proposed DPWM strategy not only takes advantage of low voltage harmonic distortion, but also reduces the switching loss of the inverter. Finally, the viability and performance of the proposed DPWM strategy are verified in the laboratory prototype.

Das Ziel der Arbeit war die Untersuchung eines neuartigen Phasenbausteins mit der Topologie des Dreipunkt – Neutral Point Clamped – Stromrichters mit Spannungszwischenkreis (3L-NPC-VSC) für Windkraftanwendungen. Wichtige Anforderungen an den Phasenbaustein und daraus resultierende Herausforderungen, sowie Lösungen für ausgewählte Teilprobleme werden präsentiert. Um die Vorteile des 3L-NPC-VSC für Hersteller von Windkraftanlagen zugänglich zu machen, ist es sinnvoll, einen neuartigen Phasenbaustein zu entwickeln. Der Phasenbaustein soll einfach in Systeme zu integrieren sein, in denen gegenwärtig Zweipunktstromrichter (2L-VSC) zum Einsatz kommen. Da sich Modulation, Zwischenkreisbalancierung und Kurzschlussschutz vom 2L-VSC unterscheiden, soll der Phasenbaustein diese Herausforderungen eigenständig bewältigen. Die Arbeit beschreibt die Konzeption eines solchen Phasenbausteins und behandelt insbesondere die Modulation, die Zwischenkreisbalancierung und den Kurzschlussschutz des 3L-NPC-VSC. Ein Vergleich verschiedener Modulationsverfahren wurde durchgeführt und die am besten geeigneten Verfahren für die Implementation in den Phasenbaustein ausgewählt. Eine Anforderung war, dass dieser Signale einer übergeordneten Regelung verarbeiten kann, welche für einen 2L-VSC berechnet wurden. Ein Überblick der Zwischenkreisbalancierungsverfahren zeigte, dass nahezu alle den Nachteil einer zusätzlich benötigten Strommessung haben. Die Untersuchung einer neuen an der Professur Leistungselektronik der TU Dresden entwickelten Methode ohne den Bedarf der Strommessung zeigte, dass diese anwendbar ist. Der Algorithmus wurde simuliert, implementiert und experimentell getestet und zeigte gute Resultate. Die Aufgabe eines komplett unabhängigen Kurzschlussschutzes war die schwierigste. Alle möglichen Fehler innerhalb eines Moduls wurden analysiert und kategorisiert. Einige Fehlertypen können innerhalb einer Phase behandelt werden. Entsprechende Algorithmen wurden entwickelt und getestet. Allerdings gibt es Fehlertypen, die nicht durch die Steuerung einer einzelnen Phase behandelt werden können. Eine schnelle Kommunikation zwischen den drei Phasen des Konverters wäre notwendig. Alternativ könnte eine übergeordnete Steuerung diese Fehler behandeln. Zum Schluss wurde ein Demonstrator des Phasenbausteins aufgebaut und experimentell untersucht. Einige Messergebnisse werden gezeigt, um die Funktion zu verifizieren.:1 Einleitung 1.1 Motivation 1.2 Zielstellung 1.3 Inhalt der Arbeit 2 Stromrichter für Windkraftanlagen 2.1 Stand der Technik 2.1.1 Zweipunktstromrichter mit Spannungszwischenkreis 2.1.2 Dreipunkt-Neutral-Point-Clamped-Stromrichter mit Spannungszwischenkreis 2.1.3 Kommerziell verfügbare Stromrichter für WKA 2.2 Vollumrichterlösung mit erhöhter Ausgangsspannung 2.2.1 Motivation und Anforderungen 2.2.2 Vereinfachter Vergleich von Zwei- und Dreipunktstromrichtern 2.3 Herausforderungen bei der Realisierung des 3L-NPC-VSC 3 Struktur und Funktion eines neuartigen 3L-NPC-Phasenbausteins 3.1 Struktur und Schnittstellen 3.1.1 Stand der Technik für 3L-NPC Phasenbausteine 3.1.2 Neuartiger 3L-NPC-VSC-Phasenbaustein 3.2 Realisierung 3.2.1 Anforderungen 3.2.2 Technische Realisierung 3.3 Experimentelle Verifikation 3.3.1 Versuchsstand 3.3.2 Messergebnisse 4 Modulation und Zwischenkreisbalancierung eines 3L-NPC-VSC 4.1 Modulationsarten im Überblick 4.1.1 Trägerbasierte Modulation für den 3L-NPC-VSC 4.2 Ausgewählte Modulation für den neuartigen Phasenbaustein 4.2.1 Zweipunktraumzeigermodulation in einem Trägerband 2L-SVM 4.2.2 Dreipunktraumzeigermodulation 3L-SVM 4.3 Stand der Technik bei Zwischenkreisbalancierungsverfahren 4.4 Die direkte Totzeitregelung zur Zwischenkreisbalancierung 4.4.1 Theoretische Grundlagen 4.4.2 Simulative Verifikation der direkten Totzeitregelung 4.4.3 Experimentelle Verifikation der DDTC 5 Kurzschlussschutz eines 3L-NPC-VSC-Phasenbausteins 5.1 Versuchsstand I5.2 Kurzschlussfehler einer 3L-NPC-VSC-Phase 5.2.1 Kategorisierung der Kurzschlüsse 5.2.2 Untersuchte Bauteilfehler innerhalb einer 3L-NPC-VSC-Phase 5.3 Kurzschlussbehandlungsmethoden 5.3.1 Stand der Technik 5.3.2 Schutzmaßnahmen für 3L-NPC-VSC 5.4 Analyse von Kurzschlüssen und Ableitung von Behandlungsmaßnahmen 5.4.1 Fehler eines äußeren IGBTs 5.4.2 Fehler eines inneren IGBTs 5.4.3 Fehler einer Clampdiode 5.5 Maßnahmen zur sicheren Behandlung von Kurzschlüssen in 3L-NPC-VSC 6 Zusammenfassung

In the past two decades the core aircraft technology is going through a drastic change. The traditional technologies that is almost half a century old, is going through a complete revamp. In the new “More Electric Aircraft” technology many mechanical, pneumatic and hydraulic systems are being replaced by electrical and power electronic systems. Airbus-A380, Boeing B-787 are the pioneers in the family of these new breed of aircrafts. As the aircraft technology is moving towards “More Electric”, more and more electric motors and motor controllers are being used in new aircrafts. Number of electric motor drive systems has increased by about ten times in more electric aircrafts compared to traditional aircrafts. Weight of any electric component that goes into aircraft needs to be low to reduce the overall weight of aircraft so as to improve the fuel efficiency of the aircraft. Hence there is an increased need to reduce weight of motors and motor controllers in commercial aircraft. High speed ironless axial flux permanent magnet brushless dc motors are becoming popular in the new more-electric aircrafts because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. However, these motors come with very low inductance, which poses a big challenge to the motor controllers in controlling the ripple current in motor windings. Multilevel inverters can solve this problem. Three-level inverters are proposed in this thesis for driving axial flux BLDC motors in aircraft. Majority of the motors in new more electric aircrafts are in the power range of 2kW to 20kW, while a few motor applications being in the range of 100kW to 150kW. Motor controllers in these applications run from 270Vdc or 540Vdc bus which is the standard in new more electric aircraft architecture. Multilevel Inverter is popular in the industry for high power and high voltage applications, where high-voltage power switching devices like IGBT, GTO are popularly used. However multilevel inverters have not been tried in the low power range which is appropriate for aircraft applications. A detail analysis of practical feasibility of constructing three-level inverter in lower power and voltage level is presented in this thesis. Analysis is presented that verify the advantages of driving low voltage and low power (300Vdc to 600Vdc and less than 100kW) motors with multilevel inverters. Practical considerations for design of MOSFET based three-level inverter are investigated and topological modifications are suggested. The effect of clamping diodes in the diode clamped multilevel inverters play an important role in determining its efficiency. SiC diodes are proposed to be used as clamping diodes. Further, it is realised that power loss introduced by reverse recovery of MOSFET body diode prohibits use of MOSFET in hard switched inverter legs. Hence, a technique of avoiding the reverse recovery losses of MOSFET body diode in three-level NPC inverter is conceived. The use of proposed multilevel inverter topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps reducing size of the inverter. In this research work elaborate trade-off analysis is done to quantify the suitability of multilevel inverters in the low power applications. For successful operation of three-level NPC inverter in aircraft electrical system, it is important for the DC bus structure in aircraft electric primary distribution system to be compatible to drive NPC inverters. Hence a detail study of AC to DC power conversion system as applied to commercial aircraft electrical system is done. Multi-pulse rectifiers using autotransformers are used in aircrafts. Investigation is done to improve these rectifiers for future aircrafts, such that they can support new technologies of future generation motor controllers. A new 24-pulse isolated transformer rectifier topology is proposed. From two 15º displaced 6-phase systems feeding two 12-pulse rectifiers that are series connected, a 24-pulse rectifier topology is obtained. Though, windings of each 12-pulse rectifiers are isolated from primary, the 6-phase generation is done without any isolation of the transformer windings. The new 24-pulse transformer topology has lower VA rating compared to standard 12-pulse rectifiers. Though the new 24-pulse transformer-rectifier solution is robust and simple, it adds to the weight of the overall system, as compared to the present architecture as the proposed topology uses isolated transformer. Non-isolated autotransformer cannot provide split voltage at the dc-link that creates a stable mid-point voltage as required by the three-level NPC inverter. Hence, a new front-end AC-DC power conversion system with switched capacitor is conceived that can support motor controllers driven by three-level inverters. Laboratory experimental results are presented to validate the new proposed topology. In this proposed topology, the inverter dc-link voltage is double the input dc-link voltage. An intense research work is performed to understand the operation of Trapezoidal Back EMF BLDC motor driven by three-Level NPC inverter. Operation of BLDC motor from three-Level inverter is primarily advantageous for low inductance motors, like ironless axial flux motors. For low inductance BLDC motor, very high switching frequency is required to limit the magnitude of ripple current in motor winding. Three-level inverters help limiting the magnitude of motor ripple current without increasing the switching frequency to very high value. Further, it is analysed that dc link mid-point current in three-level NPC inverter for driving trapezoidal BLDC motor has a zero average current with fundamental frequency same as switching frequency. Because of this, trapezoidal BLDC motors can easily be operated from three-level NPC inverter without any special attention given to mid-point voltage unbalance. One non-ideal condition arrives in practical implementation of the inverter that leads to non-zero average mid point current. Unequal gate drive dead time delays from one leg to other leg of inverter introduce dc-link mid-point voltage unbalance. For the motoring mode operation of trapezoidal BLDC motor drive, simple gate drive logic is researched that eliminates need of the gate drive dead-time, and hence solves the mid-point voltage unbalance issue. Simple closed loop control scheme for mid-point voltage balancing also is also proposed. This control scheme may be used in applications where very precise control of speed and torque ripple is warranted. All the investigations reported in this thesis are simulated extensively on MATHCAD and MATLAB platform using SIMULINK toolbox. A laboratory experimental set-up of three-Level inverter driving axial flux BLDC motor is built. The three-level inverter, operating from 300Vdc bus is built using 500V MOSFETs and 600V SiC diodes. All the control schemes are implemented digitally on digital signal processor TMS320F2812 DSP platform and GAL22V10B platforms. Experimental results are collected to validate the theoretical propositions made in the present research work. At the end, in chapter 5, some future works are proposed. A new external voltage balance circuit is proposed where the inverter dc-link voltage is same as the input dc-link voltage. This topology is based on the resonant converter principle and uses a lighter resonant inductor than prior arts available in literature. Detail simulation and experimentation of this topology may be carried out to validate the industrial benefits of this circuit. It is also thought that current source inverters may work as an alternative to voltage source inverters for driving BLDC motors. Current source inverters eliminate use of bulky DC-link capacitors. Long term reliability of current source inverters is higher than voltage source inverters due to the absence of possibility of shoot-through. Further, in voltage source inverters, the voltage at the motor terminal is limited by the source voltage (dc-link voltage). This issue is eliminated in current source inverters. An interface circuit is conceived to reduce the size of dc-link inductors in current source inverters, pending detail analysis and experimental verification. The interface circuit bases its fundamentals on the principles of operation of multilevel inverters for BLDC motors that is presented in this thesis.

In the past two decades the core aircraft technology is going through a drastic change. The traditional technologies that is almost half a century old, is going through a complete revamp. In the new “More Electric Aircraft” technology many mechanical, pneumatic and hydraulic systems are being replaced by electrical and power electronic systems. Airbus-A380, Boeing B-787 are the pioneers in the family of these new breed of aircrafts. As the aircraft technology is moving towards “More Electric”, more and more electric motors and motor controllers are being used in new aircrafts. Number of electric motor drive systems has increased by about ten times in more electric aircrafts compared to traditional aircrafts. Weight of any electric component that goes into aircraft needs to be low to reduce the overall weight of aircraft so as to improve the fuel efficiency of the aircraft. Hence there is an increased need to reduce weight of motors and motor controllers in commercial aircraft. High speed ironless axial flux permanent magnet brushless dc motors are becoming popular in the new more-electric aircrafts because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. However, these motors come with very low inductance, which poses a big challenge to the motor controllers in controlling the ripple current in motor windings. Multilevel inverters can solve this problem. Three-level inverters are proposed in this thesis for driving axial flux BLDC motors in aircraft. Majority of the motors in new more electric aircrafts are in the power range of 2kW to 20kW, while a few motor applications being in the range of 100kW to 150kW. Motor controllers in these applications run from 270Vdc or 540Vdc bus which is the standard in new more electric aircraft architecture. Multilevel Inverter is popular in the industry for high power and high voltage applications, where high-voltage power switching devices like IGBT, GTO are popularly used. However multilevel inverters have not been tried in the low power range which is appropriate for aircraft applications. A detail analysis of practical feasibility of constructing three-level inverter in lower power and voltage level is presented in this thesis. Analysis is presented that verify the advantages of driving low voltage and low power (300Vdc to 600Vdc and less than 100kW) motors with multilevel inverters. Practical considerations for design of MOSFET based three-level inverter are investigated and topological modifications are suggested. The effect of clamping diodes in the diode clamped multilevel inverters play an important role in determining its efficiency. SiC diodes are proposed to be used as clamping diodes. Further, it is realised that power loss introduced by reverse recovery of MOSFET body diode prohibits use of MOSFET in hard switched inverter legs. Hence, a technique of avoiding the reverse recovery losses of MOSFET body diode in three-level NPC inverter is conceived. The use of proposed multilevel inverter topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps reducing size of the inverter. In this research work elaborate trade-off analysis is done to quantify the suitability of multilevel inverters in the low power applications. For successful operation of three-level NPC inverter in aircraft electrical system, it is important for the DC bus structure in aircraft electric primary distribution system to be compatible to drive NPC inverters. Hence a detail study of AC to DC power conversion system as applied to commercial aircraft electrical system is done. Multi-pulse rectifiers using autotransformers are used in aircrafts. Investigation is done to improve these rectifiers for future aircrafts, such that they can support new technologies of future generation motor controllers. A new 24-pulse isolated transformer rectifier topology is proposed. From two 15º displaced 6-phase systems feeding two 12-pulse rectifiers that are series connected, a 24-pulse rectifier topology is obtained. Though, windings of each 12-pulse rectifiers are isolated from primary, the 6-phase generation is done without any isolation of the transformer windings. The new 24-pulse transformer topology has lower VA rating compared to standard 12-pulse rectifiers. Though the new 24-pulse transformer-rectifier solution is robust and simple, it adds to the weight of the overall system, as compared to the present architecture as the proposed topology uses isolated transformer. Non-isolated autotransformer cannot provide split voltage at the dc-link that creates a stable mid-point voltage as required by the three-level NPC inverter. Hence, a new front-end AC-DC power conversion system with switched capacitor is conceived that can support motor controllers driven by three-level inverters. Laboratory experimental results are presented to validate the new proposed topology. In this proposed topology, the inverter dc-link voltage is double the input dc-link voltage. An intense research work is performed to understand the operation of Trapezoidal Back EMF BLDC motor driven by three-Level NPC inverter. Operation of BLDC motor from three-Level inverter is primarily advantageous for low inductance motors, like ironless axial flux motors. For low inductance BLDC motor, very high switching frequency is required to limit the magnitude of ripple current in motor winding. Three-level inverters help limiting the magnitude of motor ripple current without increasing the switching frequency to very high value. Further, it is analysed that dc link mid-point current in three-level NPC inverter for driving trapezoidal BLDC motor has a zero average current with fundamental frequency same as switching frequency. Because of this, trapezoidal BLDC motors can easily be operated from three-level NPC inverter without any special attention given to mid-point voltage unbalance. One non-ideal condition arrives in practical implementation of the inverter that leads to non-zero average mid point current. Unequal gate drive dead time delays from one leg to other leg of inverter introduce dc-link mid-point voltage unbalance. For the motoring mode operation of trapezoidal BLDC motor drive, simple gate drive logic is researched that eliminates need of the gate drive dead-time, and hence solves the mid-point voltage unbalance issue. Simple closed loop control scheme for mid-point voltage balancing also is also proposed. This control scheme may be used in applications where very precise control of speed and torque ripple is warranted. All the investigations reported in this thesis are simulated extensively on MATHCAD and MATLAB platform using SIMULINK toolbox. A laboratory experimental set-up of three-Level inverter driving axial flux BLDC motor is built. The three-level inverter, operating from 300Vdc bus is built using 500V MOSFETs and 600V SiC diodes. All the control schemes are implemented digitally on digital signal processor TMS320F2812 DSP platform and GAL22V10B platforms. Experimental results are collected to validate the theoretical propositions made in the present research work. At the end, in chapter 5, some future works are proposed. A new external voltage balance circuit is proposed where the inverter dc-link voltage is same as the input dc-link voltage. This topology is based on the resonant converter principle and uses a lighter resonant inductor than prior arts available in literature. Detail simulation and experimentation of this topology may be carried out to validate the industrial benefits of this circuit. It is also thought that current source inverters may work as an alternative to voltage source inverters for driving BLDC motors. Current source inverters eliminate use of bulky DC-link capacitors. Long term reliability of current source inverters is higher than voltage source inverters due to the absence of possibility of shoot-through. Further, in voltage source inverters, the voltage at the motor terminal is limited by the source voltage (dc-link voltage). This issue is eliminated in current source inverters. An interface circuit is conceived to reduce the size of dc-link inductors in current source inverters, pending detail analysis and experimental verification. The interface circuit bases its fundamentals on the principles of operation of multilevel inverters for BLDC motors that is presented in this thesis.

碩士
國立高雄應用科技大學
電機工程系博碩士班
101
This thesis investigates the space vector modulation (SVM) applied to neutral-point-clamped inverters (NPC). The principle of space vector modulation is analyzed, and the MATLAB/Simulink/SimPowerSystems is used for constructing the circuit model and control module, simulation results of SVM with different switching sequence are compared, and the effect on neutral point voltage balancing, voltage utilization and harmonic distortion are discussed. Then, the ALTERA Quartus II software is used for constructing the control module of space vector modulation, and the program is downloaded to FPGA development board for realization. Actual measurement waveforms are compared with MATLAB simulation results, the consistency of each other confirms that FPGA implementation of space vector modulation function is correct.

碩士
國立勤益科技大學
電機工程系
105
This thesis presents an extension theory-based assessing method to apply fault diagnosis for inverters in motor driving systems. First, a three-level neutral point clamped (NPC) inverter was created using the PSIM software to simulate faults occurring on any power transistor in the NPC-type inverter. Also, Fast Fourier Transform was used to transform line current signals in time domain into spectrum in frequency domain for analysis of the corresponding spectrum of feature of the inverter in case of faults of different power transistors. Then, the relationship between the fault types and specific spectra was established as characteristics for extension assessment method, whereby to further create a smart fault diagnosis system for inverters. Fault-tolerant control (FTC) was further used, in the event of faulty inverter with its rated output decreased, to maintain output in balanced three phases by changing the framework of transistor connection, to reinforce the reliability of the inverter. Finally, by the results of simulation and experiment, the feasibility of the proposed smart fault diagnosis system was testified. The proposed fault diagnosing method features the advantages of minimum data, requiring no learning process, due to which fault diagnosing time is reduced, and being easy to realize. The proposed fault tolerant control strategy allows online and smooth switching in the wiring structure of the inverter.

碩士
國立高雄應用科技大學
電機工程系博碩士班
106
This thesis investigates the circuit topology of a three-level active neutral-point clamped(3L-ANPC) inverter at first. Five schemes of modulation technology for the 3L-ANPC: the traditional two kinds of modulation(PWM-1, PWM-2), DF-PWM, ALD-PWM and ADF-PWM, are explored, the loss of distribution when use these five technologies in the 3L-ANPC are analyzed. Then this thesis investigates four different topologies of five-level circuit: 8S-5L-ANPC, 5L-T-type-ANPC, 7S-5L-ANPC and 6S-5L-ANPC. Two modulation methods applicable to these four circuit topologies are detailed analyzed, and how to achieve capacitor voltage balance control is explained. The simulation results from MATLAB/Simulink are used to validate the theoretical analysis. Finally, the ALTERA Quartus II is used for design the switch excitation signals, then the code is downloaded to a FPGA board (DE2-115). A three-level ANPC and a five-level ANPC with MOSFET and IGBT as the switches are implemented and the experimental results verify the feasibility.

With the increasing popularity of multi-level inverters, the room for improvement of the performance of voltage source inverters has continuously been tested for various applications. The present project highlights the comparison of the conventional two-level inverter and the three-level Neutral-Point Clamped inverters for the application in automotive industry. The two inverters are compared for different conditions for losses, efficiency and the permissible temperature limit of operation for the non-ideal inverters that have been chosen for the application. The allowable limits of the switching frequencies for both the inverters have been discussed. The project highlights the DC-link balancing control which is the most commonly faced problem in case of a three-level Neutral-Point Clamped Inverter, with no additional circuit. Modifications of the modulation techniques for the realization of the DC-link balancing control have been proposed. Comparison of the total harmonic distortion of the line-to-line voltages at the outputs of the two and three-level inverters has been presented for both modulation techniques. The project also deals with the control of the Permanent Magnet Synchronous Motor drive using Field-Oriented Control Technique. From the detailed comparison, three-level Neutral-Point Clamped inverter has stood out as a better candidate when compared to the conventional, two-level inverter.

碩士
國立臺北科技大學
電力電子產業研發碩士專班
95
The purpose of this thesis is to design and realize a diode-clamped three-level inverter with neutral-point voltage balance. The harmonic contents of output voltage of three-level inverters are less than those for two-level inverters. However, diode-clamped three-level inverter has the problem of neutral point voltage balance. This thesis uses two control methods to balance the voltage of DC-link capacitors and reduce the total harmonic distortion of output waveforms. The simulation results are derived from Matlab®/Simulink® software. The experimental results are derived from an induction motor drive controlled by digital signal processor. It will be shown that the simulation results and experimental results confirm the performance of the control methods for neutral point voltage balance in diode-clamped three-level inverters.

碩士
國立高雄應用科技大學
電機工程系博碩士班
106
This thesis investigates the fault behavior and analysis for open-switch damages in active neutral point clamped inverters.This thesis analyzes the influence of the terminal voltage on the four working areas of the inverter operation first, and summarizes the fault analysis results.Then the Active neutral point clamped inverter is modeled in MATLAB/Simulink to analyze the performance of this inverter.This thesis analyses the working situation of the switching devices under the open-circuit fault, studies the specific fault characteristics and typical waveforms in detail.Finally, the simulation results illustrate that open switch faults diagnosis system can get correct and fast effect for identification.

碩士
國立高雄應用科技大學
電機工程系博碩士班
102
This thesis investigates the space vector modulation (SVM) applied to neutral-point-clamped inverters (NPC). Principles of three-level space vector modulation and equivalent two-level space vector modulation are discussed, then the performance of two modulation methods are analyzed in controlling the neutral point clamped inverter. The fault phenomenon is studied when the inverter unexpectedly failed during normal operation, and a fault diagnosis system is proposed to determine the position of fault switch. The Matlab/Simulink software is used for simulation. In the end, FPGA is used as a core technology in developing the SVM signal generator and fault diagnosis system. The design and simulation are implemented in Quartus II environment, and the program is downloaded to a development board for realization. From the actual measurement results illustrate that FPGA implementation of space vector modulation function is correct and fault diagnosis system can get correct effect for fault identification.

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177