Relevant bibliographies by topics / NMOs and PMOS pair

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'NMOs and PMOS pair'

Author: Grafiati
Published: 5 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "NMOs and PMOS pair"

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Yang, Chin-Lung, Chih-Hsiang Peng та Yi-Chyun Chiang. "Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology". International Journal of Microwave Science and Technology 2009 (23 лютого 2009): 1–7. http://dx.doi.org/10.1155/2009/715641.

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This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS cross-coupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental resul
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Wang, Fan, Minghai Fang, Peng Yu, et al. "Effects of Fe Contamination on the Reliability of Gate Oxide Integrity in Advanced CMOS Technology." Electronics 13, no. 12 (2024): 2391. http://dx.doi.org/10.3390/electronics13122391.

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Fe contamination has always been one of the most critical issues in the integrated circuit (IC) industry due to its catastrophic effect on device reliability and electrical characteristics. With complementary metal oxide semiconductor (CMOS) technology scaling down, this issue has been attracting more attention. In this paper, the impact of Fe impurity on the reliability of gate oxide integrity (GOI) in advanced CMOS technology is investigated. Intentional contamination of polysilicon gates was conducted in both boron- and phosphorus-doped devices. Failure analysis of the gate oxide was conduc
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Tripathi, Arunendra Nath, Rajkumar Tiwari, and Monika Tiwari. "A new approach to design Class C amplifier at nano scale with low power consumptions for mobile application." International Journal for Research in Engineering Application & Management (IJREAM) 08, no. 10 (2023): 33–36. https://doi.org/10.35291/2454-9150.2023.0007.

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At present, saving energy is one of the important goals, keeping this in mind we present a new approach to design class c amplifier which works at very low power consumption in the range of micro watt and low noise in range nano watt and works in frequency range tera hertz 1.563THz to 6.930 THz with voltage gain 20dB. Present pair is combination of NMOS and PMOS in compound pair form and it is simulated on cadence virtuoso software at 180nm scale. It can be used in radio astronomy, satellite, communications.
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Kwon, Kipaek, and Soo-Ik Chae. "Simple reversible energy recovery logic using NMOS switch networks with cross-coupled PMOS pair." Electronics Letters 34, no. 23 (1998): 2215. http://dx.doi.org/10.1049/el:19981586.

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Su, C., B. J. Blalock, S. K. Islam, L. Zuo та L. M. Tolbert. "A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (2010): 000083–88. http://dx.doi.org/10.4071/hitec-csu-ta26.

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The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI proce
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Hamedi-Hagh, Sotoudeh, and Ahmet Bindal. "Design and Characterization of the Next Generation Nanowire Amplifiers." VLSI Design 2008 (February 3, 2008): 1–5. http://dx.doi.org/10.1155/2008/190315.

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Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 d
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Kotha, Sreeteja Reddy, Karuppanan P, Abhay Kumar Gautam, and Manmath Suryavanshi. "A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications." Journal of Integrated Circuits and Systems 16, no. 3 (2021): 1–9. http://dx.doi.org/10.29292/jics.v16i3.498.

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This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transc
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Yin, Yue, Xinbing Zhang, Ziting Feng, et al. "An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing." Micromachines 15, no. 9 (2024): 1108. http://dx.doi.org/10.3390/mi15091108.

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In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the “current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs” structure, the bulk-driven pseudo-differe
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Li, Longhua, Soonwoo Kwon, Dohoon Kim, et al. "Design of Multi-Time Programmable Intellectual Property with Built-In Error Correction Code Function Based on Bipolar–CMOS–DMOS Process." Electronics 14, no. 1 (2024): 68. https://doi.org/10.3390/electronics14010068.

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The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm2), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to tes
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Babu CH, Ashok, J. V.R. Ravindra, and K. Lalkishore. "Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications." International Journal of Engineering & Technology 7, no. 2.23 (2018): 498. http://dx.doi.org/10.14419/ijet.v7i2.23.15343.

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This paper tailors 8 bit ALU for high speed and low power applications. In this design a novel PMOS and NMOS are used in place of conventional PMOS and NMOS. The main disadvantage of conventional PMOS and NMOS is low speed. With the technique of forward body biasing a novel PMOS and NMOS are derived and speed is improved. For each sub module of ALU power delay product percentage is calculated. Percentage improvement in power delay product of Novel ALU is shown in table 27.
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Dissertations / Theses on the topic "NMOs and PMOS pair"

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Kšica, Radim. "Návrh operačního zesilovače s proudovou zpětnou vazbou." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218578.

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This Master`s thesis deals with properties of current feedback operational amplifier. The main goal of this work is creation design process of current feedback operational amplifier by using CMOS technology AMIS 0,7 µm. Next goal of this work is attestation of funciton our design process. Last goal is creation the datasheet of our amplifier.
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Cho, Hanho. "Optically Powered Logic Transistor." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2525.pdf.

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AMETHYSTNA, SURYA KRIS, and SURYA KRIS AMETHYSTNA. "Reliability Study On 5V BCD CMOS Device: New PMOS-NBTI Characterization And HCI Assessment On NMOS Bend Gate Structure." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/31769353292665240991.

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碩士<br>亞洲大學<br>資訊工程學系碩士班<br>100<br>In this thesis, reliability assessment for low voltage CMOS device had been studied. New characterization for negative bias temperature instability (NBTI) was proposed using fast triangular pulse with elevated temperature to analyze Si-H bond behavior generating interface trap. Fast triangular pulse was proposed to minimize the recovery effect while the elevated temperature was used to weaken Si-H bond. This proposed measurement technique, shows that threshold voltage shift will be saturated at 3.46mV (0.48% shift) as the device temperature elevated to 400K. F
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Ajayan, K. R. "Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3516.

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Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimiz
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Ajayan, K. R. "Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology." Thesis, 2014. http://etd.iisc.ernet.in/2005/3516.

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Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimiz
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Book chapters on the topic "NMOs and PMOS pair"

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Kuntman, Hakan, Deniz Özenli, Fırat Kaçar, and Yasin Özçelep. "The Reliability Model for PMOS and NMOS Transistors Based on Statistical Methods." In Analog Circuits and Signal Processing. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-85455-2_2.

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Tewari, Suchismita, Abhijit Biswas, and Abhijit Mallik. "Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers." In Proceedings of the International Conference on Microelectronics, Computing & Communication Systems. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5565-2_13.

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Krishnamohan, Tejas, Christoph Jungemann, and Krishna C. Saraswat. "Very High Performance, Sub-20nm, Strained Si and Six Ge1-x, Hetero-structure, Center Channel (CC) NMOS and PMOS DGFETs." In Simulation of Semiconductor Processes and Devices 2004. Springer Vienna, 2004. http://dx.doi.org/10.1007/978-3-7091-0624-2_43.

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Conference papers on the topic "NMOs and PMOS pair"

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Huening, Jennifer J., Xianghong Tom Tong, Shuai Zhao, et al. "E-beam Probing and E-beam-Assisted Device Alteration (EADA) for Fault Isolation in PowerVia and Advanced Technology Nodes." In ISTFA 2024. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0519.

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Abstract This paper demonstrates that e-beam assisted device alteration (EADA) is a powerful, high-resolution technique for fault isolation debug for advanced technology nodes. A case study using this technique is reviewed and shows successful isolation of a defective single inverter. In addition, fundamental studies of ring oscillator behavior and device perturbations with e-beam exposure found clear correlations for electron beam exposure with NMOS/PMOS device parameters. Electron-hole pair generation in the device with beam exposure is likely the main component for the perturbation, but the
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Tu, Estevan Chia Hung, Jean-Baptiste Begueret, Stephane Thuries, Emmanuel Pistono, Florence Podevin, and Sylvain Bourdel. "Ultra-Low Phase Noise NMOS and PMOS Colpitts Oscillators Using BAW Resonator Comparison." In 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2024. https://doi.org/10.1109/icecs61496.2024.10848875.

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Baghini, Sajjad Shojaei, Seyed-Ali Samareh-TaheriNasab, and Samad Sheikhaei. "A Low Power Wideband 0.6-5.4 GHz CG-CS LNA with pMOS-nMOS Configuration and Resistive Feedback." In 2024 32nd International Conference on Electrical Engineering (ICEE). IEEE, 2024. http://dx.doi.org/10.1109/icee63041.2024.10668050.

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Mortelmans, W., P. Buragohain, C. Rogan, et al. "Record Performance in GAA 2D NMOS and PMOS Using Monolayer MoS2 and WSe2 with Scaled Contact and Gate Length." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631395.

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Rostomyan, Narek, Mustafa Ozen, and Peter Asbeck. "Comparison of pMOS and nMOS 28 GHz high efficiency linear power amplifiers in 45 nm CMOS SOI." In 2018 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR). IEEE, 2018. http://dx.doi.org/10.1109/pawr.2018.8310058.

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Melikyan, Vazgen, Abraham Balabanyan, Artak Hayrapetyan, and Armen Durgaryan. "NMOS/PMOS resistance calibration method using reference frequency." In 2013 Computer Science and Information Technologies (CSIT). IEEE, 2013. http://dx.doi.org/10.1109/csitechnol.2013.6710330.

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Martins, Everson, Matheus A. Alejandro, and Thais V. Fogaca. "Differential mixer with NMOS/PMOS stack at switching stage." In 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2012. http://dx.doi.org/10.1109/sbcci.2012.6344440.

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Janesick, James, Tom Elliott, James Andrews, and John Tower. "Performance and design differences between PMOS and NMOS CMOS imagers." In SPIE Commercial + Scientific Sensing and Imaging, edited by Nibir K. Dhar and Achyut K. Dutta. SPIE, 2017. http://dx.doi.org/10.1117/12.2264135.

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Bourdillon, Antony J., Yew G. Koh, Shu L. Chiang, Chong W. Lim, Jong Ren Kong, and Cao Guobing. "Transmission electron microscopy of defects in NMOS and PMOS structures." In ISMA '97 International Symposium on Microelectronics and Assembly, edited by Soon Fatt Yoon, Raymond Yu, and Chris A. Mack. SPIE, 1997. http://dx.doi.org/10.1117/12.280546.

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Eadi, Sunil Babu, and Hi-Deok Lee. "Advanced contact technology for InGaAs NMOS and Ge PMOS devices." In 2021 20th International Workshop on Junction Technology (IWJT). IEEE, 2021. http://dx.doi.org/10.23919/iwjt52818.2021.9609440.

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Journal articles
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