Log in

Relevant bibliographies by topics / NMOs and PMOS pair / Journal articles

To see the other types of publications on this topic, follow the link: NMOs and PMOS pair.

Journal articles on the topic 'NMOs and PMOS pair'

Author: Grafiati

Published: 5 June 2025

Last updated: 2 August 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'NMOs and PMOS pair.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Yang, Chin-Lung, Chih-Hsiang Peng та Yi-Chyun Chiang. "Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology". International Journal of Microwave Science and Technology 2009 (23 лютого 2009): 1–7. http://dx.doi.org/10.1155/2009/715641.

Full text

Abstract:

This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS cross-coupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental resul

APA, Harvard, Vancouver, ISO, and other styles

2

Wang, Fan, Minghai Fang, Peng Yu, et al. "Effects of Fe Contamination on the Reliability of Gate Oxide Integrity in Advanced CMOS Technology." Electronics 13, no. 12 (2024): 2391. http://dx.doi.org/10.3390/electronics13122391.

Full text

Abstract:

Fe contamination has always been one of the most critical issues in the integrated circuit (IC) industry due to its catastrophic effect on device reliability and electrical characteristics. With complementary metal oxide semiconductor (CMOS) technology scaling down, this issue has been attracting more attention. In this paper, the impact of Fe impurity on the reliability of gate oxide integrity (GOI) in advanced CMOS technology is investigated. Intentional contamination of polysilicon gates was conducted in both boron- and phosphorus-doped devices. Failure analysis of the gate oxide was conduc

APA, Harvard, Vancouver, ISO, and other styles

3

Tripathi, Arunendra Nath, Rajkumar Tiwari, and Monika Tiwari. "A new approach to design Class C amplifier at nano scale with low power consumptions for mobile application." International Journal for Research in Engineering Application & Management (IJREAM) 08, no. 10 (2023): 33–36. https://doi.org/10.35291/2454-9150.2023.0007.

Full text

Abstract:

At present, saving energy is one of the important goals, keeping this in mind we present a new approach to design class c amplifier which works at very low power consumption in the range of micro watt and low noise in range nano watt and works in frequency range tera hertz 1.563THz to 6.930 THz with voltage gain 20dB. Present pair is combination of NMOS and PMOS in compound pair form and it is simulated on cadence virtuoso software at 180nm scale. It can be used in radio astronomy, satellite, communications.

APA, Harvard, Vancouver, ISO, and other styles

4

Kwon, Kipaek, and Soo-Ik Chae. "Simple reversible energy recovery logic using NMOS switch networks with cross-coupled PMOS pair." Electronics Letters 34, no. 23 (1998): 2215. http://dx.doi.org/10.1049/el:19981586.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Su, C., B. J. Blalock, S. K. Islam, L. Zuo та L. M. Tolbert. "A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (2010): 000083–88. http://dx.doi.org/10.4071/hitec-csu-ta26.

Full text

Abstract:

The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI proce

APA, Harvard, Vancouver, ISO, and other styles

6

Hamedi-Hagh, Sotoudeh, and Ahmet Bindal. "Design and Characterization of the Next Generation Nanowire Amplifiers." VLSI Design 2008 (February 3, 2008): 1–5. http://dx.doi.org/10.1155/2008/190315.

Full text

Abstract:

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 d

APA, Harvard, Vancouver, ISO, and other styles

7

Kotha, Sreeteja Reddy, Karuppanan P, Abhay Kumar Gautam, and Manmath Suryavanshi. "A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications." Journal of Integrated Circuits and Systems 16, no. 3 (2021): 1–9. http://dx.doi.org/10.29292/jics.v16i3.498.

Full text

Abstract:

This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transc

APA, Harvard, Vancouver, ISO, and other styles

8

Yin, Yue, Xinbing Zhang, Ziting Feng, et al. "An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing." Micromachines 15, no. 9 (2024): 1108. http://dx.doi.org/10.3390/mi15091108.

Full text

Abstract:

In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the “current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs” structure, the bulk-driven pseudo-differe

APA, Harvard, Vancouver, ISO, and other styles

9

Li, Longhua, Soonwoo Kwon, Dohoon Kim, et al. "Design of Multi-Time Programmable Intellectual Property with Built-In Error Correction Code Function Based on Bipolar–CMOS–DMOS Process." Electronics 14, no. 1 (2024): 68. https://doi.org/10.3390/electronics14010068.

Full text

Abstract:

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm2), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to tes

APA, Harvard, Vancouver, ISO, and other styles

10

Babu CH, Ashok, J. V.R. Ravindra, and K. Lalkishore. "Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications." International Journal of Engineering & Technology 7, no. 2.23 (2018): 498. http://dx.doi.org/10.14419/ijet.v7i2.23.15343.

Full text

Abstract:

This paper tailors 8 bit ALU for high speed and low power applications. In this design a novel PMOS and NMOS are used in place of conventional PMOS and NMOS. The main disadvantage of conventional PMOS and NMOS is low speed. With the technique of forward body biasing a novel PMOS and NMOS are derived and speed is improved. For each sub module of ALU power delay product percentage is calculated. Percentage improvement in power delay product of Novel ALU is shown in table 27.

APA, Harvard, Vancouver, ISO, and other styles

11

Lauwers, Anne, Jorge Kittl, and Karen Maex. "RTP Requirements for CMOS Integration of Dual Work Function Phase Controlled Ni-FUSI (Fully Silicided) Gates with Simultaneous Silicidation of nMOS (NiSi) and pMOS (Ni-Rich Silicide) Gates on HfSiON." Materials Science Forum 573-574 (March 2008): 341–51. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.341.

Full text

Abstract:

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of nMOS (NiSi) and pMOS (Ni-rich) gates on HfSiON is demonstrated. Linewidth independent phase control with smooth threshold voltage (Vt) roll-off characteristics is achieved for NiSi, Ni2Si and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). A 2-step Ni FUSI process enables simultaneous silicidation of nMOS and pMOS FUSI gates, achieving different Ni/Si ratios on nMOS and pMOS by reduction of th

APA, Harvard, Vancouver, ISO, and other styles

12

Guruprasad. "Comparative analysis of PMOS and NMOS based linear regulators with similar power profiles." Journal of Electrical Systems 20, no. 3 (2024): 1500–1510. http://dx.doi.org/10.52783/jes.3556.

Full text

Abstract:

In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass

APA, Harvard, Vancouver, ISO, and other styles

13

Guruprasad. "Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles." Journal of Electrical Systems 20, no. 5s (2024): 2850–60. http://dx.doi.org/10.52783/jes.3195.

Full text

Abstract:

In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass

APA, Harvard, Vancouver, ISO, and other styles

14

Reddy, M. Devendra, and P. Dass. "Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic." Alinteri Journal of Agriculture Sciences 36, no. 1 (2021): 635–41. http://dx.doi.org/10.47059/alinteri/v36i1/ajas21090.

Full text

Abstract:

Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the

APA, Harvard, Vancouver, ISO, and other styles

15

SHRIVAS, JAYRAM, SHYAM AKASHE, and NITESH TIWARI. "A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER." International Journal of Nanoscience 12, no. 02 (2013): 1350011. http://dx.doi.org/10.1142/s0219581x13500117.

Full text

Abstract:

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turne

APA, Harvard, Vancouver, ISO, and other styles

16

Li, Yucheng, Shiqi Zhang, and Jianjun Song. "A Germanium Based Quantum Well Complementary Metal-Oxide-Semiconductor Transistor." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1245–55. http://dx.doi.org/10.1166/jno.2022.3308.

Full text

Abstract:

Germanium is recognized as an important prospective material due to its great carrier mobility. The current design and research of GeSn channel field effect transistors are far from mature. Especially the complementary Ge-based CMOS device is rarely reported. It significantly limits the application and development of Ge-based MOS technology. Based on this, a Si0.2Ge0.66Sn0.14-Ge0.82Sn0.18-Ge double heterojunction quantum well NMOS and PMOS are proposed. Benefiting from the high carrier mobility of Ge and the increased mobility brought by the quantum well, the proposed NMOS and PMOS device achi

APA, Harvard, Vancouver, ISO, and other styles

17

Mohd Said, Muzalifah, Zul Atfyi Fauzan, and Nur Fatihah Azmi. "NMOS Low Boron Activation in Pre-Amorphise Silicon." Advanced Materials Research 875-877 (February 2014): 734–38. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.734.

Full text

Abstract:

The high demand of smaller and compact size of MOSFETs has leads to desirable for ultra shallow junction formation with low sheet resistance and good electrical performances. These two characteristics are required to suppress short channel effects and to increase the efficiency of device. In this paper, Pre-amorphise implantation (PAI) PMOS with different doses of Boron and the basic PMOS structure are done by using ATHENA and the performance of devices is compared by using ATLAS software package from Silvaco TCAD. Comparison done in electrical characteristic, I-V curve Ion and Ioff has showed

APA, Harvard, Vancouver, ISO, and other styles

18

Moisiadis, Y., I. Bouras, and A. Arapoyanni. "Charge Pump Circuits for Low-voltage Applications." VLSI Design 15, no. 1 (2002): 477–83. http://dx.doi.org/10.1080/1065514021000012084.

Full text

Abstract:

In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while

APA, Harvard, Vancouver, ISO, and other styles

19

Idris, Muhammad I., Ming Hung Weng, H. K. Chan, et al. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

Full text

Abstract:

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB

APA, Harvard, Vancouver, ISO, and other styles

20

Mustapha, Muhazam, Jeffery Lee, Anis Shahida Niza Mokhtar, Kamarul ‘Asyikin Mustafa, and Bakhtiar Affendi Rosdi. "A Method of Realizing XOR/XNOR Gate using Symmetric Boolean Function Lattice Structure." Jurnal Kejuruteraan si4, no. 2 (2021): 85–92. http://dx.doi.org/10.17576/jkukm-2021-si4(2)-13.

Full text

Abstract:

The current CMOS’s industry standard XOR and XNOR gate consist of 12 and 10 transistors, respectively. This transistor count could be lowered down to produce low power circuits as XOR/XNOR are extensively used in many functional modules. As a solution, a method for realizing low transistor count XOR/XNOR gates using a special property of symmetric Boolean function is proposed. This property suggests that the circuits for such functions can be realized with fewer transistors using a special lattice structure circuit. Modifications are made to the original lattice structure to match with the cur

APA, Harvard, Vancouver, ISO, and other styles

21

Li, Y., F. Liu, B. Lu, et al. "Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage." Journal of Instrumentation 19, no. 06 (2024): P06045. http://dx.doi.org/10.1088/1748-0221/19/06/p06045.

Full text

Abstract:

Abstract This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current (gm /ID ) ratio and low-frequency (1/f) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage det

APA, Harvard, Vancouver, ISO, and other styles

22

T. Venkata, Lakshmi, and M. Kamaraju. "A novel single ended 3T SRAM cell using FinFET technology for low power applications." i-manager’s Journal on Electronics Engineering 14, no. 4 (2024): 25. http://dx.doi.org/10.26634/jele.14.4.20911.

Full text

Abstract:

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access trans

APA, Harvard, Vancouver, ISO, and other styles

23

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

Full text

Abstract:

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g

APA, Harvard, Vancouver, ISO, and other styles

24

Banu, Sufia, and Shweta Gupta. "Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso." International Journal of Electrical and Electronics Research 10, no. 2 (2022): 341–46. http://dx.doi.org/10.37391/ijeer.100246.

Full text

Abstract:

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are

APA, Harvard, Vancouver, ISO, and other styles

25

R.Nirmal, P.Nithila, K.Jayasudha, P.Velumani, M.Barkavi, and Dr D. F. Jingle Jabha. "DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO." Dogo Rangsang Research Journal 13, no. 03 (2023): 97–105. http://dx.doi.org/10.36893/drsr.2023.v13i03n03.097-105.

Full text

Abstract:

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three so

APA, Harvard, Vancouver, ISO, and other styles

26

Veirano, Francisco, Lirida Naviner, and Fernando Silveira. "Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 12 (2017): 3081–91. http://dx.doi.org/10.1109/tcsi.2017.2747480.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Liao, Wen-Shiang, Yie-Gie Liaw, Mao-Chyuan Tang, Sandipan Chakraborty, and Chee Wee Liu. "Investigation of Reliability Characteristics in NMOS and PMOS FinFETs." IEEE Electron Device Letters 29, no. 7 (2008): 788–90. http://dx.doi.org/10.1109/led.2008.2000723.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Zhang, Hongwei, Yang Guo, Shida Wang, et al. "Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset." Micromachines 15, no. 2 (2024): 201. http://dx.doi.org/10.3390/mi15020201.

Full text

Abstract:

Planar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses this gap by establishing a FinFET SRAM simulation structure and employing simulation software to delve into the charge collection process of FinFET devices during single-event upset. The results reveal substantial differences in charge collection between NMOS and PMOS, and that direct incidence of PMOS leads to the phenomenon of multiple-node

APA, Harvard, Vancouver, ISO, and other styles

29

Jain, Prateek, and Amit Joshi. "Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850092. http://dx.doi.org/10.1142/s0218126618500925.

Full text

Abstract:

An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the

APA, Harvard, Vancouver, ISO, and other styles

30

Hassan Aboadla, Ezzidin, and Ali Hassan. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236. http://dx.doi.org/10.11591/ijict.v12i3.pp236-241.

Full text

Abstract:

<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset

APA, Harvard, Vancouver, ISO, and other styles

31

Ezzidin, Hassan Aboadla, and Hassan Ali. "180 nm NMOS voltage-controlled oscillator for phase-locked loop applications." International Journal of Informatics and Communication Technology (IJ-ICT) 12, no. 3 (2023): 236–41. https://doi.org/10.11591/ijict.v12i3.pp236-241.

Full text

Abstract:

The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a tot

APA, Harvard, Vancouver, ISO, and other styles

32

Lee, Minjong, Joohoon Kang, and Young Tack Lee. "Melt Blown Fiber-Assisted Solvent-Free Device Fabrication at Low-Temperature." Micromachines 11, no. 12 (2020): 1091. http://dx.doi.org/10.3390/mi11121091.

Full text

Abstract:

In this paper, we propose a solvent-free device fabrication method using a melt-blown (MB) fiber to minimize potential chemical and thermal damages to transition-metal-dichalcogenides (TMDCs)-based semiconductor channel. The fabrication process is composed of three steps; (1) MB fibers alignment as a shadow mask, (2) metal deposition, and (3) lifting-up MB fibers. The resulting WSe2-based p-type metal-oxide-semiconductor (PMOS) device shows an ON/OFF current ratio of ~2 × 105 (ON current of ~−40 µA) and a remarkable linear hole mobility of ~205 cm2/V·s at a drain voltage of −0.1 V. These resul

APA, Harvard, Vancouver, ISO, and other styles

33

Wang, Yueyu, Jianjun Song, Xianying Dai, and Tianlong Zhao. "Study on uniaxial stress intensity of MOS channels along different crystal planes induced by SiN-film." Materials Express 10, no. 10 (2020): 1753–57. http://dx.doi.org/10.1166/mex.2020.1803.

Full text

Abstract:

The process conditions for depositing SiN film on small-sized MOS along different crystal face channels to introduce stress are the same. However, since the elastic stiffness coefficient of channel Si material is anisotropic, the stress intensity introduced in small-sized MOS channels along different crystal planes is different. It is necessary to consider it while designing and manufacturing small-sized strained MOS. In this paper, the uniaxial strained Si PMOS and NMOS with 40 nm channel along different crystal faces were produced by compressive stress and tensile stress SiN film respectivel

APA, Harvard, Vancouver, ISO, and other styles

34

May, Alexander, Mathias Rommel, Affan Abbasi, and Tobias Erlbacher. "Threshold Voltage Adjustment on 4H-SiC MOSFETs Using P-Doped Polysilicon as a Gate Material." Key Engineering Materials 947 (May 31, 2023): 57–62. http://dx.doi.org/10.4028/p-w6bx49.

Full text

Abstract:

To scale digital circuits, symmetric threshold voltages (Vth) for n-type transistors (NMOS) and p-type transistors (PMOS) are important. One step towards this in silicon carbide (SiC) is selecting a p-doped polysilicon (pPolySi). This implementation has been shown in this work with Vth being evaluated by five different methods. Furthermore, operating temperatures up to 500 °C and their impact on Vth were investigated. It has been successfully demonstrated that elevated temperature shifts Vth of both transistor types towards 0 V, whereas changing the gate electrode from n-doped PolySi (nPolySi)

APA, Harvard, Vancouver, ISO, and other styles

35

Duarte, Pedro Henrique, Ricardo Cardoso Rangel, and Joao Antonio Martino. "pH Monitoring using BESOI MOSFET with different Sensing Regions." Journal of Integrated Circuits and Systems 20, no. 1 (2025): 1–8. https://doi.org/10.29292/jics.v20i1.935.

Full text

Abstract:

This work explores the sensing regions of BESOI MOSFETs working as pMOS for pH detection using TCAD Sentaurus numerical simulation. A novel approach was employed to model the electrolyte, addressing the simulator's prior lack of a model for this material type, based on existing literature. The simulation results show that the BESOI pMOS present an increase in drain current levels for basic pH values and a decrease for acidic pH values, which is the opposite of what occurs in the case of the BESOI nMOS, in the previous work. Additionally, the voltages applied to the programming gate and the ele

APA, Harvard, Vancouver, ISO, and other styles

36

Thaar A.Kareem, Saif Benali, and Hatem Trabelsi. "Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes." International Journal of Interactive Mobile Technologies (iJIM) 17, no. 06 (2023): 180–96. http://dx.doi.org/10.3991/ijim.v17i06.38803.

Full text

Abstract:

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS cur

APA, Harvard, Vancouver, ISO, and other styles

37

Nabavi, Morteza, Farhad Ramezankhani, and Maitham Shams. "Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits." IEEE Transactions on Electron Devices 63, no. 3 (2016): 916–24. http://dx.doi.org/10.1109/ted.2016.2517446.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Silva, Otávio Soares, Rodrigo Aparecido da Silva Braga, Dean Bicudo Karolak, and Paulo Marcio Moreira e. Silva. "Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm." Research, Society and Development 9, no. 6 (2020): e51963334. http://dx.doi.org/10.33448/rsd-v9i6.3334.

Full text

Abstract:

Nos processos de fabricação de amplificadores diferenciais integrados uma característica inerente é que os transistores nMOS e pMOS construídos possuam diferenças físicas em relação aos valores projetados, efeito conhecido como descasamento. Neste trabalho será avaliado o impacto que os processos de fabricação infligem em um amplificador operacional de transcondutância construído com transistores com canal uniformemente dopado e baixa tensão de threshold e transistores de canal uniformemente dopado com tensão de threshold regular utilizando uma pesquisa experimental quantitativa.

APA, Harvard, Vancouver, ISO, and other styles

39

Arnaud, F., H. Bernard, Alessio Beverina, et al. "Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement." Solid State Phenomena 103-104 (April 2005): 37–40. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.37.

Full text

Abstract:

This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

APA, Harvard, Vancouver, ISO, and other styles

40

Lapshev, Stepan, and S. M. Rezaul Hasan. "A Low-Power Voltage Limiter/Regulator IC in Standard Thick-Oxide 130 nm CMOS for Inductive Power Transfer Application." Advances in Power Electronics 2014 (December 18, 2014): 1–6. http://dx.doi.org/10.1155/2014/317523.

Full text

Abstract:

This paper presents a novel CMOS low-power voltage limiter/regulator circuit with hysteresis for inductive power transfer in an implanted telemetry application. The circuit controls its rail voltage to the maximum value of 3 V DC employing 100 mV of comparator hysteresis. It occupies a silicon area of only 127 µm × 125 µm using the 130 nm IBM CMOS process. In addition, the circuit dissipated less than 1 mW and was designed using thick-oxide 3.6 V NMOS and PMOS devices available in the process library.

APA, Harvard, Vancouver, ISO, and other styles

41

Zainol Murad, Sohiful Anuar, Azizi Harun, Mohd Nazrin Md Isa, Saiful Nizam Mohyar, and Jamilah Karim. "A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM." Jurnal Teknologi 82, no. 6 (2020): 11–19. http://dx.doi.org/10.11113/jurnalteknologi.v82.15031.

Full text

Abstract:

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results

APA, Harvard, Vancouver, ISO, and other styles

42

van den Born, Erwin, David A. Stein, Patrick L. Iversen, and Eric J. Snijder. "Antiviral activity of morpholino oligomers designed to block various aspects of Equine arteritis virus amplification in cell culture." Journal of General Virology 86, no. 11 (2005): 3081–90. http://dx.doi.org/10.1099/vir.0.81158-0.

Full text

Abstract:

The antiviral efficacy of ten antisense phosphorodiamidate morpholino oligomers (PMOs) directed against Equine arteritis virus (EAV), a nidovirus belonging to the family Arteriviridae, was evaluated in mammalian (Vero-E6) cells. Peptide-conjugated PMOs (P-PMOs) supplied in cell culture medium at micromolar concentrations were efficiently taken up by Vero-E6 cells and were minimally cytotoxic. The P-PMOs were designed to base pair to RNA sequences involved in different aspects of EAV amplification: genome replication, subgenomic mRNA synthesis, and translation of genome and subgenomic mRNAs. A

APA, Harvard, Vancouver, ISO, and other styles

43

Weng, Ming Hung, Muhammad I. Idris, H. K. Chan, et al. "Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices." Materials Science Forum 858 (May 2016): 631–34. http://dx.doi.org/10.4028/www.scientific.net/msf.858.631.

Full text

Abstract:

We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1

APA, Harvard, Vancouver, ISO, and other styles

44

Hussain, S., R. Kumar, and G. Trivedi. "Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology." IOP Conference Series: Materials Science and Engineering 1020 (January 16, 2021): 012022. http://dx.doi.org/10.1088/1757-899x/1020/1/012022.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Shimada, H., Y. Hirano, T. Ushiki, K. Ino, and T. Ohmi. "Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications." IEEE Transactions on Electron Devices 44, no. 11 (1997): 1903–7. http://dx.doi.org/10.1109/16.641359.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Ramakrishna, P., and K. Hari Kishore. "Design of low power 10GS/s 6-Bit DAC using CMOS technology." International Journal of Engineering & Technology 7, no. 1.5 (2017): 226. http://dx.doi.org/10.14419/ijet.v7i1.5.9151.

Full text

Abstract:

A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

APA, Harvard, Vancouver, ISO, and other styles

47

Fu, Xinmiao, Miao He, and Yuan Zhang. "Different improvement designs of conventional comparator." Journal of Physics: Conference Series 2113, no. 1 (2021): 012008. http://dx.doi.org/10.1088/1742-6596/2113/1/012008.

Full text

Abstract:

Abstract Comparators play a significant role in the semiconductor industry and have become indispensable in the design of ADC. The delay and energy consumption are two important indicators of the comparator. Many designs have been made to reduce the delay and energy consumption, such as separated gata-biasing cross-coupled transistors for a new latching stage, and pMOS is used to replace nMOS in comparators. This paper analyzes the working principle of the proposed comparators designed for different needs reported on different papers. It compares their simulation results about key data such as

APA, Harvard, Vancouver, ISO, and other styles

48

Rotondaro, A. L. Pacheco, R. T. Laaksonen, and S. P. Singh. "Impact of the Nitrogen Concentration of Sub-1.3 nm Gate Oxides on 65 nm Technology Transistor Parameters." Journal of Integrated Circuits and Systems 2, no. 2 (2007): 63–66. http://dx.doi.org/10.29292/jics.v2i2.265.

Full text

Abstract:

The nitrogen concentration of ultrathin gate oxides (sub-1.3 nm) was varied in a wide range (from 13 % to 23 %). The threshold voltage and the channel carrier mobility of advanced 65 nm technology CMOSFET transistors fabricated with these oxides were analyzed. It was observed that increasing the nitrogen concentration in the gate oxide results in a negative shift of the threshold voltage for both NMOS and PMOS devices and a degradation of the hole mobility. It was also observed that pchannel transistors are more sensitive to the nitrogen concentration of the gate oxide than n-channel transisto

APA, Harvard, Vancouver, ISO, and other styles

49

Niitsu, Kiichi, Kazunori Sakuma, Naohiro Harigai, et al. "Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements." Key Engineering Materials 596 (December 2013): 176–80. http://dx.doi.org/10.4028/www.scientific.net/kem.596.176.

Full text

Abstract:

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter gene

APA, Harvard, Vancouver, ISO, and other styles

50

Zeeshan A, Mohammed, and Dr Kiran V. "Design and Comparison of Full Adder Using TG Based 4:1 MUX." International Journal of Research and Review 9, no. 11 (2022): 91–95. http://dx.doi.org/10.52403/ijrr.20221115.

Full text

Abstract:

The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder. Keywords: Mux, Full

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!