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Journal articles on the topic 'Nonbinary low-density parity check (LDPC) decoder'

Author: Grafiati

Published: 14 March 2023

Last updated: 31 July 2025

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1

Ramachandran, Varatharajan. "An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 1 (2015): 6. http://dx.doi.org/10.11591/ijres.v4.i1.pp6-12.

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<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefi

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2

Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-B

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Pham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole deco

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Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

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Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated betwe

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5

Sułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.

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Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, t

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M.Sakthivel, Raja M.Karthick, KR.Ragupathy, and Kumar K.Sathis. "PERFORMANCE COMPARISON OF EG-LDPC CODES WITH MAXIMUM LIKELIHOOD ALGORITHM OVER NON-BINARY LDPC CODES." International Journal of Computational Science and Information Technology (IJCSITY) 2, May (2014): 1–11. https://doi.org/10.5281/zenodo.3517939.

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<strong>ABSTRACT </strong> Error correcting coding has become one essential part in nearly all the modern data transmission and storage systems. Low density parity check (LDPC) codes are a class of linear block code has the superior performance closer to the Shannon’s limit. In this paper two error correcting codes from the family of LDPC codes specifically Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Nonbinary low density parity check (NB-LDPC) codes are compared in terms of power consumption, number of iterations and other parameters. For better performance of EG-LDP

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Swapnil, B. Dheple. "ANALYSIS OF REDUCED DECODING COMPLEXITY OF LOW DENSITY PARITY CHECK DECODER." International Journal of Advances in Engineering & Scientific Research 5, no. 1 (2018): 16–21. https://doi.org/10.5281/zenodo.10776884.

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<strong>ABSTRACT</strong>   <em>The approach of this paper to reduce decoding complexity of Low density parity check decoder(LDPC). For that technique uses high precision soft messages at the variable node and put down the message length, due to this number of interconnection between check node and variable node will reduce. For the designing and simulation purposes LDPC uses min-sum algorithm. In min-sum algorithm quite increment in complexity so modified min-sum  algorithm is use to reduce decoding complexity. A design model of this decoder uses for long distance communication appl

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Yashika Gaidhani, Tejaswini Panse, Monica Kalbande,. "A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n." Journal of Electrical Systems 20, no. 2s (2024): 950–58. http://dx.doi.org/10.52783/jes.1742.

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Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adapt

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Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "Low Power QC-LDPC Decoder Based on Token Ring Architecture." Energies 13, no. 23 (2020): 6310. http://dx.doi.org/10.3390/en13236310.

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimizati

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10

Hao, Ning, Yang An Zhang, Jin Nan Zhang, Ming Lun Zhang, and Xue Guang Yuan. "An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel." Applied Mechanics and Materials 347-350 (August 2013): 1864–67. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1864.

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Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

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11

Ali Jassim, Amjad, Wael A. Hadi., and Muhanned Ismael Ibrahim Al-Firas. "Serially Concatenated Low-density Parity Check Codes as Compatible Pairs." International Journal of Engineering & Technology 7, no. 4.15 (2018): 301. http://dx.doi.org/10.14419/ijet.v7i4.15.23013.

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Low-density parity checks (LDPC) codes are considered good performance error correction codes. However, decoder complexity increases with increasing code length. In this study, we introduce short-length serially concatenated LDPC codes. The proposed technique uses pairs of compatible LDPC codes that act as outer and inner serially concatenated codes. In this code pair, the inner code takes input that is the same length as the outer LDPC encoder output. This study examined two cases of LDPC codes as compatible pairs with low numbers of iterations and compared bit error rate (BER) performance to

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Lin, Cheng-Hung, Tzu-Hsuan Huang, Shu-Yen Lin, and Yu-Hsuan Lee. "Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme." Journal of Circuits, Systems and Computers 26, no. 02 (2016): 1750028. http://dx.doi.org/10.1142/s0218126617500281.

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In this paper, we propose an operation-reduced low-density parity check (LDPC) decoder design and implementation by stopping reliable operation of check nodes of the iterative two-phase message passing (TPMP) min-sum algorithm (MSA). A check node stopping (CNS) scheme is used to tag reliability of check nodes by detecting the magnitudes of the check node belief messages with a threshold. The operation of reliable check nodes tagged by the CNS scheme can be stopped in the later iterations. The proposed LDPC decoder that employs the CNS scheme can significantly terminate the redundant operations

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Khittiwitchayakul, Sirawit, Watid Phakphisut, and Pornchai Supnithi. "Associated Sectors of Magnetic Recording Systems Using Spatially Coupled LDPC Codes." ECTI Transactions on Electrical Engineering, Electronics, and Communications 20, no. 1 (2022): 10–21. http://dx.doi.org/10.37936/ecti-eec.2022201.246094.

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In traditional magnetic recording systems, non-associated sectors are mainly adopted, whereby two consecutive sectors are decoded independently by the low-density parity-check (LDPC) codes. In this paper, we propose a magnetic recording system with associated sectors, constructed using spatially coupled low-density parity-check (SC-LDPC) codes. If the SC-LDPC decoder cannot correct the erroneous bits in the current sector, it can request information stored in previous sectors to improve decoding performance. Moreover, we modify protograph-based extrinsic information transfer (P-EXIT) charts to

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El habti El idrissi, Anas, Rachid El Gouri, and Hlou Laamari. "Conception of a new LDPC decoder with hardware implementation on FPGA card." International Journal of Engineering & Technology 3, no. 4 (2014): 451. http://dx.doi.org/10.14419/ijet.v3i4.3185.

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Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission

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El Ouakili, Hajar, Mohammed El Ghzaoui, and Rachid El Alami. "Optimized decoder for low-density parity check codes based on genetic algorithms." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 3 (2024): 2717. http://dx.doi.org/10.11591/ijece.v14i3.pp2717-2724.

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Low-density parity check (LDPC) codes, are a family of error-correcting codes, their performances close to the Shannon limit make them very attractive solutions for digital communication systems. There are several algorithms for decoding LDPC codes that show great diversity in terms of performance related to error correction. Also, very recently, many research papers involved the genetic algorithm (GA) in coding theory, in particular, in the decoding linear block codes case, which has heavily contributed to reducing the bit error rate (BER). In this paper, an efficient method based on the GA i

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Yoo, Heung-Ryol, and Yung-Deug Son. "Hardware Implementation and Validation of Low-Latency LDPC." Korea Industrial Technology Convergence Society 29, no. 1 (2024): 17–25. http://dx.doi.org/10.29279/jitr.2024.29.1.17.

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In this investigation, we developed the hardware for a low-latency low-density parity check (LDPC) decoder and validated its error-correction performance. The LDPC code was chosen as the error-correction code conforming to the international portable Internet standard IEEE 802.16e. The LL-LDPC code, implemented in this study, efficiently minimizes the number of coded calculations through the utilization of a type of Structured-LDPC code defined by the physical layer description in IEEE 802.16e. The low-delay LDPC decoder employs a parallel decoding method to mitigate the decoding delay associat

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Hajar, El Ouakili, El Ghzaoui Mohammed, and El Alami Rachid. "Optimized decoder for low-density parity check codes based on genetic algorithms." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 3 (2024): 2717–24. https://doi.org/10.11591/ijece.v14i3.pp2717-2724.

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Low-density parity check (LDPC) codes, are a family of error-correcting codes, their performances close to the Shannon limit make them very attractive solutions for digital communication systems. There are several algorithms for decoding LDPC codes that show great diversity in terms of performance related to error correction. Also, very recently, many research papers involved the genetic algorithm (GA) in coding theory, in particular, in the decoding linear block codes case, which has heavily contributed toreducing the bit error rate (BER). In this paper, an effic

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18

Mishra, Rajarshini. "Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm." International Journal Of Engineering And Computer Science 7, no. 03 (2018): 23781–84. http://dx.doi.org/10.18535//ijecs/v7i3.21.

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Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many importa

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Wang, Hao-Yu, Zhong-Xun Wang, and Shuo Shang. "An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Fate Array Implementation." Applied Sciences 14, no. 12 (2024): 5162. http://dx.doi.org/10.3390/app14125162.

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Based on the IEEE 802.16e standard’s (672,336) LDPC code and the normalized Min-Sum decoding algorithm, this paper designs and implements an LDPC decoder that optimizes the channel information. The correction factor for check nodes is converted into a correction factor for the initial channel information, replacing the optimization of check node information with that of initial channel information. This achieves decoding performance equivalent to the traditional normalized Min-Sum decoding algorithm. Different correction factor values vary in complexity during FPGA implementation, as they invo

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Thuan. "IMPLEMENTATION OF SOME DECODING ALGORITHMS FOR NB-LDPC CODES ON FPGA." Journal of Military Science and Technology, no. 69A (November 16, 2020): 1–10. http://dx.doi.org/10.54939/1859-1043.j.mst.69a.2020.1-10.

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Non-binary low-density parity-check codes (NB-LDPC) provide better error correction performance in comparison with their counterparts. However, the NB-LDPC decoder has a very high complexity, especially the processing of the check node unit. This paper evaluates the error correction performance of some decoding algorithms for NB-LDPC codes in different fields with different codeword lengths. The paper also presents the results of the implementation a decoder structure for the NB-LDPC (35,23) over GF(8) on the Spartan 6 board. Analysis and evaluation results show that decoding quality on hardwa

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Mao, Yun, Ying Guo, Jun Peng, Xueqin Jiang, and Moon Ho Lee. "Double-Layer Low-Density Parity-Check Codes over Multiple-Input Multiple-Output Channels." International Journal of Antennas and Propagation 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/716313.

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We introduce a double-layer code based on the combination of a low-density parity-check (LDPC) code with the multiple-input multiple-output (MIMO) system, where the decoding can be done in both inner-iteration and outer-iteration manners. The present code, called low-density MIMO code (LDMC), has a double-layer structure, that is, one layer defines subcodes that are embedded in each transmission vector and another glues these subcodes together. It supports inner iterations inside the LDPC decoder and outeriterations between detectors and decoders, simultaneously. It can also achieve the desire

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Zhang, Ji, Anmin Chen, Ying Zhang, Baofeng Ji, Huaan Li, and Hengzhou Xu. "Low-Density Parity-Check Decoding Algorithm Based on Symmetric Alternating Direction Method of Multipliers." Entropy 27, no. 4 (2025): 404. https://doi.org/10.3390/e27040404.

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The Alternating Direction Method of Multipliers (ADMM) has proven to be an efficient approach for implementing linear programming (LP) decoding of low-density parity-check (LDPC) codes. By introducing penalty terms into the LP decoding model’s objective function, ADMM-based variable node penalized decoding effectively mitigates non-integral solutions, thereby improving frame error rate (FER) performance, especially in the low signal-to-noise ratio (SNR) region. In this paper, we leverage the ADMM framework to derive explicit iterative steps for solving the LP decoding problem for LDPC codes wi

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Yao, Chang-Kun, Yun-Ching Tang, and Hongchin Lin. "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA." Journal of Circuits, Systems and Computers 24, no. 02 (2014): 1550026. http://dx.doi.org/10.1142/s0218126615500267.

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This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz a

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Awais, Muhammad, and Carlo Condo. "Flexible LDPC Decoder Architectures." VLSI Design 2012 (June 26, 2012): 1–16. http://dx.doi.org/10.1155/2012/730835.

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluate

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Jung, Jaehwan. "Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems." Electronics 13, no. 7 (2024): 1392. http://dx.doi.org/10.3390/electronics13071392.

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A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the chan

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Anbuselvi, M., P. Saravanan, and S. Joseph Gladwin. "Analysis of a Code Construction Method for Non-Binary Quasi-Cyclic Irregular Low Density Parity Check Decoder." Journal of Computational and Theoretical Nanoscience 15, no. 2 (2018): 719–24. http://dx.doi.org/10.1166/jctn.2018.7151.

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Non-binary LDPC codes is a class of linear block code outperform in the short and moderate block length, closer to Shannon's limit. The numerical strength of the decoder is proportional to the sparsity of the parity check matrix. A Hierarchically Diagonal Parity Check Matrix (HDPCM) with better sparseness is constructed to optimize the computation complexity and decoding performance. The decoder based on the proposed matrix using FFT-SP decoding algorithm is analyzed, with different modulation schemes and channel environment. The positive impact of the constructed matrix is elaborated, conclud

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Tang, Zuo, Jing Lei, and Ying Huang. "EXIT Charts for Low-Density Algebra-Check Codes." Entropy 26, no. 12 (2024): 1118. https://doi.org/10.3390/e26121118.

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This paper focuses on the Low-Density Algebra-Check (LDAC) code, a novel low-rate channel code derived from the Low-Density Parity-Check (LDPC) code with expanded algebra-check constraints. A method for optimizing LDAC code design using Extrinsic Information Transfer (EXIT) charts is presented. Firstly, an iterative decoding model for LDAC is established according to its structure, and a method for plotting EXIT curves of the algebra-check node decoder is proposed. Then, the performance of two types of algebra-check nodes under different conditions is analyzed via EXIT curves. Finally, a low-r

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Thi Bao Nguyen, Tram, Tuy Nguyen Tan, and Hanho Lee. "Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication." Electronics 10, no. 4 (2021): 516. http://dx.doi.org/10.3390/electronics10040516.

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This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CM

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Wang, Zhi Jie, Yan Yan Hao, and Hui Lian. "Effect of Random Jitter on Performance of LDPC." Applied Mechanics and Materials 380-384 (August 2013): 3513–16. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3513.

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Low density parity check codes (LDPC) by now is an excellent channel code that approaches Shannons limit. In order to get the effect of random jitter on performance of LDPC, a simulation model is constructed in this paper. Interpolation, filter delay and decimation methods are used to simulate random jitter induced by circuits of the receiver, changing filter delay to control the jitter step length. Thus the bit error rate of LDPC decoder is gotten that shows the sensitivity of LDPC to synchronization jitter. This paper concludes that, complying with channel coding block in DVB-S2, the bit err

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Tran-Thi, Bich Ngoc, Thien Truong Nguyen-Ly, and Trang Hoang. "An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder." Electronics 12, no. 17 (2023): 3667. http://dx.doi.org/10.3390/electronics12173667.

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A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Ki

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Beuschel, C., and H. J. Pfleiderer. "Hardwarearchitektur für einen universellen LDPC Decoder." Advances in Radio Science 7 (May 19, 2009): 213–18. http://dx.doi.org/10.5194/ars-7-213-2009.

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Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren paralle

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Cai, Fang, and Xinmiao Zhang. "Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 11 (2013): 2010–23. http://dx.doi.org/10.1109/tvlsi.2012.2226920.

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Zhong, Fei, and Shu Xu Guo. "Study on a New Joint Source-Channel Decoder Design." Applied Mechanics and Materials 340 (July 2013): 471–75. http://dx.doi.org/10.4028/www.scientific.net/amm.340.471.

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To improve upon the Low-Density Parity-Check (LDPC) codes , incorporating compressed sensing (CS) and information redundancy, a new joint decoding algorithm frame is presented. The proposed system exploits the information redundancy by CS reconstruction during the iterative decoding process to correct decoding of LDPC codes. The simulation results show that the algorithm presented can improve system decoding performance and obviously make bit error ratio (BER) lower then traditional LDPC codes. In addition, a relatively short argument is given on different CS reconstructed algorithms in propos

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Ismail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

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Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging

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Zhao, Ling, Yi Hou, and Rong Ke Liu. "Layered TPMP Decoding for QC-LDPC Codes." Applied Mechanics and Materials 197 (September 2012): 596–603. http://dx.doi.org/10.4028/www.scientific.net/amm.197.596.

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This paper presents a layered two-phase message passing (L-TPMP) decoding algorithm for general quasi-cyclic low-density parity-check (QC-LDPC) codes, which not only achieves high hardware utilization efficiency (HUE), but also brings in great memory block reduction. The main idea is to split the check matrix into several layers row-wise, then to perform the message passing computations sequentially layer by layer and the two-phase computations of different layers can be overlapped performed. There is no constraint to layer the check matrix hence L-TPMP decoding can be used in both high and lo

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Wang, Zhong-xun, Yang Xi, and Zhan-kai Bao. "Nonbinary Low-Density Parity Check Decoding Algorithm Research-Based Majority Logic Decoding." International Journal of Pattern Recognition and Artificial Intelligence 34, no. 12 (2020): 2058016. http://dx.doi.org/10.1142/s0218001420580161.

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In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the

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Ivanov, Fedor, and Aleksey Kuvshinov. "On the comparison of different serial concatenated schemes based on polar and LDPC codes." Facta universitatis - series: Electronics and Energetics 37, no. 3 (2024): 483–96. https://doi.org/10.2298/fuee2403483i.

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Nowadays concatenated codes are actively developed for different applications of error-correcting theory. In this paper we propose a new method for constructing concatenated codes consisting of some outer error-correcting code and a particular designed inner low-density parity-check (LDPC) code. We consider polarization-adjusted convolutional (PAC) code and LDPC code as outer code of suggested construction. A specialized optimization algorithm was developed to generate inner code with particular error-reducing properties. By using the woven codes decoder with this design, the complexity of the

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Lacruz, Jesus O., Francisco Garcia-Herrero, David Declercq, and Javier Valls. "Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (2015): 1783–92. http://dx.doi.org/10.1109/tvlsi.2014.2344113.

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Lin, Cheng-Hung, Hsin-Hao Su, Tang-Syun Chen, and Cheng-Kai Lu. "Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks." Electronics 11, no. 5 (2022): 733. http://dx.doi.org/10.3390/electronics11050733.

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In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the mi

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Walled Khalid Abdulwahab and Sarmad Mahmood Hadi. "Low Complexity High Throughput Low Density Parity Check Code Based on Compromised Iteration over 5G Out Door Channel." Proceedings of Engineering and Technology Innovation 30 (April 1, 2025): 53–65. https://doi.org/10.46604/peti.2024.14379.

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This paper presents a framework for determining an optimized decoding iteration value for low-density parity-check (LDPC) decoders, considering factors such as error rate performance, complexity, throughput, and latency. The compromised iteration is calculated at a specific signal-to-noise ratio (SNR). At this SNR, the error rate performance of the LDPC code meets the requirement for 5G by achieving a Bit Error Rate (BER) less than 10-4. The optimized decoding iteration value is determined for a given coding length, rate, and communication channel. The system has been evaluated using two chann

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Kakde, Sandeep, Atish Khobragade, Shrikant Ambatkar, and Pranay Nandanwar. "Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm." IIUM Engineering Journal 18, no. 2 (2017): 128–36. http://dx.doi.org/10.31436/iiumej.v18i2.677.

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For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives

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Mitra, Ved, Mahesh C. Govil, Girdhari Singh, and Sanjeev Agrawal. "High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes." Periodica Polytechnica Electrical Engineering and Computer Science 64, no. 2 (2019): 179–91. http://dx.doi.org/10.3311/ppee.14807.

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Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performanc

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Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "FPGA-Oriented LDPC Decoder for Cyber-Physical Systems." Mathematics 8, no. 5 (2020): 723. http://dx.doi.org/10.3390/math8050723.

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A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of

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Wang, Biao. "Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT." Security and Communication Networks 2022 (October 14, 2022): 1–13. http://dx.doi.org/10.1155/2022/4599105.

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As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low s

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TSANG, TONY. "A METHOD FOR PERFORMANCE MODELING AND EVALUATION OF LDPC DECODER ARCHITECTURE." International Journal of Modeling, Simulation, and Scientific Computing 04, no. 02 (2013): 1350003. http://dx.doi.org/10.1142/s1793962313500037.

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This paper presents a high-throughput memory efficient decoder for low density parity check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to our selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the WiGig networks. State-of-the-art flexible LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. This work develops a flexible, fully pipelined architecture for the IEEE 802.11ad standard

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Tuntoolavest, Usana, and Visuttha Manthamkarn. "A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols." Engineering Journal 26, no. 9 (2022): 35–46. http://dx.doi.org/10.4186/ej.2022.26.9.35.

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Wang, Zhong Xun, and Xing Long Gao. "Design of Modified Minsum Decoder of LDPC Code in the Simplified Difference-Domain." Applied Mechanics and Materials 385-386 (August 2013): 1576–81. http://dx.doi.org/10.4028/www.scientific.net/amm.385-386.1576.

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In this paper, we propose the modified minsum decoding algorithm of LDPC(Low-Density Parity-Check) code in the simplified difference-domain on the basis of detailed analysis of LDPC decoding algorithm in difference-domain. The simulation indicates that the proposed decoding algorithm offers almost no performance degradation compared with the BP(Belief Propagation) decoding algorithm in log-domain and the decoding algorithm in difference-domain and offers better performance than minsum decoding algorithm in log-domain and greatly reduces the computation complexity in AWGN(Additive White Gaussia

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Mosleh, Mahmood Farhan, Fadhil Sahib Hasan, and Ruaa Majeed Azeez. "Design and implementation of log domain decoder." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1454. http://dx.doi.org/10.11591/ijece.v10i2.pp1454-1468.

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Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very cl

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Mahmood, Farhan Mosleh, Sahib Hasan Fadhil, and Majeed Azeez Ruaa. "Design and implementation of log domain decoder." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1454–568. https://doi.org/10.11591/ijece.v10i2.pp1454-1568.

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Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very clo

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Cuc, Adriana-Maria, Florin Lucian Morgoș, Adriana-Marcela Grava, and Cristian Grava. "Iterative Equalization and Decoding over an Additive White Gaussian Noise Channel with ISI Using Low-Density Parity-Check Codes." Applied Sciences 13, no. 22 (2023): 12294. http://dx.doi.org/10.3390/app132212294.

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In this article we present an iterative system of equalization and decoding to manage the intersymbol interference over an additive white Gaussian noise (AWGN) channel. Following the classic turbo equalization scheme, the proposed system consists of low-density parity-check (LDPC) coding at the transmitter side; we applied a Log maximum a posteriori probability (Log-MAP) equalizer and min-sum LDPC decoding at the receiver side. The equalizer and decoder, linked through interleaving and deinterleaving, iteratively update each other’s information. We performed the performance analysis of the pro

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