Relevant bibliographies by topics / Novel processor architecture

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Novel processor architecture'

Author: Grafiati
Published: 4 June 2021
Last updated: 2 February 2022

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Journal articles on the topic "Novel processor architecture"

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Yantır, Hasan Erdem, Wenzhe Guo, Ahmed M. Eltawil, Fadi J. Kurdahi, and Khaled Nabil Salama. "An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor." Micromachines 10, no. 8 (July 31, 2019): 509. http://dx.doi.org/10.3390/mi10080509.

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Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.
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Göhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

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Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.
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Meyer, M. "A novel processor architecture with exact tag-free pointers." IEEE Micro 24, no. 3 (May 2004): 46–55. http://dx.doi.org/10.1109/mm.2004.2.

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Karmakar, Amiya, Amitabha Sinha, Pratik Kumar Sinha, and Pijush Biswas. "Architecture of a Novel Configurable Communication Processor for SDR." International Journal of VLSI Design & Communication Systems 6, no. 4 (August 30, 2015): 35–49. http://dx.doi.org/10.5121/vlsic.2015.6404.

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Bu, Wei Jing. "A Novel Numerical Control Architecture Based on Multiprocessor and Real-Time Ethernet." Applied Mechanics and Materials 155-156 (February 2012): 120–24. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.120.

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The design of the CNC system to realize the function of the dedicated processor/modular is very select. Low cost of the ARM processor with Windows CE operating system is perfect for soft real-time tasks, such as the system state display, program explains, etc. The high performance DSP processors µ C/OS-II operating system is real-time tasks efforts, which is responsible for interpolation, speed control. In addition, to meet demand for the reconstruction of the design and flexible manufacturing, a reconfigurable based on FPGA technology for module, meet the functional requirement, build the PLC based on real-time Ethernet field bus network for simple connections between executors in the numerical control system controller.
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Yang, Liu, Xiao Qiang Ni, and Heng Zhu Liu. "Implementing and Optimizing DES on Stream Processor." Advanced Materials Research 532-533 (June 2012): 714–18. http://dx.doi.org/10.4028/www.scientific.net/amr.532-533.714.

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Processors using stream architecture can make good use of the on-chip resources and explore the data locality and parallelism. DES algorithm is one of the most popular cipher algorithms. This paper proposes the novel implementation of DES algorithm on stream architecture based on both stream programming model and DES algorithm and the speedup is 1.27 times.
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Yang, Hui, Shu Ming Chen, and Tie Bin Wu. "A Novel Two-Level Instruction Issue Window Based on VLIW Architecture." Advanced Materials Research 317-319 (August 2011): 146–49. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.146.

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Instruction compression technique overcomes the drawbacks of traditional VLIW architectures with low density in the instruction cache. However, the separated long instruction word was arranged into two cache line. It comes to be a bottleneck problem for VLIW architecture processor performance because these split long instruction word can not be fetched and issued simultaneously. A novel two-level instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and stores one iteration of the loop body to support software pipeline technique, which improves VLIW DSP processor performance effectively. Proposed machanism was synthesized to evaluate its overall costs, and the performance speedup result for DSP/IMG library bencharks using the cycle accurate simulator are presented.
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L.Giridas, K., and A. Shajin Nargunam. "A Novel Architecture for Hybrid Processor Pool Model using IITPS Scheme." International Journal of Computer Applications 49, no. 5 (July 28, 2012): 20–25. http://dx.doi.org/10.5120/7624-0684.

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Dong, Jing Chuan, Tai Yong Wang, Bo Li, Xian Wang, and Zhe Liu. "Design and Implementation of an Interpolation Processor for CNC Machining." Advanced Materials Research 819 (September 2013): 322–27. http://dx.doi.org/10.4028/www.scientific.net/amr.819.322.

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As the demand for high speed and high precision machining increases, the fast and accurate real-time interpolation is necessary in modern computerized numerical control (CNC) systems. However, the complexity of the interpolation algorithm is an obstacle for the embedded processor to achieve high performance control. In this paper, a novel interpolation processor is designed to accelerate the real-time interpolation algorithm. The processor features an advanced parallel architecture, including a 3-stage instruction pipeline, very long instruction word (VLIW) support, and asynchronous instruction execution mechanism. The architecture is aimed for accelerating the computing-intensive tasks in CNC systems. A prototype platform was built using a low-cost field programmable gate array (FPGA) chip to implementation the processor. Experimental result has verified the design and showed the good computing performance of the proposed architecture.
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Issa, Joseph. "A Novel Method to Predict Processor Performance by Modeling Different Architecture Parameters." Journal of Computer Science 16, no. 4 (April 1, 2020): 479–92. http://dx.doi.org/10.3844/jcssp.2020.479.492.

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Dissertations / Theses on the topic "Novel processor architecture"

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Lakshmanan, Karthick. "Design of an Automation Framework for a Novel Data-Flow Processor Architecture." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34193.

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Improved process technology has resulted in the integration of computing elements into multiple application areas. General purpose micro-controllers are designed to assist in this integration through a flexible design. The application areas, however, are so diverse in nature that the general purpose micro-controllers may not provide a suitable abstraction for all classes of applications. There is a need for specially designed architectures in application areas where the general purpose micro-controllers suffer from inefficiencies. This thesis focuses in the design of a processor architecture that provides a suitable design abstraction for a class of periodic, event-driven embedded applications such as sensor-monitoring systems. The design principles of the processor architecture are focused on the target application requirements, which are identified as event-driven nature with concurrent task execution and deterministic timing behavior. Additionally, to reduce the design complexity of applications on this novel architecture, an automation framework has been implemented. This thesis presents the design of the processor architecture and the automation framework explaining the suitability of the designed architecture for the target applications. The energy use of the novel architecture is compared with that of PIC12F675 micro-controller to demonstrate the energy-efficiency of the designed architecture.
Master of Science
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Jones, Daniel. "High speed simulation of microprocessor systems using LTU dynamic binary translation." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4609.

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This thesis presents new simulation techniques designed to speed up the simulation of microprocessor systems. The advanced simulation techniques may be applied to the simulator class which employs dynamic binary translation as its underlying technology. This research supports the hypothesis that faster simulation speeds can be realized by translating larger sections of the target program at runtime. The primary motivation for this research was to help facilitate comprehensive design-space exploration and hardware/software co-design of novel processor architectures by reducing the time required to run simulations. Instruction set simulators are used to design and to verify new system architectures, and to develop software in parallel with hardware. However, compromises must often be made when performing these tasks due to time constraints. This is particularly true in the embedded systems domain where there is a short time-to-market. The processing demands placed on simulation platforms are exacerbated further by the need to simulate the increasingly complex, multi-core processors of tomorrow. High speed simulators are therefore essential to reducing the time required to design and test advanced microprocessors, enabling new systems to be released ahead of the competition. Dynamic binary translation based simulators typically translate small sections of the target program at runtime. This research considers the translation of larger units of code in order to increase simulation speed. The new simulation techniques identify large sections of program code suitable for translation after analyzing a profile of the target program’s execution path built-up during simulation. The average instruction level simulation speed for the EEMBC benchmark suite is shown to be at least 63% faster for the new simulation techniques than for basic block dynamic binary translation based simulation and 14.8 times faster than interpretive simulation. The average cycle-approximate simulation speed is shown to be at least 32% faster for the new simulation techniques than for basic block dynamic binary translation based simulation and 8.37 times faster than cycle-accurate interpretive simulation.
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Fox, Michael A. (Michael Allan). "Novel affordances of computation to the design processes of kinetic structures." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/10995.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1996.
Includes bibliographical references (leaves 44-45).
This paper is a discourse into the relationship between the process, computational tools and the role which symbolic structure can play in both. I argue the relationship of the process and tools is dialectic, whereby the tools we utilize in design develop new heuristics, the methodologies in tum, if reflectively understood, can be more aptly facilitated through the development of novel tools. The tools and the process then evolve together. A theory is laid out exploring the human visual information processing systems pertinence to the limitations in mental three-dimensional imaging and transformation operations relevant to the operations of drawing and mental visualization within the architectural design processes, substantiating the designers "necessity" to d raw (by traditional means, but more importantly here, through the inclusive integration of CAD within the process). The "necessity" to draw is explored as a re-presentational process to the visual system predicated upon the existence of a structured internal "library" of diagram-like representations. I argue that the ways we utilize such idiosyncratic libraries is predicated upon the ways in which we go about structuring the perceived "experienced" world around us into "symbol systems". And finally, the ways we utilize our reflective understanding of the heuristic transformations of these "symbols" within the design process in the context of a CAD environment are explored as a means to an enhanced understanding of that which is being designed and consequently as a vehicle for the development of future CAD systems to better facilitate such methodologies of designing. A personal design process of several kinetic structures is carried out in order to arrive at a localized process analysis within computer-aided design environment. Through an interactive, reflective process analysis, conclusions are drawn as to the affordances and limitations of such tools as suggestive of the operations a CAD environment might perform so as to better foster future methodologies of designing. The design "experiments" are utilized as a vehicle to understand the process. Specifically three kinetic projects are exploited for the prototypical "operations" they display. When difficulties or mental limitations are encountered with the operations, specific "tools" are developed to facilitate the limitation or to overcome the problem.
by Michael A. Fox.
M.S.
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Hayes, Timothy. "Novel vector architectures for data management." Doctoral thesis, Universitat Politècnica de Catalunya, 2015. http://hdl.handle.net/10803/397645.

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As the rate of annual data generation grows exponentially, there is a demand to manage, query and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. Today, Dennard scaling has ceased, and further performance must come from exploiting parallelism. Vector architectures offer a highly efficient and scalable way of exploiting data-level parallelism (DLP) through sophisticated single instruction-multiple data (SIMD) instruction sets. Traditionally, vector machines were used to accelerate scientific workloads rather than business-domain applications. In this thesis, we design innovative vector extensions for a modern superscalar microarchitecture that are optimised for data management workloads. Based on extensive analysis of these workloads, we propose new algorithms, novel instructions and microarchitectural optimisations. We first profile a leading commercial decision support system to better understand where the execution time is spent. We find that the hash join operator is responsible for a significant portion of the time. Based on our profiling, we develop lightweight integer-based pipelined vector extensions to capture the DLP in the operator. We then proceed to implement and evaluate these extensions using a custom simulation framework based on PTLsim and DRAMSim2. We motivate key design decisions based on the structure of the algorithm and compare these choices against alternatives experimentally. We discover that relaxing the base architecture's memory model is very beneficial when executing a vectorised implementation of the algorithm. This relaxed model serves as a powerful mechanism to execute indexed vector memory instructions out of order without requiring complex associative hardware. We find that our vectorised implementation shows good speedups. Furthermore, the vectorised version exhibits better scalability compared to the original scalar version run on a microarchitecture with larger superscalar and out-of-order structures. We then make a detailed study of SIMD sorting algorithms. Using our simulation framework, we evaluate the strengths, weaknesses and scalability of three diverse vectorised sorting algorithms- quicksort, bitonic mergesort and radix sort. We find that each of these algorithms has its unique set of bottlenecks. Based on these findings, we propose VSR sort- a novel vectorised non-comparative sorting algorithm that is based on radix sort but without its drawbacks. VSR sort, however, cannot be implemented directly with typical vector instructions due to the irregularity of its DLP. To facilitate the implementation of this algorithm, we define two new vector instructions and propose a complementary hardware structure for their execution. We find that VSR sort significantly outperforms each of the other vectorised algorithms. Next, we propose and evaluate five different ways of vectorising GROUP BY data aggregations. We find that although data aggregation algorithms are abundant in DLP, it is often too irregular to be expressed efficiently using typical vector instructions. By extending the hardware used for VSR sort, we propose a set of vector instructions and novel algorithms to better capture this irregular DLP. Furthermore, we discover that the best algorithm is highly dependent on the characteristics of the input. Finally, we evaluate the area, energy and power of these extensions using McPAT. Our results show that our proposed vector extensions come with a modest area overhead, even when using a large maximum vector length with lockstepped parallel lanes. Using sorting as a case study, we find that all of the vectorised algorithms consume much less energy than their scalar counterpart. In particular, our novel VSR sort requires an order of magnitude less energy than the scalar baseline. With respect to power, we discover that our vector extensions present a very reasonable increase in wattage.
El crecimiento exponencial de la ratio de creación de datos anual conlleva asociada una demanda para gestionar, consultar y resumir cantidades enormes de información rápidamente. En el pasado, se confiaba en el escalado de la frecuencia de los procesadores para incrementar el rendimiento. Hoy en día los incrementos de rendimiento deben conseguirse mediante la explotación de paralelismo. Las arquitecturas vectoriales ofrecen una manera muy eficiente y escalable de explotar el paralelismo a nivel de datos (DLP, por sus siglas en inglés) a través de sofisticados conjuntos de instrucciones "Single Instruction-Multiple Data" (SIMD). Tradicionalmente, las máquinas vectoriales se usaban para acelerar aplicaciones científicas y no de negocios. En esta tesis diseñamos extensiones vectoriales innovadoras para una microarquitectura superescalar moderna, optimizadas para tareas de gestión de datos. Basándonos en un extenso análisis de estas aplicaciones, también proponemos nuevos algoritmos, instrucciones novedosas y optimizaciones en la microarquitectura. Primero, caracterizamos un sistema comercial de soporte de decisiones. Encontramos que el operador "hash join" es responsable de una porción significativa del tiempo. Basándonos en nuestra caracterización, desarrollamos extensiones vectoriales ligeras para datos enteros, con el objetivo de capturar el paralelismo en este operandos. Entonces implementos y evaluamos estas extensiones usando un simulador especialmente adaptado por nosotros, basado en PTLsim y DRAMSim2. Descubrimos que relajar el modelo de memoria de la arquitectura base es altamente beneficioso, permitiendo ejecutar instrucciones vectoriales de memoria indexadas, fuera de orden, sin necesitar hardware asociativo complejo. Encontramos que nuestra implementación vectorial consigue buenos incrementos de rendimiento. Seguimos con la realización de un estudio detallado de algoritmos de ordenación SIMD. Usando nuestra infraestructura de simulación, evaluamos los puntos fuertes y débiles así como la escalabilidad de tres algoritmos vectorizados de ordenación diferentes quicksort, bitonic mergesort y radix sort. A partir de este análisis, proponemos "VSR sort" un nuevo algoritmo de ordenación vectorizado, basado en radix sort pero sin sus limitaciones. Sin embargo, VSR sort no puede ser implementado directamente con instrucciones vectoriales típicas, debido a la irregularidad de su DLP. Para facilitar la implementación de este algoritmo, definimos dos nuevas instrucciones vectoriales y proponemos una estructura hardware correspondiente. VSR sort consigue un rendimiento significativamente más alto que los otros algoritmos. A continuación, proponemos y evaluamos cinco maneras diferentes de vectorizar agregaciones de datos "GROUP BY". Encontramos que, aunque los algoritmos de agregación de datos tienen DLP abundante, frecuentemente este es demasiado irregular para ser expresado eficientemente usando instrucciones vectoriales típicas. Mediante la extensión del hardware usado para VSR sort, proponemos un conjunto de instrucciones vectoriales y algoritmos para capturar mejor este DLP irregular. Finalmente, evaluamos el área, energía y potencia de estas extensiones usando McPAT. Nuestros resultados muestran que las extensiones vectoriales propuestas conllevan un aumento modesto del área del procesador, incluso cuando se utiliza una longitud vectorial larga con varias líneas de ejecución vectorial paralelas. Escogiendo los algoritmos de ordenación como caso de estudio, encontramos que todos los algoritmos vectorizados consumen mucha menos energía que una implementación escalar. En particular, nuestro nuevo algoritmo VSR sort requiere un orden de magnitud menos de energía que el algoritmo escalar de referencia. Respecto a la potencia disipada, descubrimos que nuestras extensiones vectoriales presentan un incremento muy razonable
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Xu, Li-Qun, and 許立群. "A Novel Processor Architecture for 3D Graphics Perspective Texture Mapping." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/93587717807331201770.

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Hsui, Li-Chyun, and 許立群. "A Novel Processor Architecture for 3D Graphics Perspective Texture Mapping." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/90087361694712770188.

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碩士
國立交通大學
電子工程學系
85
3D computer graphics has becoming more and more important in modern multimedia and virtual reality systems. In this area, texture mapping is one of the most successful techniques which can make images look more realistic and complex. In this thesis, a perspective texture mapping processor (PTMP) is designed and implemented to improve the texture mapping performance of computer graphics. The PTMP can give the proper effort of foreshortening on texture mapped polygon. The hardware of rasterization and anti-aliasing is incorporated into PTMP.The features of this design include modified four sided polygon scan-converter, logarithm space divider, and simplified algorithms for anti-aliasing. To enhance rendering speed and throughput, the fully pipelined architecture is designed. By analyzing data flows and operations, many resource sharing techniques can be utilized to reducehardware cost. The post layout simulation results show that the system can operate up to 71MHz. That is, the pixel rate is 17.85M pixels per second and 158.67K 10 * 10, Z buffered, polygon rate per second can be achieved. The gate count of the PTMP is about 30K, and the die size is 7522mm*6107mm. The whole chip is designed and implemented with COMPASS 0.6mm HP CMOS cell library, and it is currently under fabrication through NSC/CIC MPC services.
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Shepherd, Simon J., James M. Noras, and Yuan Zhou. "Novel design of multiplier-less FFT processors." 2007. http://hdl.handle.net/10454/3129.

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This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.
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Books on the topic "Novel processor architecture"

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Casasent, David Paul. Novel parallel architectures and algorithms for linear algebra processors: Progress report, grant NAG-1-575. [Washington, D.C: National Aeronautics and Space Administration, 1987.

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Book chapters on the topic "Novel processor architecture"

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Wu, Xiaofeng, Vassilios Chouliaras, Jose Nunez-Yanez, Roger Goodall, and Tanya Vladimirova. "A Novel Processor Architecture for Real-Time Control." In Advances in Computer Systems Architecture, 270–80. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_22.

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Shoufan, Abdulhadi, Sorin A. Huss, and Murtuza Cutleriwala. "A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management." In High Performance Embedded Architectures and Compilers, 169–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11587514_12.

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Bauer, Lars, Hongyan Zhang, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, and Jörg Henkel. "Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures." In Dependable Embedded Systems, 277–302. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_12.

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AbstractRuntime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.
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Konrad, Mirjam, Dana Saez, and Martin Trautz. "Integration of Algorithm-Based Optimization into the Design Process of Industrial Buildings: A Case Study." In Proceedings of the 2021 DigitalFUTURES, 179–88. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5983-6_17.

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AbstractAlgorithm-based optimization is widely applied in many fields like industrial production, resulting in state-of-the-art workflows in the production process optimization. This project takes the cultural lag of conventional industrial architecture design as a motivation to investigate the implementation of algorithm-based optimization into traditional design processes. We argue that an enhanced way of architectural decision-making is possible. Current approaches use a translation of the whole design problem into a single, overly complicated optimization system. Contrary to that, this paper presents a novel workflow that defines precise design steps and applies optimizations only if suitable. Furthermore, this method can generate relevant results for factory planning design problems with contradicting factors, making it a promising approach for the complex challenges of i.e. resource-efficient building.
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Mohamed, H., D. W. Bao, and R. Snooks. "Super Composite: Carbon Fibre Infused 3D Printed Tectonics." In Proceedings of the 2020 DigitalFUTURES, 297–308. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4400-6_28.

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AbstractThis research posits an innovative process of embedding carbon fibre as the primary structure within large-scale polymer 3D printed intricate architectural forms. The design and technical implications of this research are explored and demonstrated through two proto-architectural projects, Cloud Affects and Unclear Cloud, developed by the RMIT Architecture Snooks Research Lab. These projects are designed through a tectonic approach that we describe as a super composite – an approach that creates a compression of tectonics through algorithmic self-organisation and advanced manufacturing. Framed within a critical view of the lineage of polymer 3D printing and high tech fibres in the field of architectural design, the research outlines the limitations of existing robotic processes employed in contemporary carbon fibre fabrication. In response, the paper proposes an approach we describe as Infused Fibre Reinforced Plastic (IFRP) as a novel fabrication method for intricate geometries. This method involves 3D printing of sacrificial formwork conduits within the skin of complex architectural forms that are infused with continuous carbon fibre structural elements. Through detailed observation and critical review of Cloud Affects and Unclear Cloud (Fig. 2), the paper assesses innovations and challenges of this research in areas including printing, detailing, structural analysis and FEA modelling. The paper notes how these techniques have been refined through the iterative design of the two projects, including the development of fibre distribution mapping to optimise the structural performance.
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Miriyala, Srinivas Soumitri, Itishree Mohanty, and Kishalay Mitra. "Performance Improvement in Hot Rolling Process with Novel Neural Architectural Search." In Management and Industrial Engineering, 177–97. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-75847-9_9.

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Zhu, Erzhou, Meng Li, Jia Xu, Xuejun Li, Feng Liu, and Futian Wang. "TIMOM: A Novel Time Influence Multi-objective Optimization Cloud Data Storage Model for Business Process Management." In Algorithms and Architectures for Parallel Processing, 315–29. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-38991-8_21.

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Gandor, Malin, Nicolas Jäckel, Lorenz Käser, Alexander Schlie, Ingo Stierand, Axel Terfloth, Steffen Toborg, Louis Wachtmeister, and Anna Wißdorf. "Architectures for Dynamically Coupled Systems." In Model-Based Engineering of Collaborative Embedded Systems, 95–124. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-62136-0_5.

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AbstractDynamically coupled collaborative embedded systems operate in groups that form, change, and dissolve—often frequently—during their lifetime. Furthermore, the context in which collaborative systems operate is a dynamic one: systems in the context may appear, change their visible behavior, and disappear again. Ensuring safe operation of such collaborative systems is of key importance, while their dynamic nature poses challenges that do not occur in “classical” system design. This starts with the elicitation of the operational context against which the system will be designed—requiring capture of its dynamic nature—and affects all other design phases as well. Novel development methods are required, enabling engineers to deal with the challenges raised by dynamicity in a manageable way. This chapter presents methods that have been developed to support engineers in this task. The methods cover different viewpoints and abstraction levels of the development process, starting at the requirements viewpoint, and glance at the functional and technical design, as well as verification methods for the type of systems envisioned.
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Daneluzzo, Mirko, and Michele Daneluzzo. "Reinventing Staircases for Thermoplastic Additive Manufacturing." In Proceedings of the 2021 DigitalFUTURES, 349–58. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5983-6_32.

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AbstractThe paper presents an ongoing project focusing on the application of additive manufacturing technologies for the design of staircases. Additive digital fabrication allows architects to reinvestigate materials, processes, and creates new design opportunities to explore novel aesthetical and functional expression in architecture, enabling a reinterpretation of the typology of the staircase, using thermoplastic materials. This paper reviews the opportunities and challenges of using 3D printing for fabricating custom stairs with complex geometries in two studied configurations.
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Chen, Yuhan, Youyu Lu, Tianyi Gu, Zhirui Bian, Likai Wang, and Ziyu Tong. "From Separation to Incorporation - A Full-Circle Application of Computational Approaches to Performance-Based Architectural Design." In Proceedings of the 2021 DigitalFUTURES, 189–98. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5983-6_18.

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AbstractIn performance-based architectural design, most existing techniques and design approaches to assisting designers are primarily for a single design problem such as building massing, spatial layouts, or facade design. However, architectural design is a synthesis process that considers multiple design problems. Thus, for achieving an overall improvement in building performance, it is critical to incorporate computational techniques and methods into all key design problems. In this regard, this paper presents a full-circle application of different computational design approaches and tools to exploit the potential of building performance in driving architectural design towards more novel and sustainable buildings as well as to explore new research design paradigms for performance-based architectural design in real-world design scenarios. This paper takes a commercial complex building design as an example to demonstrate how building performance can be incorporated into different building design problems and reflect on the limitations of existing tools in supporting the architectural design.
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Conference papers on the topic "Novel processor architecture"

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Srivastava, Harshit, and Noor Mahammad Sk. "A novel flexible baseband processor architecture framework." In 2014 International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2014. http://dx.doi.org/10.1109/spin.2014.6777007.

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Hihara, Hiroki, Akira Iwasaki, Nobuo Tamagawa, Mitsunobu Kuribayashi, Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, et al. "Novel processor architecture for onboard infrared sensors." In SPIE Optical Engineering + Applications, edited by Marija Strojnik. SPIE, 2016. http://dx.doi.org/10.1117/12.2237433.

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Hung, Jen-Sheng, Chia-Hsing Lin, and Chein-Wei Jen. "Novel memory architecture for video signal processor." In Video Communications and Fiber Optic Networks, edited by Naohisa Ohta. SPIE, 1993. http://dx.doi.org/10.1117/12.161478.

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Tajahuerce, Enrique, Jesus S. Lancis, Vicent Climent, Mercedes Fernandez-Alonso, and Pedro Andres. "Achromatic Fourier processor: a novel optical architecture." In Second Iberoamerican Meeting on Optics, edited by Daniel Malacara-Hernandez, Sofia E. Acosta-Ortiz, Ramon Rodriguez-Vera, Zacarias Malacara, and Arquimedes A. Morales. SPIE, 1996. http://dx.doi.org/10.1117/12.231105.

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Zode, Pravin P., and R. B. Deshmukh. "Novel fault attack resistant Elliptic Curve processor architecture." In 2014 Annual IEEE India Conference (INDICON). IEEE, 2014. http://dx.doi.org/10.1109/indicon.2014.7030395.

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Song, William S., Vitaliy Gleyzer, Alexei Lomakin, and Jeremy Kepner. "Novel graph processor architecture, prototype system, and results." In 2016 IEEE High Performance Extreme Computing Conference (HPEC). IEEE, 2016. http://dx.doi.org/10.1109/hpec.2016.7761635.

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Kemeny, S. E., E. S. Eid, and E. R. Fossum. "Novel CCD Image Processor For Z-Plane Architecture." In SPIE 1989 Technical Symposium on Aerospace Sensing, edited by John C. Carson. SPIE, 1989. http://dx.doi.org/10.1117/12.960372.

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Kondo, M., H. Okawara, H. Nakamura, T. Boku, and S. Sakai. "SCIMA: a novel processor architecture for high performance computing." In Proceedings Fourth International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region. IEEE, 2000. http://dx.doi.org/10.1109/hpc.2000.846577.

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Kalendar, Marija, Danijela Jakimovska, Aristotel Tentov, and Goce Dokoski. "Novel processor architecture for modified advanced routing in NGN." In the 2011 ACM Symposium. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/1982185.1982292.

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Ignat, Cristian, Paul Farago, and Sorin Hintea. "FPGA Implementation of a Novel Dual - BRAM Processor Architecture." In 2020 43rd International Conference on Telecommunications and Signal Processing (TSP). IEEE, 2020. http://dx.doi.org/10.1109/tsp49548.2020.9163584.

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Reports on the topic "Novel processor architecture"

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Klenke, Robert. Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,. Fort Belvoir, VA: Defense Technical Information Center, July 2006. http://dx.doi.org/10.21236/ada455450.

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