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Relevant bibliographies by topics / NWFET-Nanowire FET

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Journal articles
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Academic literature on the topic 'NWFET-Nanowire FET'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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Journal articles on the topic "NWFET-Nanowire FET"

1

Kumar, Deepak, and Shamsher Singh. "TRAP CHARGES INDUCED IMMUNITY IN DUAL METAL GATE (DMG) JUNCTIONLESS ACCUMULATION MODE (JAM) NANOWIRE FET (NWFET)." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1209–15. https://doi.org/10.21917/ijme.2021.0208.

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In this brief, we have done a comparative study of Single Metal Gate Junctionless Accumulation Mode Nanowire FET (SMG-JAM-NWFET) and Dual Metal Gate Junctionless Accumulation Mode Nanowire FET (DMG-JAM-NWFET) for their immunity against the trap induced charges. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the potential, current, transconductance and output conductance. Aberration in other parameters like drain characteristics, Subthreshold Slope, capacitances and cut-off

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Bharti and Poornima Mittal. "Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation." ECS Journal of Solid State Science and Technology 13, no. 1 (2024): 013004. http://dx.doi.org/10.1149/2162-8777/ad1c90.

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Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, g

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3

Choi, Yejoo, Jinwoong Lee, Jaehyuk Lim, Seungjun Moon, and Changhwan Shin. "Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET." Electronics 10, no. 16 (2021): 1899. http://dx.doi.org/10.3390/electronics10161899.

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In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS

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Bharti and Poornima Mittal. "Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis." Physica Scripta 99, no. 8 (2024): 086103. http://dx.doi.org/10.1088/1402-4896/ad63d4.

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Abstract An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into th

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5

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this r

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6

Bharti and Poornima Mittal. "Analytical modeling of fringe capacitance in opposite-doped core-shell junctionless nanowire FET." Engineering Research Express 7, no. 1 (2025): 015385. https://doi.org/10.1088/2631-8695/adc0ec.

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Abstract An analytical model of Oppositely Doped Core–Shell Junctionless Nanowire Field Effect Transistor (ODCS-JL-NWFET) using surface potential is proposed in this paper. The model incorporates the influence of fringe capacitance through the gate sidewall spacer on the potential distribution function. The analytical results align well with simulated outcomes across various ODCS-JL-NWFET physical parameters, such as threshold voltage, drain current, and subthreshold slope. Furthermore, the model illustrates the impact of channel length scaling on device parameters for different core thickness

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7

Ditshego, Nonofo M. J. "ZnO Nanowire Field Effect Transistor for Biosensing: A Review." Journal of Nano Research 60 (November 2019): 94–112. http://dx.doi.org/10.4028/www.scientific.net/jnanor.60.94.

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The last 19 years have seen intense research made on zinc oxide (ZnO) material mainly due to the ability of converting the natural n-type material into p-type. For a long time, the p-type state was impossible to attain and maintain. The review focuses on ways of improving the doped ZnO material which acts as a channel for nanowire field effect transistor (NWFET) and biosensor. The biosensor has specific binding which is called functionalisation achieved by attaching a variety of compounds on the designated sensing area. Reference electrodes and buffers are used as controllers. Top-down fabrica

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8

Thakur, Rajiv Ranjan, and Nidhi Chaturvedi. "Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications." Nano 16, no. 08 (2021): 2150096. http://dx.doi.org/10.1142/s179329202150096x.

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In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text]

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Song, Taigon. "Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm." IEEE Transactions on Nanotechnology 18 (2019): 240–51. http://dx.doi.org/10.1109/tnano.2019.2896362.

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10

Gong, Xiao, Kaizhen Han, Chen Sun, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.

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Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research developmen

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Dissertations / Theses on the topic "NWFET-Nanowire FET"

1

Narendar, Harish. "A Simulation Study of Enhancement mode Indium Arsenide Nanowire Field Effect Transistor." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1259080514.

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Book chapters on the topic "NWFET-Nanowire FET"

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Bala, Shashi, Raj Kumar, Jeetendra Singh, and Sanjeev Kumar Sharma. "Design and Simulation Analysis of NWFET for Digital Application." In Advances in Computer and Electrical Engineering. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch006.

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This chapter presents the design and simulation analysis nanowire-based FET (NWFET) for best possible Ig-Vgs characteristics. A NWFET is a device in which channel is wire-like structure with diameter or lateral dimension in nanometer (10-9 m) range. Performance analysis has been done for various design and process parameters variation to propose optimized parameter for best performance. Although a lot of focus has been put on homogenous Si based NWFETs, there has been a rising interest in III-V NWFETs. This is mainly due to the excellent carrier transport properties are provided by these mater

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2

Mathiba Jack Ditshego, Nonofo. "ZnO Nanowire Field-Effect Transistor for Biosensing: A Review." In Nanowires - Recent Progress [Working Title]. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.93707.

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The last 19 years have seen intense research made on zinc oxide (ZnO) material, mainly due to the ability of converting the natural n-type material into p-type. For a long time, the p-type state was impossible to attain and maintain. This chapter focuses on ways of improving the doped ZnO material which acts as a channel for nanowire field-effect transistor (NWFET) and biosensor. The biosensor has specific binding which is called functionalization that is achieved by attaching a variety of compounds on the designated sensing area. Reference electrodes and buffers are used as controllers. Top-d

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3

Kumar, Raj, Shashi Bala, and Arvind Kumar. "Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors." In Advances in Computer and Electrical Engineering. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch003.

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To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties

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Conference papers on the topic "NWFET-Nanowire FET"

1

Yadav, Shivani, and Sonam Rewari. "Trench Gate JAM Dielectric Modulated Nanowire FET (TG-JAM-DM-NWFET) Biosensor." In 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). IEEE, 2022. http://dx.doi.org/10.1109/edkcon56221.2022.10032912.

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2

Sung, W. L., and Y. Li. "Read Static Noise Margin Fluctuation Induced by Various Random Discrete Dopants on 6T SRAM with Nanowire FET (NWFET) and Hybrid FinFET-NWFET Cells." In 2018 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2018. http://dx.doi.org/10.7567/ssdm.2018.ps-1-26.

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3

Kumar, Deepak, Shamsher Singh, and Nitin Mittal. "Small-Signal RF response of dual metal gate (DMG) junctionless accumulation mode (JAM) nanowire FET (NWFET)." In PROCEEDINGS OF THE 4TH INTERNATIONAL COMPUTER SCIENCES AND INFORMATICS CONFERENCE (ICSIC 2022). AIP Publishing, 2023. http://dx.doi.org/10.1063/5.0143322.

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