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Journal articles on the topic 'NWFET-Nanowire FET'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Kumar, Deepak, and Shamsher Singh. "TRAP CHARGES INDUCED IMMUNITY IN DUAL METAL GATE (DMG) JUNCTIONLESS ACCUMULATION MODE (JAM) NANOWIRE FET (NWFET)." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1209–15. https://doi.org/10.21917/ijme.2021.0208.

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In this brief, we have done a comparative study of Single Metal Gate Junctionless Accumulation Mode Nanowire FET (SMG-JAM-NWFET) and Dual Metal Gate Junctionless Accumulation Mode Nanowire FET (DMG-JAM-NWFET) for their immunity against the trap induced charges. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the potential, current, transconductance and output conductance. Aberration in other parameters like drain characteristics, Subthreshold Slope, capacitances and cut-off

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2

Bharti and Poornima Mittal. "Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation." ECS Journal of Solid State Science and Technology 13, no. 1 (2024): 013004. http://dx.doi.org/10.1149/2162-8777/ad1c90.

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Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, g

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3

Choi, Yejoo, Jinwoong Lee, Jaehyuk Lim, Seungjun Moon, and Changhwan Shin. "Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET." Electronics 10, no. 16 (2021): 1899. http://dx.doi.org/10.3390/electronics10161899.

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In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS

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4

Bharti and Poornima Mittal. "Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis." Physica Scripta 99, no. 8 (2024): 086103. http://dx.doi.org/10.1088/1402-4896/ad63d4.

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Abstract An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into th

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5

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this r

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6

Bharti and Poornima Mittal. "Analytical modeling of fringe capacitance in opposite-doped core-shell junctionless nanowire FET." Engineering Research Express 7, no. 1 (2025): 015385. https://doi.org/10.1088/2631-8695/adc0ec.

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Abstract An analytical model of Oppositely Doped Core–Shell Junctionless Nanowire Field Effect Transistor (ODCS-JL-NWFET) using surface potential is proposed in this paper. The model incorporates the influence of fringe capacitance through the gate sidewall spacer on the potential distribution function. The analytical results align well with simulated outcomes across various ODCS-JL-NWFET physical parameters, such as threshold voltage, drain current, and subthreshold slope. Furthermore, the model illustrates the impact of channel length scaling on device parameters for different core thickness

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7

Ditshego, Nonofo M. J. "ZnO Nanowire Field Effect Transistor for Biosensing: A Review." Journal of Nano Research 60 (November 2019): 94–112. http://dx.doi.org/10.4028/www.scientific.net/jnanor.60.94.

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The last 19 years have seen intense research made on zinc oxide (ZnO) material mainly due to the ability of converting the natural n-type material into p-type. For a long time, the p-type state was impossible to attain and maintain. The review focuses on ways of improving the doped ZnO material which acts as a channel for nanowire field effect transistor (NWFET) and biosensor. The biosensor has specific binding which is called functionalisation achieved by attaching a variety of compounds on the designated sensing area. Reference electrodes and buffers are used as controllers. Top-down fabrica

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8

Thakur, Rajiv Ranjan, and Nidhi Chaturvedi. "Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications." Nano 16, no. 08 (2021): 2150096. http://dx.doi.org/10.1142/s179329202150096x.

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In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text]

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9

Song, Taigon. "Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm." IEEE Transactions on Nanotechnology 18 (2019): 240–51. http://dx.doi.org/10.1109/tnano.2019.2896362.

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10

Gong, Xiao, Kaizhen Han, Chen Sun, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.

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Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research developmen

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11

P, Vimala, and N. V. Rakshith. "Comparative Study of Multi-gate Nanowire Field Effect Transistor." Journal of Nanotechnology and Nano-Engineering 5, no. 3 (2019): 1–9. https://doi.org/10.5281/zenodo.3451862.

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<em>A silicon multi-gate nanowire simulation is presented in this paper. The simulation studies are conducted based on electrical parameters such as Current-Voltage (I-V) characteristics, Mid-channel conduction band profile and mid- channel charge density profile using Nanohub Multi-gate Nanowire FET simulator. These characterization studies are performed to investigate the performance of silicon nanowire based on different gate arrangements in the device. We have simulated the silicon nanowire field effect transistors (FETs) with multiple gates such as double, tri, pi, ome

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12

Wu, Chia-Yu, Han-Yi Cheng, Keng-Liang Ou, and Chi-Chang Wu. "Real-time sensing of hepatitis B virus X gene using an ultrasensitive nanowire field effect transistor." Journal of Polymer Engineering 34, no. 3 (2014): 273–77. http://dx.doi.org/10.1515/polyeng-2013-0216.

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Abstract Devices based on semiconducting nanowires (NWs) are functioning as highly sensitive and selective sensors for the label-free detection of biological and chemical species. This paper demonstrates a novel back-gated silicon NW field effect transistor (NWFET) for gene detection. The fabricated NWFET was employed as the biomolecule sensor for the early, real-time, and label-free screening of hepatitis B virus (HBV) X gene. The DNA fragment in HBV demonstrates the linearity from 10 fM to 1 pM, of which the detection limit is estimated to be about 3.2 fM. The obtained results also show that

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13

Gupta, Sumedha, Neeta Pandey, and R. S. Gupta. "Non‐uniform doping dependent electrical parameters of dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET)." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 37, no. 2 (2024). http://dx.doi.org/10.1002/jnm.3203.

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AbstractThis paper presents an analytical analysis of a dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET) possessing a horizontal‐like non‐uniform doping profile. The 2‐D electrostatic potential distribution is evaluated using Poisson's equation under the applicable boundary conditions. Also, the impact of straggle length parameter and the peak doping concentration upon the device behavior is also examined. For authenticating the obtained analytical outcomes, TCAD simulations were also performed. Both the results were contrasted and found to be in good ag

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14

Kumar, Deepak, and Shamsher Singh. "Analytical Modeling of Trap Charges Induced Dual Metal Junctionless Accumulation Mode Nanowire FET (DM-JAM-NWFET)." Silicon, October 8, 2021. http://dx.doi.org/10.1007/s12633-021-01402-y.

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15

Yirak, Mekonnen Getnet, and Rishu Chaujar. "Comparative Assessment of Trap Charges Effect on Triple Hybrid Metal Gate Dielectric Modulated Junctionless Gate All Around Nanowire FET‐Based Biosensor." Advances in Condensed Matter Physics 2025, no. 1 (2025). https://doi.org/10.1155/acmp/3744806.

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This work investigates how interface trap charges (ITCs) affect the performance of biosensors made from junctionless nanowire field‐effect transistors (NWFETs) with triple hybrid metal gate dielectric modulated gates. The subthreshold sensitivity of double and triple metal gate silicon NWFET biosensors was investigated using the SILVACO ATLAS‐TCAD simulation tool, emphasizing the impacts of positive and negative ITCs. Simulations examined the impact of uniformly immobilized biomolecules within the nanogap cavity region and evaluated key electrical characteristics, such as transconductance, swi

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16

Anupama, Sonam Rewari, and Neeta Pandey. "Numerical simulation and characterization of high-power Gallium Nitride based Junctionless Accumulation Mode Nanowire FET (GaN-JAM-NWFET) for small signal high frequency terahertz applications." AEU - International Journal of Electronics and Communications, November 2023, 155032. http://dx.doi.org/10.1016/j.aeue.2023.155032.

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17

Anguru, Chandana, Vamsi Krishna Aryasomayajula, Venkata Ramakrishna Kotha, et al. "Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective." ECS Journal of Solid State Science and Technology, December 14, 2023. http://dx.doi.org/10.1149/2162-8777/ad15a8.

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Abstract This paper presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO2 exhibits lowest IOFF of ~89.28%, and largest ION/IOFF ratio with better subthreshold performance of ~42.51% as compared to Air spacer at Lext= 7nm. In addition, TiO2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO2+Air spacer showed prodigious DC/Analog/RF performan

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